linux/drivers/tty/serial/8250/8250_fintek.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Probe for F81216A LPC to 4 UART
 *
 *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
 */
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pnp.h>
#include <linux/kernel.h>
#include <linux/serial_core.h>
#include <linux/irq.h>
#include  "8250.h"

#define ADDR_PORT …
#define DATA_PORT …
#define EXIT_KEY …
#define CHIP_ID1 …
#define CHIP_ID2 …
#define CHIP_ID_F81865 …
#define CHIP_ID_F81866 …
#define CHIP_ID_F81966 …
#define CHIP_ID_F81216AD …
#define CHIP_ID_F81216H …
#define CHIP_ID_F81216 …
#define VENDOR_ID1 …
#define VENDOR_ID1_VAL …
#define VENDOR_ID2 …
#define VENDOR_ID2_VAL …
#define IO_ADDR1 …
#define IO_ADDR2 …
#define LDN …

#define FINTEK_IRQ_MODE …
#define IRQ_SHARE …
#define IRQ_MODE_MASK …
#define IRQ_LEVEL_LOW …
#define IRQ_EDGE_HIGH …

/*
 * F81216H clock source register, the value and mask is the same with F81866,
 * but it's on F0h.
 *
 * Clock speeds for UART (register F0h)
 * 00: 1.8432MHz.
 * 01: 18.432MHz.
 * 10: 24MHz.
 * 11: 14.769MHz.
 */
#define RS485 …
#define RTS_INVERT …
#define RS485_URA …
#define RXW4C_IRA …
#define TXW4C_IRA …

#define FIFO_CTRL …
#define FIFO_MODE_MASK …
#define FIFO_MODE_128 …
#define RXFTHR_MODE_MASK …
#define RXFTHR_MODE_4X …

#define F81216_LDN_LOW …
#define F81216_LDN_HIGH …

/*
 * F81866/966 registers
 *
 * The IRQ setting mode of F81866/966 is not the same with F81216 series.
 *	Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
 *	Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
 *
 * Clock speeds for UART (register F2h)
 * 00: 1.8432MHz.
 * 01: 18.432MHz.
 * 10: 24MHz.
 * 11: 14.769MHz.
 */
#define F81866_IRQ_MODE …
#define F81866_IRQ_SHARE …
#define F81866_IRQ_MODE0 …

#define F81866_FIFO_CTRL …
#define F81866_IRQ_MODE1 …

#define F81866_LDN_LOW …
#define F81866_LDN_HIGH …

#define F81866_UART_CLK …
#define F81866_UART_CLK_MASK …
#define F81866_UART_CLK_1_8432MHZ …
#define F81866_UART_CLK_14_769MHZ …
#define F81866_UART_CLK_18_432MHZ …
#define F81866_UART_CLK_24MHZ …

struct fintek_8250 { … };

static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
{ … }

static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
{ … }

static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
			       u8 data)
{ … }

static int fintek_8250_enter_key(u16 base_port, u8 key)
{ … }

static void fintek_8250_exit_key(u16 base_port)
{ … }

static int fintek_8250_check_id(struct fintek_8250 *pdata)
{ … }

static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
				     int *max)
{ … }

static int fintek_8250_rs485_config(struct uart_port *port, struct ktermios *termios,
			      struct serial_rs485 *rs485)
{ … }

static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
{ … }

static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
{ … }

static void fintek_8250_set_termios(struct uart_port *port,
				    struct ktermios *termios,
				    const struct ktermios *old)
{ … }

static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
{ … }

static int probe_setup_port(struct fintek_8250 *pdata,
					struct uart_8250_port *uart)
{ … }

/* Only the first port supports delays */
static const struct serial_rs485 fintek_8250_rs485_supported_port0 = …;

static const struct serial_rs485 fintek_8250_rs485_supported = …;

static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
{ … }

int fintek_8250_probe(struct uart_8250_port *uart)
{ … }