// SPDX-License-Identifier: GPL-2.0 /* * 8250-core based driver for the OMAP internal UART * * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. * * Copyright (C) 2014 Sebastian Andrzej Siewior * */ #include <linux/atomic.h> #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> #include <linux/serial_8250.h> #include <linux/serial_reg.h> #include <linux/tty_flip.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/delay.h> #include <linux/pm_runtime.h> #include <linux/console.h> #include <linux/pm_qos.h> #include <linux/pm_wakeirq.h> #include <linux/dma-mapping.h> #include <linux/sys_soc.h> #include "8250.h" #define DEFAULT_CLK_SPEED … #define OMAP_UART_REGSHIFT … #define UART_ERRATA_i202_MDR1_ACCESS … #define OMAP_UART_WER_HAS_TX_WAKEUP … #define OMAP_DMA_TX_KICK … /* * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. * The same errata is applicable to AM335x and DRA7x processors too. */ #define UART_ERRATA_CLOCK_DISABLE … #define UART_HAS_EFR2 … #define UART_HAS_RHR_IT_DIS … #define UART_RX_TIMEOUT_QUIRK … #define UART_HAS_NATIVE_RS485 … #define OMAP_UART_FCR_RX_TRIG … #define OMAP_UART_FCR_TX_TRIG … /* SCR register bitmasks */ #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK … #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK … #define OMAP_UART_SCR_TX_EMPTY … #define OMAP_UART_SCR_DMAMODE_MASK … #define OMAP_UART_SCR_DMAMODE_1 … #define OMAP_UART_SCR_DMAMODE_CTL … /* MVR register bitmasks */ #define OMAP_UART_MVR_SCHEME_SHIFT … #define OMAP_UART_LEGACY_MVR_MAJ_MASK … #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT … #define OMAP_UART_LEGACY_MVR_MIN_MASK … #define OMAP_UART_MVR_MAJ_MASK … #define OMAP_UART_MVR_MAJ_SHIFT … #define OMAP_UART_MVR_MIN_MASK … /* SYSC register bitmasks */ #define OMAP_UART_SYSC_SOFTRESET … /* SYSS register bitmasks */ #define OMAP_UART_SYSS_RESETDONE … #define UART_TI752_TLR_TX … #define UART_TI752_TLR_RX … #define TRIGGER_TLR_MASK(x) … #define TRIGGER_FCR_MASK(x) … /* Enable XON/XOFF flow control on output */ #define OMAP_UART_SW_TX … /* Enable XON/XOFF flow control on input */ #define OMAP_UART_SW_RX … #define OMAP_UART_WER_MOD_WKUP … #define OMAP_UART_TX_WAKEUP_EN … #define TX_TRIGGER … #define RX_TRIGGER … #define OMAP_UART_TCR_RESTORE(x) … #define OMAP_UART_TCR_HALT(x) … #define UART_BUILD_REVISION(x, y) … #define OMAP_UART_REV_46 … #define OMAP_UART_REV_52 … #define OMAP_UART_REV_63 … /* Interrupt Enable Register 2 */ #define UART_OMAP_IER2 … #define UART_OMAP_IER2_RHR_IT_DIS … /* Mode Definition Register 3 */ #define UART_OMAP_MDR3 … #define UART_OMAP_MDR3_DIR_POL … #define UART_OMAP_MDR3_DIR_EN … /* Enhanced features register 2 */ #define UART_OMAP_EFR2 … #define UART_OMAP_EFR2_TIMEOUT_BEHAVE … /* RX FIFO occupancy indicator */ #define UART_OMAP_RX_LVL … /* Timeout low and High */ #define UART_OMAP_TO_L … #define UART_OMAP_TO_H … struct omap8250_priv { … }; struct omap8250_dma_params { … }; struct omap8250_platdata { … }; #ifdef CONFIG_SERIAL_8250_DMA static void omap_8250_rx_dma_flush(struct uart_8250_port *p); #else static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } #endif static u32 uart_read(struct omap8250_priv *priv, u32 reg) { … } /* * Called on runtime PM resume path from omap8250_restore_regs(), and * omap8250_set_mctrl(). */ static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) { … } static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) { … } /* * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) * The access to uart register after MDR1 Access * causes UART to corrupt data. * * Need a delay = * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) * give 10 times as much */ static void omap_8250_mdr1_errataset(struct uart_8250_port *up, struct omap8250_priv *priv) { … } static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, struct omap8250_priv *priv) { … } static void omap8250_update_scr(struct uart_8250_port *up, struct omap8250_priv *priv) { … } static void omap8250_update_mdr1(struct uart_8250_port *up, struct omap8250_priv *priv) { … } static void omap8250_restore_regs(struct uart_8250_port *up) { … } /* * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have * some differences in how we want to handle flow control. */ static void omap_8250_set_termios(struct uart_port *port, struct ktermios *termios, const struct ktermios *old) { … } /* same as 8250 except that we may have extra flow bits set in EFR */ static void omap_8250_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { … } static void omap_serial_fill_features_erratas(struct uart_8250_port *up, struct omap8250_priv *priv) { … } static void omap8250_uart_qos_work(struct work_struct *work) { … } #ifdef CONFIG_SERIAL_8250_DMA static int omap_8250_dma_handle_irq(struct uart_port *port); #endif static irqreturn_t omap8250_irq(int irq, void *dev_id) { … } static int omap_8250_startup(struct uart_port *port) { … } static void omap_8250_shutdown(struct uart_port *port) { … } static void omap_8250_throttle(struct uart_port *port) { … } static void omap_8250_unthrottle(struct uart_port *port) { … } static int omap8250_rs485_config(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485) { … } #ifdef CONFIG_SERIAL_8250_DMA static int omap_8250_rx_dma(struct uart_8250_port *p); /* Must be called while priv->rx_dma_lock is held */ static void __dma_rx_do_complete(struct uart_8250_port *p) { … } static void __dma_rx_complete(void *param) { … } static void omap_8250_rx_dma_flush(struct uart_8250_port *p) { … } static int omap_8250_rx_dma(struct uart_8250_port *p) { … } static int omap_8250_tx_dma(struct uart_8250_port *p); static void omap_8250_dma_tx_complete(void *param) { … } static int omap_8250_tx_dma(struct uart_8250_port *p) { … } static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) { … } static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) { … } static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) { … } /* * This is mostly serial8250_handle_irq(). We have a slightly different DMA * hoook for RX/TX and need different logic for them in the ISR. Therefore we * use the default routine in the non-DMA case and this one for with DMA. */ static int omap_8250_dma_handle_irq(struct uart_port *port) { … } static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) { … } #else static inline int omap_8250_rx_dma(struct uart_8250_port *p) { return -EINVAL; } #endif static int omap8250_no_handle_irq(struct uart_port *port) { … } static struct omap8250_dma_params am654_dma = …; static struct omap8250_dma_params am33xx_dma = …; static struct omap8250_platdata am654_platdata = …; static struct omap8250_platdata am33xx_platdata = …; static struct omap8250_platdata omap4_platdata = …; static const struct of_device_id omap8250_dt_ids[] = …; MODULE_DEVICE_TABLE(of, omap8250_dt_ids); static int omap8250_probe(struct platform_device *pdev) { … } static void omap8250_remove(struct platform_device *pdev) { … } static int omap8250_prepare(struct device *dev) { … } static void omap8250_complete(struct device *dev) { … } static int omap8250_suspend(struct device *dev) { … } static int omap8250_resume(struct device *dev) { … } static int omap8250_lost_context(struct uart_8250_port *up) { … } static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) { … } /* TODO: in future, this should happen via API in drivers/reset/ */ static int omap8250_soft_reset(struct device *dev) { … } static int omap8250_runtime_suspend(struct device *dev) { … } static int omap8250_runtime_resume(struct device *dev) { … } #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP static int __init omap8250_console_fixup(void) { … } console_initcall(omap8250_console_fixup); #endif static const struct dev_pm_ops omap8250_dev_pm_ops = …; static struct platform_driver omap8250_platform_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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