// SPDX-License-Identifier: GPL-2.0 /* * Probe module for 8250/16550-type PCI serial ports. * * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. * * Copyright (C) 2001 Russell King, All Rights Reserved. */ #undef DEBUG #include <linux/module.h> #include <linux/pci.h> #include <linux/string.h> #include <linux/kernel.h> #include <linux/math.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/tty.h> #include <linux/serial_reg.h> #include <linux/serial_core.h> #include <linux/8250_pci.h> #include <linux/bitops.h> #include <linux/bitfield.h> #include <asm/byteorder.h> #include <asm/io.h> #include "8250.h" #include "8250_pcilib.h" #define PCI_VENDOR_ID_SBSMODULARIO … #define PCI_SUBVENDOR_ID_SBSMODULARIO … #define PCI_DEVICE_ID_OCTPRO … #define PCI_SUBDEVICE_ID_OCTPRO232 … #define PCI_SUBDEVICE_ID_OCTPRO422 … #define PCI_SUBDEVICE_ID_POCTAL232 … #define PCI_SUBDEVICE_ID_POCTAL422 … #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 … #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 … #define PCI_VENDOR_ID_ADVANTECH … #define PCI_DEVICE_ID_INTEL_CE4100_UART … #define PCI_DEVICE_ID_ADVANTECH_PCI1600 … #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 … #define PCI_DEVICE_ID_ADVANTECH_PCI3620 … #define PCI_DEVICE_ID_ADVANTECH_PCI3618 … #define PCI_DEVICE_ID_ADVANTECH_PCIf618 … #define PCI_DEVICE_ID_TITAN_200I … #define PCI_DEVICE_ID_TITAN_400I … #define PCI_DEVICE_ID_TITAN_800I … #define PCI_DEVICE_ID_TITAN_800EH … #define PCI_DEVICE_ID_TITAN_800EHB … #define PCI_DEVICE_ID_TITAN_400EH … #define PCI_DEVICE_ID_TITAN_100E … #define PCI_DEVICE_ID_TITAN_200E … #define PCI_DEVICE_ID_TITAN_400E … #define PCI_DEVICE_ID_TITAN_800E … #define PCI_DEVICE_ID_TITAN_200EI … #define PCI_DEVICE_ID_TITAN_200EISI … #define PCI_DEVICE_ID_TITAN_200V3 … #define PCI_DEVICE_ID_TITAN_400V3 … #define PCI_DEVICE_ID_TITAN_410V3 … #define PCI_DEVICE_ID_TITAN_800V3 … #define PCI_DEVICE_ID_TITAN_800V3B … #define PCI_DEVICE_ID_OXSEMI_16PCI958 … #define PCIE_DEVICE_ID_NEO_2_OX_IBM … #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA … #define PCI_DEVICE_ID_INTEL_PATSBURG_KT … #define PCI_VENDOR_ID_WCH … #define PCI_DEVICE_ID_WCH_CH352_2S … #define PCI_DEVICE_ID_WCH_CH353_4S … #define PCI_DEVICE_ID_WCH_CH353_2S1PF … #define PCI_DEVICE_ID_WCH_CH353_1S1P … #define PCI_DEVICE_ID_WCH_CH353_2S1P … #define PCI_DEVICE_ID_WCH_CH355_4S … #define PCI_VENDOR_ID_AGESTAR … #define PCI_DEVICE_ID_AGESTAR_9375 … #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE … #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 … #define PCIE_VENDOR_ID_WCH … #define PCIE_DEVICE_ID_WCH_CH382_2S1P … #define PCIE_DEVICE_ID_WCH_CH384_4S … #define PCIE_DEVICE_ID_WCH_CH384_8S … #define PCIE_DEVICE_ID_WCH_CH382_2S … #define PCI_DEVICE_ID_MOXA_CP102E … #define PCI_DEVICE_ID_MOXA_CP102EL … #define PCI_DEVICE_ID_MOXA_CP102N … #define PCI_DEVICE_ID_MOXA_CP104EL_A … #define PCI_DEVICE_ID_MOXA_CP104N … #define PCI_DEVICE_ID_MOXA_CP112N … #define PCI_DEVICE_ID_MOXA_CP114EL … #define PCI_DEVICE_ID_MOXA_CP114N … #define PCI_DEVICE_ID_MOXA_CP116E_A_A … #define PCI_DEVICE_ID_MOXA_CP116E_A_B … #define PCI_DEVICE_ID_MOXA_CP118EL_A … #define PCI_DEVICE_ID_MOXA_CP118E_A_I … #define PCI_DEVICE_ID_MOXA_CP132EL … #define PCI_DEVICE_ID_MOXA_CP132N … #define PCI_DEVICE_ID_MOXA_CP134EL_A … #define PCI_DEVICE_ID_MOXA_CP134N … #define PCI_DEVICE_ID_MOXA_CP138E_A … #define PCI_DEVICE_ID_MOXA_CP168EL_A … /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 … #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 … /* * init function returns: * > 0 - number of ports * = 0 - use board->num_ports * < 0 - error */ struct pci_serial_quirk { … }; struct f815xxa_data { … }; struct serial_private { … }; #define PCI_DEVICE_ID_HPE_PCI_SERIAL … static const struct pci_device_id pci_use_msi[] = …; static int pci_default_setup(struct serial_private*, const struct pciserial_board*, struct uart_8250_port *, int); static void moan_device(const char *str, struct pci_dev *dev) { … } static int setup_port(struct serial_private *priv, struct uart_8250_port *port, u8 bar, unsigned int offset, int regshift) { … } /* * ADDI-DATA GmbH communication cards <[email protected]> */ static int addidata_apci7800_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * AFAVLAB uses a different mixture of BARs and offsets * Not that ugly ;) -- HW */ static int afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * HP's Remote Management Console. The Diva chip came in several * different versions. N-class, L2000 and A500 have two Diva chips, each * with 3 UARTs (the third UART on the second chip is unused). Superdome * and Keystone have one Diva chip with 3 UARTs. Some later machines have * one Diva chip, but it has been expanded to 5 UARTs. */ static int pci_hp_diva_init(struct pci_dev *dev) { … } /* * HP's Diva chip puts the 4th/5th serial port further out, and * some serial ports are supposed to be hidden on certain models. */ static int pci_hp_diva_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * Added for EKF Intel i960 serial boards */ static int pci_inteli960ni_init(struct pci_dev *dev) { … } /* * Some PCI serial cards using the PLX 9050 PCI interface chip require * that the card interrupt be explicitly enabled or disabled. This * seems to be mainly needed on card using the PLX which also use I/O * mapped memory. */ static int pci_plx9050_init(struct pci_dev *dev) { … } static void pci_plx9050_exit(struct pci_dev *dev) { … } #define NI8420_INT_ENABLE_REG … #define NI8420_INT_ENABLE_BIT … static void pci_ni8420_exit(struct pci_dev *dev) { … } /* MITE registers */ #define MITE_IOWBSR1 … #define MITE_IOWCR1 … #define MITE_LCIMR1 … #define MITE_LCIMR2 … #define MITE_LCIMR2_CLR_CPU_IE … static void pci_ni8430_exit(struct pci_dev *dev) { … } /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ static int sbs_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * This does initialization for PMC OCTALPRO cards: * maps the device memory, resets the UARTs (needed, bc * if the module is removed and inserted again, the card * is in the sleep mode) and enables global interrupt. */ /* global control register offset for SBS PMC-OctalPro */ #define OCT_REG_CR_OFF … static int sbs_init(struct pci_dev *dev) { … } /* * Disables the global interrupt of PMC-OctalPro */ static void sbs_exit(struct pci_dev *dev) { … } /* * SIIG serial cards have an PCI interface chip which also controls * the UART clocking frequency. Each UART can be clocked independently * (except cards equipped with 4 UARTs) and initial clocking settings * are stored in the EEPROM chip. It can cause problems because this * version of serial driver doesn't support differently clocked UART's * on single PCI card. To prevent this, initialization functions set * high frequency clocking for all UART's on given card. It is safe (I * hope) because it doesn't touch EEPROM settings to prevent conflicts * with other OSes (like M$ DOS). * * SIIG support added by Andrey Panin <[email protected]>, 10/1999 * * There is two family of SIIG serial cards with different PCI * interface chip and different configuration methods: * - 10x cards have control registers in IO and/or memory space; * - 20x cards have control registers in standard PCI configuration space. * * Note: all 10x cards have PCI device ids 0x10.. * all 20x cards have PCI device ids 0x20.. * * There are also Quartet Serial cards which use Oxford Semiconductor * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. * * Note: some SIIG cards are probed by the parport_serial object. */ #define PCI_DEVICE_ID_SIIG_1S_10x … #define PCI_DEVICE_ID_SIIG_2S_10x … static int pci_siig10x_init(struct pci_dev *dev) { … } #define PCI_DEVICE_ID_SIIG_2S_20x … #define PCI_DEVICE_ID_SIIG_2S1P_20x … static int pci_siig20x_init(struct pci_dev *dev) { … } static int pci_siig_init(struct pci_dev *dev) { … } static int pci_siig_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * Timedia has an explosion of boards, and to avoid the PCI table from * growing *huge*, we use this function to collapse some 70 entries * in the PCI table into one, for sanity's and compactness's sake. */ static const unsigned short timedia_single_port[] = …; static const unsigned short timedia_dual_port[] = …; static const unsigned short timedia_quad_port[] = …; static const unsigned short timedia_eight_port[] = …; static const struct timedia_struct { … } timedia_data[] = …; /* * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of * listing them individually, this driver merely grabs them all with * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, * and should be left free to be claimed by parport_serial instead. */ static int pci_timedia_probe(struct pci_dev *dev) { … } static int pci_timedia_init(struct pci_dev *dev) { … } /* * Timedia/SUNIX uses a mixture of BARs and offsets * Ugh, this is ugly as all hell --- TYT */ static int pci_timedia_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * Some Titan cards are also a little weird */ static int titan_400l_800l_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_xircom_init(struct pci_dev *dev) { … } static int pci_ni8420_init(struct pci_dev *dev) { … } #define MITE_IOWBSR1_WSIZE … #define MITE_IOWBSR1_WIN_OFFSET … #define MITE_IOWBSR1_WENAB … #define MITE_LCIMR1_IO_IE_0 … #define MITE_LCIMR2_SET_CPU_IE … #define MITE_IOWCR1_RAMSEL_MASK … static int pci_ni8430_init(struct pci_dev *dev) { … } /* UART Port Control Register */ #define NI8430_PORTCON … #define NI8430_PORTCON_TXVR_ENABLE … static int pci_ni8430_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_netmos_9900_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* the 99xx series comes with a range of device IDs and a variety * of capabilities: * * 9900 has varying capabilities and can cascade to sub-controllers * (cascading should be purely internal) * 9904 is hardwired with 4 serial ports * 9912 and 9922 are hardwired with 2 serial ports */ static int pci_netmos_9900_numports(struct pci_dev *dev) { … } static int pci_netmos_init(struct pci_dev *dev) { … } /* * These chips are available with optionally one parallel port and up to * two serial ports. Unfortunately they all have the same product id. * * Basic configuration is done over a region of 32 I/O ports. The base * ioport is called INTA or INTC, depending on docs/other drivers. * * The region of the 32 I/O ports is configured in POSIO0R... */ /* registers */ #define ITE_887x_MISCR … #define ITE_887x_INTCBAR … #define ITE_887x_UARTBAR … #define ITE_887x_PS0BAR … #define ITE_887x_POSIO0 … /* I/O space size */ #define ITE_887x_IOSIZE … /* I/O space size (bits 26-24; 8 bytes = 011b) */ #define ITE_887x_POSIO_IOSIZE_8 … /* I/O space size (bits 26-24; 32 bytes = 101b) */ #define ITE_887x_POSIO_IOSIZE_32 … /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ #define ITE_887x_POSIO_SPEED … /* enable IO_Space bit */ #define ITE_887x_POSIO_ENABLE … /* inta_addr are the configuration addresses of the ITE */ static const short inta_addr[] = …; static int pci_ite887x_init(struct pci_dev *dev) { … } static void pci_ite887x_exit(struct pci_dev *dev) { … } /* * Oxford Semiconductor Inc. * Check if an OxSemi device is part of the Tornado range of devices. */ #define PCI_VENDOR_ID_ENDRUN … #define PCI_DEVICE_ID_ENDRUN_1588 … static bool pci_oxsemi_tornado_p(struct pci_dev *dev) { … } /* * Determine the number of ports available on a Tornado device. */ static int pci_oxsemi_tornado_init(struct pci_dev *dev) { … } /* Tornado-specific constants for the TCR and CPR registers; see below. */ #define OXSEMI_TORNADO_TCR_MASK … #define OXSEMI_TORNADO_CPR_MASK … #define OXSEMI_TORNADO_CPR_MIN … #define OXSEMI_TORNADO_CPR_DEF … /* * Determine the oversampling rate, the clock prescaler, and the clock * divisor for the requested baud rate. The clock rate is 62.5 MHz, * which is four times the baud base, and the prescaler increments in * steps of 1/8. Therefore to make calculations on integers we need * to use a scaled clock rate, which is the baud base multiplied by 32 * (or our assumed UART clock rate multiplied by 2). * * The allowed oversampling rates are from 4 up to 16 inclusive (values * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows * values between 1.000 and 63.875 inclusive (operation for values from * 0.000 to 0.875 has not been specified). The clock divisor is the usual * unsigned 16-bit integer. * * For the most accurate baud rate we use a table of predetermined * oversampling rates and clock prescalers that records all possible * products of the two parameters in the range from 4 up to 255 inclusive, * and additionally 335 for the 1500000bps rate, with the prescaler scaled * by 8. The table is sorted by the decreasing value of the oversampling * rate and ties are resolved by sorting by the decreasing value of the * product. This way preference is given to higher oversampling rates. * * We iterate over the table and choose the product of an oversampling * rate and a clock prescaler that gives the lowest integer division * result deviation, or if an exact integer divider is found we stop * looking for it right away. We do some fixup if the resulting clock * divisor required would be out of its unsigned 16-bit integer range. * * Finally we abuse the supposed fractional part returned to encode the * 4-bit value of the oversampling rate and the 9-bit value of the clock * prescaler which will end up in the TCR and CPR/CPR2 registers. */ static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, unsigned int baud, unsigned int *frac) { … } /* * Set the oversampling rate in the transmitter clock cycle register (TCR), * the clock prescaler in the clock prescaler register (CPR and CPR2), and * the clock divisor in the divisor latch (DLL and DLM). Note that for * backwards compatibility any write to CPR clears CPR2 and therefore CPR * has to be written first, followed by CPR2, which occupies the location * of CKS used with earlier UART designs. */ static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, unsigned int baud, unsigned int quot, unsigned int quot_frac) { … } /* * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. */ static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, unsigned int mctrl) { … } /* * We require EFR features for clock programming, so set UPF_FULL_PROBE * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. */ static int pci_oxsemi_tornado_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *up, int idx) { … } #define QPCR_TEST_FOR1 … #define QPCR_TEST_GET1 … #define QPCR_TEST_FOR2 … #define QPCR_TEST_GET2 … #define QPCR_TEST_FOR3 … #define QPCR_TEST_GET3 … #define QPCR_TEST_FOR4 … #define QPCR_TEST_GET4 … #define QOPR_CLOCK_X1 … #define QOPR_CLOCK_X2 … #define QOPR_CLOCK_X4 … #define QOPR_CLOCK_X8 … #define QOPR_CLOCK_RATE_MASK … /* Quatech devices have their own extra interface features */ static struct pci_device_id quatech_cards[] = …; static int pci_quatech_rqopr(struct uart_8250_port *port) { … } static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) { … } static int pci_quatech_rqmcr(struct uart_8250_port *port) { … } static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) { … } static int pci_quatech_has_qmcr(struct uart_8250_port *port) { … } static int pci_quatech_test(struct uart_8250_port *port) { … } static int pci_quatech_clock(struct uart_8250_port *port) { … } static int pci_quatech_rs422(struct uart_8250_port *port) { … } static int pci_quatech_init(struct pci_dev *dev) { … } static int pci_quatech_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_default_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int ce4100_serial_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_omegapci_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_brcm_trumanage_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* RTS will control by MCR if this bit is 0 */ #define FINTEK_RTS_CONTROL_BY_HW … /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ #define FINTEK_RTS_INVERT … /* We should do proper H/W transceiver setting before change to RS485 mode */ static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485) { … } static const struct serial_rs485 pci_fintek_rs485_supported = …; static int pci_fintek_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_fintek_init(struct pci_dev *dev) { … } static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) { … } static int pci_fintek_f815xxa_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_fintek_f815xxa_init(struct pci_dev *dev) { … } static int skip_tx_en_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static void kt_handle_break(struct uart_port *p) { … } static unsigned int kt_serial_in(struct uart_port *p, int offset) { … } static int kt_serial_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_eg20t_init(struct pci_dev *dev) { … } static int pci_wch_ch353_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_wch_ch355_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } static int pci_wch_ch38x_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } #define CH384_XINT_ENABLE_REG … #define CH384_XINT_ENABLE_BIT … static int pci_wch_ch38x_init(struct pci_dev *dev) { … } static void pci_wch_ch38x_exit(struct pci_dev *dev) { … } static int pci_sunix_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } #define MOXA_PUART_GPIO_EN … #define MOXA_PUART_GPIO_OUT … #define MOXA_GPIO_PIN2 … #define MOXA_RS232 … #define MOXA_RS422 … #define MOXA_RS485_4W … #define MOXA_RS485_2W … #define MOXA_UIR_OFFSET … #define MOXA_EVEN_RS_MASK … #define MOXA_ODD_RS_MASK … enum { … }; static unsigned short moxa_get_nports(unsigned short device) { … } static bool pci_moxa_is_mini_pcie(unsigned short device) { … } static unsigned int pci_moxa_supported_rs(struct pci_dev *dev) { … } static int pci_moxa_set_interface(const struct pci_dev *dev, unsigned int port_idx, u8 mode) { … } static int pci_moxa_init(struct pci_dev *dev) { … } static int pci_moxa_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) { … } /* * Master list of serial port init/setup/exit quirks. * This does not describe the general nature of the port. * (ie, baud base, number and location of ports, etc) * * This list is ordered alphabetically by vendor then device. * Specific entries must come before more generic entries. */ static struct pci_serial_quirk pci_serial_quirks[] = …; static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) { … } static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) { … } /* * This is the configuration table for all of the PCI serial boards * which we support. It is directly indexed by the pci_board_num_t enum * value, which is encoded in the pci_device_id PCI probe table's * driver_data member. * * The makeup of these names are: * pbn_bn{_bt}_n_baud{_offsetinhex} * * bn = PCI BAR number * bt = Index using PCI BARs * n = number of serial ports * baud = baud rate * offsetinhex = offset for each sequential port (in hex) * * This table is sorted by (in order): bn, bt, baud, offsetindex, n. * * Please note: in theory if n = 1, _bt infix should make no difference. * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 */ enum pci_board_num_t { … }; /* * uart_offset - the space between channels * reg_shift - describes how the UART registers are mapped * to PCI memory by the card. * For example IER register on SBS, Inc. PMC-OctPro is located at * offset 0x10 from the UART base, while UART_IER is defined as 1 * in include/linux/serial_reg.h, * see first lines of serial_in() and serial_out() in 8250.c */ static struct pciserial_board pci_boards[] = …; #define REPORT_CONFIG(option) … #define REPORT_8250_CONFIG(option) … static const struct pci_device_id blacklist[] = …; static int serial_pci_is_class_communication(struct pci_dev *dev) { … } /* * Given a complete unknown PCI device, try to use some heuristics to * guess what the configuration might be, based on the pitiful PCI * serial specs. Returns 0 on success, -ENODEV on failure. */ static int serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) { … } static inline int serial_pci_matches(const struct pciserial_board *board, const struct pciserial_board *guessed) { … } struct serial_private * pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) { … } EXPORT_SYMBOL_GPL(…); static void pciserial_detach_ports(struct serial_private *priv) { … } void pciserial_remove_ports(struct serial_private *priv) { … } EXPORT_SYMBOL_GPL(…); void pciserial_suspend_ports(struct serial_private *priv) { … } EXPORT_SYMBOL_GPL(…); void pciserial_resume_ports(struct serial_private *priv) { … } EXPORT_SYMBOL_GPL(…); /* * Probe one serial board. Unfortunately, there is no rhyme nor reason * to the arrangement of serial ports on a PCI card. */ static int pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) { … } static void pciserial_remove_one(struct pci_dev *dev) { … } #ifdef CONFIG_PM_SLEEP static int pciserial_suspend_one(struct device *dev) { … } static int pciserial_resume_one(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, pciserial_resume_one); static const struct pci_device_id serial_pci_tbl[] = …; static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, pci_channel_state_t state) { … } static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) { … } static void serial8250_io_resume(struct pci_dev *dev) { … } static const struct pci_error_handlers serial8250_err_handler = …; static struct pci_driver serial_pci_driver = …; module_pci_driver(…) …; MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …; MODULE_DEVICE_TABLE(pci, serial_pci_tbl); MODULE_IMPORT_NS(…);
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