// SPDX-License-Identifier: GPL-2.0 /* * Probe module for 8250/16550-type MCHP PCI serial ports. * * Based on drivers/tty/serial/8250/8250_pci.c, * * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. */ #include <linux/array_size.h> #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/circ_buf.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/gfp_types.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/minmax.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/overflow.h> #include <linux/pci.h> #include <linux/pm.h> #include <linux/serial_core.h> #include <linux/serial_reg.h> #include <linux/serial_8250.h> #include <linux/spinlock.h> #include <linux/string.h> #include <linux/time.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/types.h> #include <linux/units.h> #include <asm/byteorder.h> #include "8250.h" #include "8250_pcilib.h" #define PCI_DEVICE_ID_EFAR_PCI12000 … #define PCI_DEVICE_ID_EFAR_PCI11010 … #define PCI_DEVICE_ID_EFAR_PCI11101 … #define PCI_DEVICE_ID_EFAR_PCI11400 … #define PCI_DEVICE_ID_EFAR_PCI11414 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 … #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 … #define PCI_SUBDEVICE_ID_EFAR_PCI12000 … #define PCI_SUBDEVICE_ID_EFAR_PCI11010 … #define PCI_SUBDEVICE_ID_EFAR_PCI11101 … #define PCI_SUBDEVICE_ID_EFAR_PCI11400 … #define PCI_SUBDEVICE_ID_EFAR_PCI11414 … #define UART_SYSTEM_ADDR_BASE … #define UART_DEV_REV_REG … #define UART_DEV_REV_MASK … #define UART_SYSLOCK_REG … #define UART_SYSLOCK … #define SYSLOCK_SLEEP_TIMEOUT … #define SYSLOCK_RETRY_CNT … #define UART_RX_BYTE_FIFO … #define UART_TX_BYTE_FIFO … #define UART_FIFO_CTL … #define UART_ACTV_REG … #define UART_BLOCK_SET_ACTIVE … #define UART_PCI_CTRL_REG … #define UART_PCI_CTRL_SET_MULTIPLE_MSI … #define UART_PCI_CTRL_D3_CLK_ENABLE … #define ADCL_CFG_REG … #define ADCL_CFG_POL_SEL … #define ADCL_CFG_PIN_SEL … #define ADCL_CFG_EN … #define UART_BIT_SAMPLE_CNT_8 … #define UART_BIT_SAMPLE_CNT_16 … #define BAUD_CLOCK_DIV_INT_MSK … #define ADCL_CFG_RTS_DELAY_MASK … #define UART_WAKE_REG … #define UART_WAKE_MASK_REG … #define UART_WAKE_N_PIN … #define UART_WAKE_NCTS … #define UART_WAKE_INT … #define UART_WAKE_SRCS … #define UART_BAUD_CLK_DIVISOR_REG … #define FRAC_DIV_CFG_REG … #define UART_RESET_REG … #define UART_RESET_D3_RESET_DISABLE … #define UART_BURST_STATUS_REG … #define UART_TX_BURST_FIFO … #define UART_RX_BURST_FIFO … #define UART_BIT_DIVISOR_8 … #define UART_BIT_DIVISOR_16 … #define UART_BAUD_4MBPS … #define MAX_PORTS … #define PORT_OFFSET … #define RX_BUF_SIZE … #define UART_BYTE_SIZE … #define UART_BURST_SIZE … #define UART_BST_STAT_RX_COUNT_MASK … #define UART_BST_STAT_TX_COUNT_MASK … #define UART_BST_STAT_IIR_INT_PEND … #define UART_LSR_OVERRUN_ERR_CLR … #define UART_BST_STAT_LSR_RX_MASK … #define UART_BST_STAT_LSR_RX_ERR_MASK … #define UART_BST_STAT_LSR_OVERRUN_ERR … #define UART_BST_STAT_LSR_PARITY_ERR … #define UART_BST_STAT_LSR_FRAME_ERR … #define UART_BST_STAT_LSR_THRE … struct pci1xxxx_8250 { … }; static const struct serial_rs485 pci1xxxx_rs485_supported = …; static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) { … } static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) { … } static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) { … } static const int logical_to_physical_port_idx[][MAX_PORTS] = …; static int pci1xxxx_get_num_ports(struct pci_dev *dev) { … } static unsigned int pci1xxxx_get_divisor(struct uart_port *port, unsigned int baud, unsigned int *frac) { … } static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, unsigned int quot, unsigned int frac) { … } static int pci1xxxx_rs485_config(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485) { … } static u32 pci1xxxx_read_burst_status(struct uart_port *port) { … } static void pci1xxxx_process_read_data(struct uart_port *port, unsigned char *rx_buff, u32 *buff_index, u32 *valid_byte_count) { … } static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) { … } static void pci1xxxx_process_write_data(struct uart_port *port, int *data_empty_count, u32 *valid_byte_count) { … } static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) { … } static int pci1xxxx_handle_irq(struct uart_port *port) { … } static bool pci1xxxx_port_suspend(int line) { … } static void pci1xxxx_port_resume(int line) { … } static int pci1xxxx_suspend(struct device *dev) { … } static int pci1xxxx_resume(struct device *dev) { … } static int pci1xxxx_setup(struct pci_dev *pdev, struct uart_8250_port *port, int port_idx, int rev) { … } static unsigned int pci1xxxx_get_max_port(int subsys_dev) { … } static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) { … } static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv) { … } static int pci1xxxx_serial_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static void pci1xxxx_serial_remove(struct pci_dev *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); static const struct pci_device_id pci1xxxx_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); static struct pci_driver pci1xxxx_pci_driver = …; module_pci_driver(…) …; static_assert(…); MODULE_IMPORT_NS(…); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux