// SPDX-License-Identifier: GPL-2.0+ /* * Application UART driver for: * Freescale STMP37XX/STMP378X * Alphascale ASM9260 * * Author: dmitry pervushin <[email protected]> * * Copyright 2014 Oleksij Rempel <[email protected]> * Provide Alphascale ASM9260 support. * Copyright 2008-2010 Freescale Semiconductor, Inc. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. */ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/init.h> #include <linux/console.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/wait.h> #include <linux/tty.h> #include <linux/tty_driver.h> #include <linux/tty_flip.h> #include <linux/serial.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/device.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/gpio/consumer.h> #include <linux/err.h> #include <linux/irq.h> #include "serial_mctrl_gpio.h" #define MXS_AUART_PORTS … #define MXS_AUART_FIFO_SIZE … #define SET_REG … #define CLR_REG … #define TOG_REG … #define AUART_CTRL0 … #define AUART_CTRL1 … #define AUART_CTRL2 … #define AUART_LINECTRL … #define AUART_LINECTRL2 … #define AUART_INTR … #define AUART_DATA … #define AUART_STAT … #define AUART_DEBUG … #define AUART_VERSION … #define AUART_AUTOBAUD … #define AUART_CTRL0_SFTRST … #define AUART_CTRL0_CLKGATE … #define AUART_CTRL0_RXTO_ENABLE … #define AUART_CTRL0_RXTIMEOUT(v) … #define AUART_CTRL0_XFER_COUNT(v) … #define AUART_CTRL1_XFER_COUNT(v) … #define AUART_CTRL2_DMAONERR … #define AUART_CTRL2_TXDMAE … #define AUART_CTRL2_RXDMAE … #define AUART_CTRL2_CTSEN … #define AUART_CTRL2_RTSEN … #define AUART_CTRL2_RTS … #define AUART_CTRL2_RXE … #define AUART_CTRL2_TXE … #define AUART_CTRL2_UARTEN … #define AUART_LINECTRL_BAUD_DIV_MAX … #define AUART_LINECTRL_BAUD_DIV_MIN … #define AUART_LINECTRL_BAUD_DIVINT_SHIFT … #define AUART_LINECTRL_BAUD_DIVINT_MASK … #define AUART_LINECTRL_BAUD_DIVINT(v) … #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT … #define AUART_LINECTRL_BAUD_DIVFRAC_MASK … #define AUART_LINECTRL_BAUD_DIVFRAC(v) … #define AUART_LINECTRL_SPS … #define AUART_LINECTRL_WLEN_MASK … #define AUART_LINECTRL_WLEN(v) … #define AUART_LINECTRL_FEN … #define AUART_LINECTRL_STP2 … #define AUART_LINECTRL_EPS … #define AUART_LINECTRL_PEN … #define AUART_LINECTRL_BRK … #define AUART_INTR_RTIEN … #define AUART_INTR_TXIEN … #define AUART_INTR_RXIEN … #define AUART_INTR_CTSMIEN … #define AUART_INTR_RTIS … #define AUART_INTR_TXIS … #define AUART_INTR_RXIS … #define AUART_INTR_CTSMIS … #define AUART_STAT_BUSY … #define AUART_STAT_CTS … #define AUART_STAT_TXFE … #define AUART_STAT_TXFF … #define AUART_STAT_RXFE … #define AUART_STAT_OERR … #define AUART_STAT_BERR … #define AUART_STAT_PERR … #define AUART_STAT_FERR … #define AUART_STAT_RXCOUNT_MASK … /* * Start of Alphascale asm9260 defines * This list contains only differences of existing bits * between imx2x and asm9260 */ #define ASM9260_HW_CTRL0 … /* * RW. Tell the UART to execute the RX DMA Command. The * UART will clear this bit at the end of receive execution. */ #define ASM9260_BM_CTRL0_RXDMA_RUN … /* RW. 0 use FIFO for status register; 1 use DMA */ #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS … /* * RW. RX TIMEOUT Enable. Valid for FIFO and DMA. * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA * operation. If this bit is set to 1, a receive timeout will cause the receive * DMA logic to terminate by filling the remaining DMA bytes with garbage data. */ #define ASM9260_BM_CTRL0_RXTO_ENABLE … /* * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before * asserting timeout on the RX input. If the RXFIFO is not empty and the RX * input is idle, then the watchdog counter will decrement each bit-time. Note * 7-bit-time is added to the programmed value, so a value of zero will set * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also * note that the counter is reloaded at the end of each frame, so if the frame * is 10 bits long and the timeout counter value is zero, then timeout will * occur (when FIFO is not empty) even if the RX input is not idle. The default * value is 0x3 (31 bit-time). */ #define ASM9260_BM_CTRL0_RXTO_MASK … /* TIMEOUT = (100*7+1)*(1/BAUD) */ #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT … /* TX ctrl register */ #define ASM9260_HW_CTRL1 … /* * RW. Tell the UART to execute the TX DMA Command. The * UART will clear this bit at the end of transmit execution. */ #define ASM9260_BM_CTRL1_TXDMA_RUN … #define ASM9260_HW_CTRL2 … /* * RW. Receive Interrupt FIFO Level Select. * The trigger points for the receive interrupt are as follows: * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries. * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. */ #define ASM9260_BM_CTRL2_RXIFLSEL … #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL … /* RW. Same as RXIFLSEL */ #define ASM9260_BM_CTRL2_TXIFLSEL … #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL … /* RW. Set DTR. When this bit is 1, the output is 0. */ #define ASM9260_BM_CTRL2_DTR … /* RW. Loop Back Enable */ #define ASM9260_BM_CTRL2_LBE … #define ASM9260_BM_CTRL2_PORT_ENABLE … #define ASM9260_HW_LINECTRL … /* * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this * bit is cleared stick parity is disabled. */ #define ASM9260_BM_LCTRL_SPS … /* RW. Word length */ #define ASM9260_BM_LCTRL_WLEN … #define ASM9260_BM_LCTRL_CHRL_5 … #define ASM9260_BM_LCTRL_CHRL_6 … #define ASM9260_BM_LCTRL_CHRL_7 … #define ASM9260_BM_LCTRL_CHRL_8 … /* * Interrupt register. * contains the interrupt enables and the interrupt status bits */ #define ASM9260_HW_INTR … /* Tx FIFO EMPTY Raw Interrupt enable */ #define ASM9260_BM_INTR_TFEIEN … /* Overrun Error Interrupt Enable. */ #define ASM9260_BM_INTR_OEIEN … /* Break Error Interrupt Enable. */ #define ASM9260_BM_INTR_BEIEN … /* Parity Error Interrupt Enable. */ #define ASM9260_BM_INTR_PEIEN … /* Framing Error Interrupt Enable. */ #define ASM9260_BM_INTR_FEIEN … /* nUARTDSR Modem Interrupt Enable. */ #define ASM9260_BM_INTR_DSRMIEN … /* nUARTDCD Modem Interrupt Enable. */ #define ASM9260_BM_INTR_DCDMIEN … /* nUARTRI Modem Interrupt Enable. */ #define ASM9260_BM_INTR_RIMIEN … /* Auto-Boud Timeout */ #define ASM9260_BM_INTR_ABTO … #define ASM9260_BM_INTR_ABEO … /* Tx FIFO EMPTY Raw Interrupt state */ #define ASM9260_BM_INTR_TFEIS … /* Overrun Error */ #define ASM9260_BM_INTR_OEIS … /* Break Error */ #define ASM9260_BM_INTR_BEIS … /* Parity Error */ #define ASM9260_BM_INTR_PEIS … /* Framing Error */ #define ASM9260_BM_INTR_FEIS … #define ASM9260_BM_INTR_DSRMIS … #define ASM9260_BM_INTR_DCDMIS … #define ASM9260_BM_INTR_RIMIS … /* * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a * time. In PIO mode, only one character can be accessed at a time. The status * register contains the receive data flags and valid bits. */ #define ASM9260_HW_DATA … #define ASM9260_HW_STAT … /* RO. If 1, UARTAPP is present in this product. */ #define ASM9260_BM_STAT_PRESENT … /* RO. If 1, HISPEED is present in this product. */ #define ASM9260_BM_STAT_HISPEED … /* RO. Receive FIFO Full. */ #define ASM9260_BM_STAT_RXFULL … /* RO. The UART Debug Register contains the state of the DMA signals. */ #define ASM9260_HW_DEBUG … /* DMA Command Run Status */ #define ASM9260_BM_DEBUG_TXDMARUN … #define ASM9260_BM_DEBUG_RXDMARUN … /* DMA Command End Status */ #define ASM9260_BM_DEBUG_TXCMDEND … #define ASM9260_BM_DEBUG_RXCMDEND … /* DMA Request Status */ #define ASM9260_BM_DEBUG_TXDMARQ … #define ASM9260_BM_DEBUG_RXDMARQ … #define ASM9260_HW_ILPR … #define ASM9260_HW_RS485CTRL … /* * RW. This bit reverses the polarity of the direction control signal on the RTS * (or DTR) pin. * If 0, The direction control pin will be driven to logic ‘0’ when the * transmitter has data to be sent. It will be driven to logic ‘1’ after the * last bit of data has been transmitted. */ #define ASM9260_BM_RS485CTRL_ONIV … /* RW. Enable Auto Direction Control. */ #define ASM9260_BM_RS485CTRL_DIR_CTRL … /* * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control. * If 1 and DIR_CTRL = 1, pin DTR is used for direction control. */ #define ASM9260_BM_RS485CTRL_PINSEL … /* RW. Enable Auto Address Detect (AAD). */ #define ASM9260_BM_RS485CTRL_AADEN … /* RW. Disable receiver. */ #define ASM9260_BM_RS485CTRL_RXDIS … /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */ #define ASM9260_BM_RS485CTRL_RS485EN … #define ASM9260_HW_RS485ADRMATCH … /* Contains the address match value. */ #define ASM9260_BM_RS485ADRMATCH_MASK … #define ASM9260_HW_RS485DLY … /* * RW. Contains the direction control (RTS or DTR) delay value. This delay time * is in periods of the baud clock. */ #define ASM9260_BM_RS485DLY_MASK … #define ASM9260_HW_AUTOBAUD … /* WO. Auto-baud time-out interrupt clear bit. */ #define ASM9260_BM_AUTOBAUD_TO_INT_CLR … /* WO. End of auto-baud interrupt clear bit. */ #define ASM9260_BM_AUTOBAUD_EO_INT_CLR … /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */ #define ASM9260_BM_AUTOBAUD_AUTORESTART … /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */ #define ASM9260_BM_AUTOBAUD_MODE … /* * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is * automatically cleared after auto-baud completion. */ #define ASM9260_BM_AUTOBAUD_START … #define ASM9260_HW_CTRL3 … #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK … /* * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on * pins 137 and 144. */ #define ASM9260_BM_CTRL3_MASTERMODE … /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */ #define ASM9260_BM_CTRL3_SYNCMODE … /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */ #define ASM9260_BM_CTRL3_MSBF … /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */ #define ASM9260_BM_CTRL3_BAUD8 … /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */ #define ASM9260_BM_CTRL3_9BIT … #define ASM9260_HW_ISO7816_CTRL … /* RW. Enable High Speed mode. */ #define ASM9260_BM_ISO7816CTRL_HS … /* Disable Successive Receive NACK */ #define ASM9260_BM_ISO7816CTRL_DS_NACK … #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK … /* Receive NACK Inhibit */ #define ASM9260_BM_ISO7816CTRL_INACK … #define ASM9260_BM_ISO7816CTRL_NEG_DATA … /* RW. 1 - ISO7816 mode; 0 - USART mode */ #define ASM9260_BM_ISO7816CTRL_ENABLE … #define ASM9260_HW_ISO7816_ERRCNT … /* Parity error counter. Will be cleared after reading */ #define ASM9260_BM_ISO7816_NB_ERRORS_MASK … #define ASM9260_HW_ISO7816_STATUS … /* Max number of Repetitions Reached */ #define ASM9260_BM_ISO7816_STAT_ITERATION … /* End of Alphascale asm9260 defines */ static struct uart_driver auart_driver; enum mxs_auart_type { … }; struct vendor_data { … }; enum { … }; static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = …; static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = …; static const struct vendor_data vendor_alphascale_asm9260 = …; static const struct vendor_data vendor_freescale_stmp37xx = …; struct mxs_auart_port { … }; static const struct of_device_id mxs_auart_dt_ids[] = …; MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); static inline int is_imx28_auart(struct mxs_auart_port *s) { … } static inline int is_asm9260_auart(struct mxs_auart_port *s) { … } static inline bool auart_dma_enabled(struct mxs_auart_port *s) { … } static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap, unsigned int reg) { … } static unsigned int mxs_read(const struct mxs_auart_port *uap, unsigned int reg) { … } static void mxs_write(unsigned int val, struct mxs_auart_port *uap, unsigned int reg) { … } static void mxs_set(unsigned int val, struct mxs_auart_port *uap, unsigned int reg) { … } static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, unsigned int reg) { … } static void mxs_auart_stop_tx(struct uart_port *u); #define to_auart_port(u) … static void mxs_auart_tx_chars(struct mxs_auart_port *s); static void dma_tx_callback(void *param) { … } static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) { … } static void mxs_auart_tx_chars(struct mxs_auart_port *s) { … } static void mxs_auart_rx_char(struct mxs_auart_port *s) { … } static void mxs_auart_rx_chars(struct mxs_auart_port *s) { … } static int mxs_auart_request_port(struct uart_port *u) { … } static int mxs_auart_verify_port(struct uart_port *u, struct serial_struct *ser) { … } static void mxs_auart_config_port(struct uart_port *u, int flags) { … } static const char *mxs_auart_type(struct uart_port *u) { … } static void mxs_auart_release_port(struct uart_port *u) { … } static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) { … } #define MCTRL_ANY_DELTA … static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) { … } static u32 mxs_auart_get_mctrl(struct uart_port *u) { … } /* * Enable modem status interrupts */ static void mxs_auart_enable_ms(struct uart_port *port) { … } /* * Disable modem status interrupts */ static void mxs_auart_disable_ms(struct uart_port *port) { … } static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); static void dma_rx_callback(void *arg) { … } static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) { … } static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) { … } static void mxs_auart_dma_exit(struct mxs_auart_port *s) { … } static int mxs_auart_dma_init(struct mxs_auart_port *s) { … } #define RTS_AT_AUART() … #define CTS_AT_AUART() … static void mxs_auart_settermios(struct uart_port *u, struct ktermios *termios, const struct ktermios *old) { … } static void mxs_auart_set_ldisc(struct uart_port *port, struct ktermios *termios) { … } static irqreturn_t mxs_auart_irq_handle(int irq, void *context) { … } static void mxs_auart_reset_deassert(struct mxs_auart_port *s) { … } static void mxs_auart_reset_assert(struct mxs_auart_port *s) { … } static int mxs_auart_startup(struct uart_port *u) { … } static void mxs_auart_shutdown(struct uart_port *u) { … } static unsigned int mxs_auart_tx_empty(struct uart_port *u) { … } static void mxs_auart_start_tx(struct uart_port *u) { … } static void mxs_auart_stop_tx(struct uart_port *u) { … } static void mxs_auart_stop_rx(struct uart_port *u) { … } static void mxs_auart_break_ctl(struct uart_port *u, int ctl) { … } static const struct uart_ops mxs_auart_ops = …; static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch) { … } static void auart_console_write(struct console *co, const char *str, unsigned int count) { … } static void __init auart_console_get_options(struct mxs_auart_port *s, int *baud, int *parity, int *bits) { … } static int __init auart_console_setup(struct console *co, char *options) { … } static struct console auart_console = …; #endif static struct uart_driver auart_driver = …; static void mxs_init_regs(struct mxs_auart_port *s) { … } static int mxs_get_clks(struct mxs_auart_port *s, struct platform_device *pdev) { … } static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) { … } static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) { … } static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) { … } static int mxs_auart_probe(struct platform_device *pdev) { … } static void mxs_auart_remove(struct platform_device *pdev) { … } static struct platform_driver mxs_auart_driver = …; static int __init mxs_auart_init(void) { … } static void __exit mxs_auart_exit(void) { … } module_init(…) …; module_exit(mxs_auart_exit); MODULE_LICENSE(…) …; MODULE_DESCRIPTION(…) …; MODULE_ALIAS(…) …;
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