linux/include/linux/serial_s3c.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
 *
 *  Copyright (C) 2002 Shane Nay ([email protected])
 *
 *  Additional defines, Copyright 2003 Simtec Electronics ([email protected])
 *
 *  Adapted from:
 *
 *  Internal header file for MX1ADS serial ports (UART1 & 2)
 *
 *  Copyright (C) 2002 Shane Nay ([email protected])
 */

#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H

#define S3C2410_URXH
#define S3C2410_UTXH
#define S3C2410_ULCON
#define S3C2410_UCON
#define S3C2410_UFCON
#define S3C2410_UMCON
#define S3C2410_UBRDIV
#define S3C2410_UTRSTAT
#define S3C2410_UERSTAT
#define S3C2410_UFSTAT
#define S3C2410_UMSTAT

#define S3C2410_LCON_CFGMASK

#define S3C2410_LCON_CS5
#define S3C2410_LCON_CS6
#define S3C2410_LCON_CS7
#define S3C2410_LCON_CS8
#define S3C2410_LCON_CSMASK

#define S3C2410_LCON_PNONE
#define S3C2410_LCON_PEVEN
#define S3C2410_LCON_PODD
#define S3C2410_LCON_PMASK

#define S3C2410_LCON_STOPB
#define S3C2410_LCON_IRM

#define S3C2440_UCON_CLKMASK
#define S3C2440_UCON_CLKSHIFT
#define S3C2440_UCON_PCLK
#define S3C2440_UCON_UCLK
#define S3C2440_UCON_PCLK2
#define S3C2440_UCON_FCLK
#define S3C2443_UCON_EPLL

#define S3C6400_UCON_CLKMASK
#define S3C6400_UCON_CLKSHIFT
#define S3C6400_UCON_PCLK
#define S3C6400_UCON_PCLK2
#define S3C6400_UCON_UCLK0
#define S3C6400_UCON_UCLK1

#define S3C2440_UCON2_FCLK_EN
#define S3C2440_UCON0_DIVMASK
#define S3C2440_UCON1_DIVMASK
#define S3C2440_UCON2_DIVMASK
#define S3C2440_UCON_DIVSHIFT

#define S3C2412_UCON_CLKMASK
#define S3C2412_UCON_CLKSHIFT
#define S3C2412_UCON_UCLK
#define S3C2412_UCON_USYSCLK
#define S3C2412_UCON_PCLK
#define S3C2412_UCON_PCLK2

#define S3C2410_UCON_CLKMASK
#define S3C2410_UCON_CLKSHIFT
#define S3C2410_UCON_UCLK
#define S3C2410_UCON_SBREAK

#define S3C2410_UCON_TXILEVEL
#define S3C2410_UCON_RXILEVEL
#define S3C2410_UCON_TXIRQMODE
#define S3C2410_UCON_RXIRQMODE
#define S3C2410_UCON_RXFIFO_TOI
#define S3C2443_UCON_RXERR_IRQEN
#define S3C2410_UCON_LOOPBACK

#define S3C2410_UCON_DEFAULT

#define S3C64XX_UCON_TXBURST_1
#define S3C64XX_UCON_TXBURST_4
#define S3C64XX_UCON_TXBURST_8
#define S3C64XX_UCON_TXBURST_16
#define S3C64XX_UCON_TXBURST_MASK
#define S3C64XX_UCON_RXBURST_1
#define S3C64XX_UCON_RXBURST_4
#define S3C64XX_UCON_RXBURST_8
#define S3C64XX_UCON_RXBURST_16
#define S3C64XX_UCON_RXBURST_MASK
#define S3C64XX_UCON_TIMEOUT_SHIFT
#define S3C64XX_UCON_TIMEOUT_MASK
#define S3C64XX_UCON_EMPTYINT_EN
#define S3C64XX_UCON_DMASUS_EN
#define S3C64XX_UCON_TXINT_LEVEL
#define S3C64XX_UCON_RXINT_LEVEL
#define S3C64XX_UCON_TIMEOUT_EN
#define S3C64XX_UCON_ERRINT_EN
#define S3C64XX_UCON_TXMODE_DMA
#define S3C64XX_UCON_TXMODE_CPU
#define S3C64XX_UCON_TXMODE_MASK
#define S3C64XX_UCON_RXMODE_DMA
#define S3C64XX_UCON_RXMODE_CPU
#define S3C64XX_UCON_RXMODE_MASK

#define S3C2410_UFCON_FIFOMODE
#define S3C2410_UFCON_TXTRIG0
#define S3C2410_UFCON_RXTRIG8
#define S3C2410_UFCON_RXTRIG12

/* S3C2440 FIFO trigger levels */
#define S3C2440_UFCON_RXTRIG1
#define S3C2440_UFCON_RXTRIG8
#define S3C2440_UFCON_RXTRIG16
#define S3C2440_UFCON_RXTRIG32

#define S3C2440_UFCON_TXTRIG0
#define S3C2440_UFCON_TXTRIG16
#define S3C2440_UFCON_TXTRIG32
#define S3C2440_UFCON_TXTRIG48

#define S3C2410_UFCON_RESETBOTH
#define S3C2410_UFCON_RESETTX
#define S3C2410_UFCON_RESETRX

#define S3C2410_UFCON_DEFAULT

#define S3C2410_UMCOM_AFC
#define S3C2410_UMCOM_RTS_LOW

#define S3C2412_UMCON_AFC_63
#define S3C2412_UMCON_AFC_56
#define S3C2412_UMCON_AFC_48
#define S3C2412_UMCON_AFC_40
#define S3C2412_UMCON_AFC_32
#define S3C2412_UMCON_AFC_24
#define S3C2412_UMCON_AFC_16
#define S3C2412_UMCON_AFC_8

#define S3C2410_UFSTAT_TXFULL
#define S3C2410_UFSTAT_RXFULL
#define S3C2410_UFSTAT_TXMASK
#define S3C2410_UFSTAT_TXSHIFT
#define S3C2410_UFSTAT_RXMASK
#define S3C2410_UFSTAT_RXSHIFT

/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL
#define S3C2440_UFSTAT_RXFULL
#define S3C2440_UFSTAT_TXSHIFT
#define S3C2440_UFSTAT_RXSHIFT
#define S3C2440_UFSTAT_TXMASK
#define S3C2440_UFSTAT_RXMASK

#define S3C2410_UTRSTAT_TIMEOUT
#define S3C2410_UTRSTAT_TXE
#define S3C2410_UTRSTAT_TXFE
#define S3C2410_UTRSTAT_RXDR

#define S3C2410_UERSTAT_OVERRUN
#define S3C2410_UERSTAT_FRAME
#define S3C2410_UERSTAT_BREAK
#define S3C2443_UERSTAT_PARITY

#define S3C2410_UERSTAT_ANY

#define S3C2410_UMSTAT_CTS
#define S3C2410_UMSTAT_DeltaCTS

#define S3C2443_DIVSLOT

/* S3C64XX interrupt registers. */
#define S3C64XX_UINTP
#define S3C64XX_UINTSP
#define S3C64XX_UINTM

#define S3C64XX_UINTM_RXD
#define S3C64XX_UINTM_ERROR
#define S3C64XX_UINTM_TXD
#define S3C64XX_UINTM_RXD_MSK
#define S3C64XX_UINTM_ERR_MSK
#define S3C64XX_UINTM_TXD_MSK

/* Following are specific to S5PV210 */
#define S5PV210_UCON_CLKMASK
#define S5PV210_UCON_CLKSHIFT
#define S5PV210_UCON_PCLK
#define S5PV210_UCON_UCLK

#define S5PV210_UFCON_TXTRIG0
#define S5PV210_UFCON_TXTRIG4
#define S5PV210_UFCON_TXTRIG8
#define S5PV210_UFCON_TXTRIG16
#define S5PV210_UFCON_TXTRIG32
#define S5PV210_UFCON_TXTRIG64
#define S5PV210_UFCON_TXTRIG128
#define S5PV210_UFCON_TXTRIG256

#define S5PV210_UFCON_RXTRIG1
#define S5PV210_UFCON_RXTRIG4
#define S5PV210_UFCON_RXTRIG8
#define S5PV210_UFCON_RXTRIG16
#define S5PV210_UFCON_RXTRIG32
#define S5PV210_UFCON_RXTRIG64
#define S5PV210_UFCON_RXTRIG128
#define S5PV210_UFCON_RXTRIG256

#define S5PV210_UFSTAT_TXFULL
#define S5PV210_UFSTAT_RXFULL
#define S5PV210_UFSTAT_TXMASK
#define S5PV210_UFSTAT_TXSHIFT
#define S5PV210_UFSTAT_RXMASK
#define S5PV210_UFSTAT_RXSHIFT

#define S3C2410_UCON_CLKSEL0
#define S3C2410_UCON_CLKSEL1
#define S3C2410_UCON_CLKSEL2
#define S3C2410_UCON_CLKSEL3

/* Default values for s5pv210 UCON and UFCON uart registers */
#define S5PV210_UCON_DEFAULT

#define S5PV210_UFCON_DEFAULT

#define APPLE_S5L_UCON_RXTO_ENA
#define APPLE_S5L_UCON_RXTO_LEGACY_ENA
#define APPLE_S5L_UCON_RXTHRESH_ENA
#define APPLE_S5L_UCON_TXTHRESH_ENA
#define APPLE_S5L_UCON_RXTO_ENA_MSK
#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK
#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK
#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK

#define APPLE_S5L_UCON_DEFAULT
#define APPLE_S5L_UCON_MASK

#define APPLE_S5L_UTRSTAT_RXTO_LEGACY
#define APPLE_S5L_UTRSTAT_RXTHRESH
#define APPLE_S5L_UTRSTAT_TXTHRESH
#define APPLE_S5L_UTRSTAT_RXTO
#define APPLE_S5L_UTRSTAT_ALL_FLAGS

#ifndef __ASSEMBLY__

#include <linux/serial_core.h>

/* configuration structure for per-machine configurations for the
 * serial port
 *
 * the pointer is setup by the machine specific initialisation from the
 * arch/arm/mach-s3c/ directory.
*/

struct s3c2410_uartcfg {};

#endif /* __ASSEMBLY__ */

#endif /* __ASM_ARM_REGS_SERIAL_H */