// SPDX-License-Identifier: GPL-2.0 /* * serial_tegra.c * * High-speed serial driver for NVIDIA Tegra SoCs * * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. * * Author: Laxman Dewangan <[email protected]> */ #include <linux/clk.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pagemap.h> #include <linux/platform_device.h> #include <linux/reset.h> #include <linux/serial.h> #include <linux/serial_8250.h> #include <linux/serial_core.h> #include <linux/serial_reg.h> #include <linux/slab.h> #include <linux/string.h> #include <linux/termios.h> #include <linux/tty.h> #include <linux/tty_flip.h> #define TEGRA_UART_TYPE … #define TX_EMPTY_STATUS … #define BYTES_TO_ALIGN(x) … #define TEGRA_UART_RX_DMA_BUFFER_SIZE … #define TEGRA_UART_LSR_TXFIFO_FULL … #define TEGRA_UART_IER_EORD … #define TEGRA_UART_MCR_RTS_EN … #define TEGRA_UART_MCR_CTS_EN … #define TEGRA_UART_LSR_ANY … #define TEGRA_UART_IRDA_CSR … #define TEGRA_UART_SIR_ENABLED … #define TEGRA_UART_TX_PIO … #define TEGRA_UART_TX_DMA … #define TEGRA_UART_MIN_DMA … #define TEGRA_UART_FIFO_SIZE … /* * Tx fifo trigger level setting in tegra uart is in * reverse way then conventional uart. */ #define TEGRA_UART_TX_TRIG_16B … #define TEGRA_UART_TX_TRIG_8B … #define TEGRA_UART_TX_TRIG_4B … #define TEGRA_UART_TX_TRIG_1B … #define TEGRA_UART_MAXIMUM … /* Default UART setting when started: 115200 no parity, stop, 8 data bits */ #define TEGRA_UART_DEFAULT_BAUD … #define TEGRA_UART_DEFAULT_LSR … /* Tx transfer mode */ #define TEGRA_TX_PIO … #define TEGRA_TX_DMA … #define TEGRA_UART_FCR_IIR_FIFO_EN … /** * struct tegra_uart_chip_data: SOC specific data. * * @tx_fifo_full_status: Status flag available for checking tx fifo full. * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not. * Tegra30 does not allow this. * @support_clk_src_div: Clock source support the clock divider. * @fifo_mode_enable_status: Is FIFO mode enabled? * @uart_max_port: Maximum number of UART ports * @max_dma_burst_bytes: Maximum size of DMA bursts * @error_tolerance_low_range: Lowest number in the error tolerance range * @error_tolerance_high_range: Highest number in the error tolerance range */ struct tegra_uart_chip_data { … }; struct tegra_baud_tolerance { … }; struct tegra_uart_port { … }; static void tegra_uart_start_next_tx(struct tegra_uart_port *tup); static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup); static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, bool dma_to_memory); static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, unsigned long reg) { … } static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, unsigned long reg) { … } static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u) { … } static unsigned int tegra_uart_get_mctrl(struct uart_port *u) { … } static void set_rts(struct tegra_uart_port *tup, bool active) { … } static void set_dtr(struct tegra_uart_port *tup, bool active) { … } static void set_loopbk(struct tegra_uart_port *tup, bool active) { … } static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl) { … } static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) { … } /** * tegra_uart_wait_cycle_time: Wait for N UART clock periods * * @tup: Tegra serial port data structure. * @cycles: Number of clock periods to wait. * * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART * clock speed is 16X the current baud rate. */ static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, unsigned int cycles) { … } /* Wait for a symbol-time. */ static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, unsigned int syms) { … } static int tegra_uart_wait_fifo_mode_enabled(struct tegra_uart_port *tup) { … } static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) { … } static long tegra_get_tolerance_rate(struct tegra_uart_port *tup, unsigned int baud, long rate) { … } static int tegra_check_rate_in_range(struct tegra_uart_port *tup) { … } static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) { … } static u8 tegra_uart_decode_rx_error(struct tegra_uart_port *tup, unsigned long lsr) { … } static int tegra_uart_request_port(struct uart_port *u) { … } static void tegra_uart_release_port(struct uart_port *u) { … } static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) { … } static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, unsigned int bytes) { … } static void tegra_uart_tx_dma_complete(void *args) { … } static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, unsigned long count) { … } static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) { … } /* Called by serial core driver with u->lock taken. */ static void tegra_uart_start_tx(struct uart_port *u) { … } static unsigned int tegra_uart_tx_empty(struct uart_port *u) { … } static void tegra_uart_stop_tx(struct uart_port *u) { … } static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) { … } static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, struct tty_port *port) { … } static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, struct tty_port *port, unsigned int count) { … } static void do_handle_rx_pio(struct tegra_uart_port *tup) { … } static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, unsigned int residue) { … } static void tegra_uart_rx_dma_complete(void *args) { … } static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) { … } static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) { … } static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) { … } static void tegra_uart_handle_modem_signal_change(struct uart_port *u) { … } static irqreturn_t tegra_uart_isr(int irq, void *data) { … } static void tegra_uart_stop_rx(struct uart_port *u) { … } static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) { … } static int tegra_uart_hw_init(struct tegra_uart_port *tup) { … } static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, bool dma_to_memory) { … } static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, bool dma_to_memory) { … } static int tegra_uart_startup(struct uart_port *u) { … } /* * Flush any TX data submitted for DMA and PIO. Called when the * TX circular buffer is reset. */ static void tegra_uart_flush_buffer(struct uart_port *u) { … } static void tegra_uart_shutdown(struct uart_port *u) { … } static void tegra_uart_enable_ms(struct uart_port *u) { … } static void tegra_uart_set_termios(struct uart_port *u, struct ktermios *termios, const struct ktermios *oldtermios) { … } static const char *tegra_uart_type(struct uart_port *u) { … } static const struct uart_ops tegra_uart_ops = …; static struct uart_driver tegra_uart_driver = …; static int tegra_uart_parse_dt(struct platform_device *pdev, struct tegra_uart_port *tup) { … } static struct tegra_uart_chip_data tegra20_uart_chip_data = …; static struct tegra_uart_chip_data tegra30_uart_chip_data = …; static struct tegra_uart_chip_data tegra186_uart_chip_data = …; static struct tegra_uart_chip_data tegra194_uart_chip_data = …; static const struct of_device_id tegra_uart_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_uart_of_match); static int tegra_uart_probe(struct platform_device *pdev) { … } static void tegra_uart_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int tegra_uart_suspend(struct device *dev) { … } static int tegra_uart_resume(struct device *dev) { … } #endif static const struct dev_pm_ops tegra_uart_pm_ops = …; static struct platform_driver tegra_uart_platform_driver = …; static int __init tegra_uart_init(void) { … } static void __exit tegra_uart_exit(void) { … } module_init(…) …; module_exit(tegra_uart_exit); MODULE_ALIAS(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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