/* * Intel GTT (Graphics Translation Table) routines * * Caveat: This driver implements the linux agp interface, but this is far from * a agp driver! GTT support ended up here for purely historical reasons: The * old userspace intel graphics drivers needed an interface to map memory into * the GTT. And the drm provides a default interface for graphic devices sitting * on an agp port. So it made sense to fake the GTT support as an agp port to * avoid having to create a new api. * * With gem this does not make much sense anymore, just needlessly complicates * the code. But as long as the old graphics stack is still support, it's stuck * here. * * /fairy-tale-mode off */ #include <linux/module.h> #include <linux/pci.h> #include <linux/kernel.h> #include <linux/pagemap.h> #include <linux/agp_backend.h> #include <linux/iommu.h> #include <linux/delay.h> #include <asm/smp.h> #include "agp.h" #include "intel-agp.h" #include <drm/intel/intel-gtt.h> #include <asm/set_memory.h> /* * If we have Intel graphics, we're not going to have anything other than * an Intel IOMMU. So make the correct use of the PCI DMA API contingent * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). * Only newer chipsets need to bother with this, of course. */ #ifdef CONFIG_INTEL_IOMMU #define USE_PCI_DMA_API … #else #define USE_PCI_DMA_API … #endif struct intel_gtt_driver { … }; static struct _intel_private { … } intel_private; #define INTEL_GTT_GEN … #define IS_G33 … #define IS_PINEVIEW … #define IS_IRONLAKE … #define HAS_PGTBL_EN … #if IS_ENABLED(CONFIG_AGP_INTEL) static int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, struct sg_table *st) { … } static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) { … } static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) { … } /* Exists to support ARGB cursors */ static struct page *i8xx_alloc_pages(void) { … } static void i8xx_destroy_pages(struct page *page) { … } #endif #define I810_GTT_ORDER … static int i810_setup(void) { … } static void i810_cleanup(void) { … } #if IS_ENABLED(CONFIG_AGP_INTEL) static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, int type) { … } /* * The i810/i830 requires a physical address to program its mouse * pointer into hardware. * However the Xserver still writes to it through the agp aperture. */ static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) { … } static void intel_i810_free_by_type(struct agp_memory *curr) { … } #endif static int intel_gtt_setup_scratch_page(void) { … } static void i810_write_entry(dma_addr_t addr, unsigned int entry, unsigned int flags) { … } static resource_size_t intel_gtt_stolen_size(void) { … } static void i965_adjust_pgetbl_size(unsigned int size_flag) { … } static unsigned int i965_gtt_total_entries(void) { … } static unsigned int intel_gtt_total_entries(void) { … } static unsigned int intel_gtt_mappable_entries(void) { … } static void intel_gtt_teardown_scratch_page(void) { … } static void intel_gtt_cleanup(void) { … } /* Certain Gen5 chipsets require require idling the GPU before * unmapping anything from the GTT when VT-d is enabled. */ static inline int needs_ilk_vtd_wa(void) { … } static bool intel_gtt_can_wc(void) { … } static int intel_gtt_init(void) { … } #if IS_ENABLED(CONFIG_AGP_INTEL) static const struct aper_size_info_fixed intel_fake_agp_sizes[] = …; static int intel_fake_agp_fetch_size(void) { … } #endif static void i830_cleanup(void) { … } /* The chipset_flush interface needs to get data that has already been * flushed out of the CPU all the way out to main memory, because the GPU * doesn't snoop those buffers. * * The 8xx series doesn't have the same lovely interface for flushing the * chipset write buffers that the later chips do. According to the 865 * specs, it's 64 octwords, or 1KB. So, to get those previous things in * that buffer out, we just fill 1KB and clflush it out, on the assumption * that it'll push whatever was in there out. It appears to work. */ static void i830_chipset_flush(void) { … } static void i830_write_entry(dma_addr_t addr, unsigned int entry, unsigned int flags) { … } bool intel_gmch_enable_gtt(void) { … } EXPORT_SYMBOL(…); static int i830_setup(void) { … } #if IS_ENABLED(CONFIG_AGP_INTEL) static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) { … } static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) { … } static int intel_fake_agp_configure(void) { … } #endif static bool i830_check_flags(unsigned int flags) { … } void intel_gmch_gtt_insert_page(dma_addr_t addr, unsigned int pg, unsigned int flags) { … } EXPORT_SYMBOL(…); void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, unsigned int pg_start, unsigned int flags) { … } EXPORT_SYMBOL(…); #if IS_ENABLED(CONFIG_AGP_INTEL) static void intel_gmch_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, struct page **pages, unsigned int flags) { … } static int intel_fake_agp_insert_entries(struct agp_memory *mem, off_t pg_start, int type) { … } #endif void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) { … } EXPORT_SYMBOL(…); #if IS_ENABLED(CONFIG_AGP_INTEL) static int intel_fake_agp_remove_entries(struct agp_memory *mem, off_t pg_start, int type) { … } static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, int type) { … } #endif static int intel_alloc_chipset_flush_resource(void) { … } static void intel_i915_setup_chipset_flush(void) { … } static void intel_i965_g33_setup_chipset_flush(void) { … } static void intel_i9xx_setup_flush(void) { … } static void i9xx_cleanup(void) { … } static void i9xx_chipset_flush(void) { … } static void i965_write_entry(dma_addr_t addr, unsigned int entry, unsigned int flags) { … } static int i9xx_setup(void) { … } #if IS_ENABLED(CONFIG_AGP_INTEL) static const struct agp_bridge_driver intel_fake_agp_driver = …; #endif static const struct intel_gtt_driver i81x_gtt_driver = …; static const struct intel_gtt_driver i8xx_gtt_driver = …; static const struct intel_gtt_driver i915_gtt_driver = …; static const struct intel_gtt_driver g33_gtt_driver = …; static const struct intel_gtt_driver pineview_gtt_driver = …; static const struct intel_gtt_driver i965_gtt_driver = …; static const struct intel_gtt_driver g4x_gtt_driver = …; static const struct intel_gtt_driver ironlake_gtt_driver = …; /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of * driver and gmch_driver must be non-null, and find_gmch will determine * which one should be used if a gmch_chip_id is present. */ static const struct intel_gtt_driver_description { … } intel_gtt_chipsets[] = …; static int find_gmch(u16 device) { … } int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, struct agp_bridge_data *bridge) { … } EXPORT_SYMBOL(…); void intel_gmch_gtt_get(u64 *gtt_total, phys_addr_t *mappable_base, resource_size_t *mappable_end) { … } EXPORT_SYMBOL(…); void intel_gmch_gtt_flush(void) { … } EXPORT_SYMBOL(…); void intel_gmch_remove(void) { … } EXPORT_SYMBOL(…); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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