// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016 Google, Inc * * This device driver implements a TCG PTP FIFO interface over SPI for chips * with Cr50 firmware. * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard. */ #include <linux/completion.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pm.h> #include <linux/spi/spi.h> #include <linux/wait.h> #include "tpm_tis_core.h" #include "tpm_tis_spi.h" /* * Cr50 timing constants: * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC. * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep. * - requires waiting for "ready" IRQ, if supported; or waiting for at least * CR50_NOIRQ_ACCESS_DELAY_MSEC between transactions, if IRQ is not supported. * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication. */ #define CR50_SLEEP_DELAY_MSEC … #define CR50_WAKE_START_DELAY_USEC … #define CR50_NOIRQ_ACCESS_DELAY … #define CR50_READY_IRQ_TIMEOUT … #define CR50_FLOW_CONTROL … #define MAX_IRQ_CONFIRMATION_ATTEMPTS … #define TPM_CR50_FW_VER(l) … #define TPM_CR50_MAX_FW_VER_LEN … /* Default quality for hwrng. */ #define TPM_CR50_DEFAULT_RNG_QUALITY … struct cr50_spi_phy { … }; static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) { … } /* * The cr50 interrupt handler just signals waiting threads that the * interrupt was asserted. It does not do any processing triggered * by interrupts but is instead used to avoid fixed delays. */ static irqreturn_t cr50_spi_irq_handler(int dummy, void *dev_id) { … } /* * Cr50 needs to have at least some delay between consecutive * transactions. Make sure we wait. */ static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) { … } /* * Cr50 might go to sleep if there is no SPI activity for some time and * miss the first few bits/bytes on the bus. In such case, wake it up * by asserting CS and give it time to start up. */ static bool cr50_needs_waking(struct cr50_spi_phy *phy) { … } static void cr50_wake_if_needed(struct cr50_spi_phy *cr50_phy) { … } /* * Flow control: clock the bus and wait for cr50 to set LSB before * sending/receiving data. TCG PTP spec allows it to happen during * the last byte of header, but cr50 never does that in practice, * and earlier versions had a bug when it was set too early, so don't * check for it during header transfer. */ static int cr50_spi_flow_control(struct tpm_tis_spi_phy *phy, struct spi_transfer *spi_xfer) { … } static bool tpm_cr50_spi_is_firmware_power_managed(struct device *dev) { … } static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 len, u8 *in, const u8 *out) { … } static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len, u8 *result, enum tpm_tis_io_mode io_mode) { … } static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len, const u8 *value, enum tpm_tis_io_mode io_mode) { … } static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = …; static void cr50_print_fw_version(struct tpm_tis_data *data) { … } int cr50_spi_probe(struct spi_device *spi) { … } #ifdef CONFIG_PM_SLEEP int tpm_tis_spi_resume(struct device *dev) { … } #endif
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