/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. * Author: Joerg Roedel <[email protected]> * Leo Duran <[email protected]> */ #ifndef _ASM_X86_AMD_IOMMU_TYPES_H #define _ASM_X86_AMD_IOMMU_TYPES_H #include <linux/bitfield.h> #include <linux/iommu.h> #include <linux/types.h> #include <linux/mmu_notifier.h> #include <linux/mutex.h> #include <linux/msi.h> #include <linux/list.h> #include <linux/spinlock.h> #include <linux/pci.h> #include <linux/irqreturn.h> #include <linux/io-pgtable.h> /* * Maximum number of IOMMUs supported */ #define MAX_IOMMUS … /* * some size calculation constants */ #define DEV_TABLE_ENTRY_SIZE … #define ALIAS_TABLE_ENTRY_SIZE … #define RLOOKUP_TABLE_ENTRY_SIZE … /* Capability offsets used by the driver */ #define MMIO_CAP_HDR_OFFSET … #define MMIO_RANGE_OFFSET … #define MMIO_MISC_OFFSET … /* Masks, shifts and macros to parse the device range capability */ #define MMIO_RANGE_LD_MASK … #define MMIO_RANGE_FD_MASK … #define MMIO_RANGE_BUS_MASK … #define MMIO_RANGE_LD_SHIFT … #define MMIO_RANGE_FD_SHIFT … #define MMIO_RANGE_BUS_SHIFT … #define MMIO_GET_LD(x) … #define MMIO_GET_FD(x) … #define MMIO_GET_BUS(x) … #define MMIO_MSI_NUM(x) … /* Flag masks for the AMD IOMMU exclusion range */ #define MMIO_EXCL_ENABLE_MASK … #define MMIO_EXCL_ALLOW_MASK … /* Used offsets into the MMIO space */ #define MMIO_DEV_TABLE_OFFSET … #define MMIO_CMD_BUF_OFFSET … #define MMIO_EVT_BUF_OFFSET … #define MMIO_CONTROL_OFFSET … #define MMIO_EXCL_BASE_OFFSET … #define MMIO_EXCL_LIMIT_OFFSET … #define MMIO_EXT_FEATURES … #define MMIO_PPR_LOG_OFFSET … #define MMIO_GA_LOG_BASE_OFFSET … #define MMIO_GA_LOG_TAIL_OFFSET … #define MMIO_MSI_ADDR_LO_OFFSET … #define MMIO_MSI_ADDR_HI_OFFSET … #define MMIO_MSI_DATA_OFFSET … #define MMIO_INTCAPXT_EVT_OFFSET … #define MMIO_INTCAPXT_PPR_OFFSET … #define MMIO_INTCAPXT_GALOG_OFFSET … #define MMIO_EXT_FEATURES2 … #define MMIO_CMD_HEAD_OFFSET … #define MMIO_CMD_TAIL_OFFSET … #define MMIO_EVT_HEAD_OFFSET … #define MMIO_EVT_TAIL_OFFSET … #define MMIO_STATUS_OFFSET … #define MMIO_PPR_HEAD_OFFSET … #define MMIO_PPR_TAIL_OFFSET … #define MMIO_GA_HEAD_OFFSET … #define MMIO_GA_TAIL_OFFSET … #define MMIO_CNTR_CONF_OFFSET … #define MMIO_CNTR_REG_OFFSET … #define MMIO_REG_END_OFFSET … /* Extended Feature Bits */ #define FEATURE_PREFETCH … #define FEATURE_PPR … #define FEATURE_X2APIC … #define FEATURE_NX … #define FEATURE_GT … #define FEATURE_IA … #define FEATURE_GA … #define FEATURE_HE … #define FEATURE_PC … #define FEATURE_GATS … #define FEATURE_GLX … #define FEATURE_GAM_VAPIC … #define FEATURE_PASMAX … #define FEATURE_GIOSUP … #define FEATURE_HASUP … #define FEATURE_EPHSUP … #define FEATURE_HDSUP … #define FEATURE_SNP … /* Extended Feature 2 Bits */ #define FEATURE_SNPAVICSUP … #define FEATURE_SNPAVICSUP_GAM(x) … /* Note: * The current driver only support 16-bit PASID. * Currently, hardware only implement upto 16-bit PASID * even though the spec says it could have upto 20 bits. */ #define PASID_MASK … /* MMIO status bits */ #define MMIO_STATUS_EVT_OVERFLOW_MASK … #define MMIO_STATUS_EVT_INT_MASK … #define MMIO_STATUS_COM_WAIT_INT_MASK … #define MMIO_STATUS_EVT_RUN_MASK … #define MMIO_STATUS_PPR_OVERFLOW_MASK … #define MMIO_STATUS_PPR_INT_MASK … #define MMIO_STATUS_PPR_RUN_MASK … #define MMIO_STATUS_GALOG_RUN_MASK … #define MMIO_STATUS_GALOG_OVERFLOW_MASK … #define MMIO_STATUS_GALOG_INT_MASK … /* event logging constants */ #define EVENT_ENTRY_SIZE … #define EVENT_TYPE_SHIFT … #define EVENT_TYPE_MASK … #define EVENT_TYPE_ILL_DEV … #define EVENT_TYPE_IO_FAULT … #define EVENT_TYPE_DEV_TAB_ERR … #define EVENT_TYPE_PAGE_TAB_ERR … #define EVENT_TYPE_ILL_CMD … #define EVENT_TYPE_CMD_HARD_ERR … #define EVENT_TYPE_IOTLB_INV_TO … #define EVENT_TYPE_INV_DEV_REQ … #define EVENT_TYPE_INV_PPR_REQ … #define EVENT_TYPE_RMP_FAULT … #define EVENT_TYPE_RMP_HW_ERR … #define EVENT_DEVID_MASK … #define EVENT_DEVID_SHIFT … #define EVENT_DOMID_MASK_LO … #define EVENT_DOMID_MASK_HI … #define EVENT_FLAGS_MASK … #define EVENT_FLAGS_SHIFT … #define EVENT_FLAG_RW … #define EVENT_FLAG_I … /* feature control bits */ #define CONTROL_IOMMU_EN … #define CONTROL_HT_TUN_EN … #define CONTROL_EVT_LOG_EN … #define CONTROL_EVT_INT_EN … #define CONTROL_COMWAIT_EN … #define CONTROL_INV_TIMEOUT … #define CONTROL_PASSPW_EN … #define CONTROL_RESPASSPW_EN … #define CONTROL_COHERENT_EN … #define CONTROL_ISOC_EN … #define CONTROL_CMDBUF_EN … #define CONTROL_PPRLOG_EN … #define CONTROL_PPRINT_EN … #define CONTROL_PPR_EN … #define CONTROL_GT_EN … #define CONTROL_GA_EN … #define CONTROL_GAM_EN … #define CONTROL_GALOG_EN … #define CONTROL_GAINT_EN … #define CONTROL_XT_EN … #define CONTROL_INTCAPXT_EN … #define CONTROL_IRTCACHEDIS … #define CONTROL_SNPAVIC_EN … #define CTRL_INV_TO_MASK … #define CTRL_INV_TO_NONE … #define CTRL_INV_TO_1MS … #define CTRL_INV_TO_10MS … #define CTRL_INV_TO_100MS … #define CTRL_INV_TO_1S … #define CTRL_INV_TO_10S … #define CTRL_INV_TO_100S … /* command specific defines */ #define CMD_COMPL_WAIT … #define CMD_INV_DEV_ENTRY … #define CMD_INV_IOMMU_PAGES … #define CMD_INV_IOTLB_PAGES … #define CMD_INV_IRT … #define CMD_COMPLETE_PPR … #define CMD_INV_ALL … #define CMD_COMPL_WAIT_STORE_MASK … #define CMD_COMPL_WAIT_INT_MASK … #define CMD_INV_IOMMU_PAGES_SIZE_MASK … #define CMD_INV_IOMMU_PAGES_PDE_MASK … #define CMD_INV_IOMMU_PAGES_GN_MASK … #define PPR_STATUS_MASK … #define PPR_STATUS_SHIFT … #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS … /* macros and definitions for device table entries */ #define DEV_ENTRY_VALID … #define DEV_ENTRY_TRANSLATION … #define DEV_ENTRY_HAD … #define DEV_ENTRY_PPR … #define DEV_ENTRY_IR … #define DEV_ENTRY_IW … #define DEV_ENTRY_NO_PAGE_FAULT … #define DEV_ENTRY_EX … #define DEV_ENTRY_SYSMGT1 … #define DEV_ENTRY_SYSMGT2 … #define DEV_ENTRY_IRQ_TBL_EN … #define DEV_ENTRY_INIT_PASS … #define DEV_ENTRY_EINT_PASS … #define DEV_ENTRY_NMI_PASS … #define DEV_ENTRY_LINT0_PASS … #define DEV_ENTRY_LINT1_PASS … #define DEV_ENTRY_MODE_MASK … #define DEV_ENTRY_MODE_SHIFT … #define MAX_DEV_TABLE_ENTRIES … /* constants to configure the command buffer */ #define CMD_BUFFER_SIZE … #define CMD_BUFFER_UNINITIALIZED … #define CMD_BUFFER_ENTRIES … #define MMIO_CMD_SIZE_SHIFT … #define MMIO_CMD_SIZE_512 … /* constants for event buffer handling */ #define EVT_BUFFER_SIZE … #define EVT_LEN_MASK … /* Constants for PPR Log handling */ #define PPR_LOG_ENTRIES … #define PPR_LOG_SIZE_SHIFT … #define PPR_LOG_SIZE_512 … #define PPR_ENTRY_SIZE … #define PPR_LOG_SIZE … /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */ #define PPR_FLAG_EXEC … #define PPR_FLAG_READ … #define PPR_FLAG_WRITE … #define PPR_FLAG_US … #define PPR_FLAG_RVSD … #define PPR_FLAG_GN … #define PPR_REQ_TYPE(x) … #define PPR_FLAGS(x) … #define PPR_DEVID(x) … #define PPR_TAG(x) … #define PPR_PASID1(x) … #define PPR_PASID2(x) … #define PPR_PASID(x) … #define PPR_REQ_FAULT … /* Constants for GA Log handling */ #define GA_LOG_ENTRIES … #define GA_LOG_SIZE_SHIFT … #define GA_LOG_SIZE_512 … #define GA_ENTRY_SIZE … #define GA_LOG_SIZE … #define GA_TAG(x) … #define GA_DEVID(x) … #define GA_REQ_TYPE(x) … #define GA_GUEST_NR … #define IOMMU_IN_ADDR_BIT_SIZE … #define IOMMU_OUT_ADDR_BIT_SIZE … /* * This bitmap is used to advertise the page sizes our hardware support * to the IOMMU core, which will then use this information to split * physically contiguous memory regions it is mapping into page sizes * that we support. * * 512GB Pages are not supported due to a hardware bug * Page sizes >= the 52 bit max physical address of the CPU are not supported. */ #define AMD_IOMMU_PGSIZES … /* Special mode where page-sizes are limited to 4 KiB */ #define AMD_IOMMU_PGSIZES_4K … /* 4K, 2MB, 1G page sizes are supported */ #define AMD_IOMMU_PGSIZES_V2 … /* Bit value definition for dte irq remapping fields*/ #define DTE_IRQ_PHYS_ADDR_MASK … #define DTE_IRQ_REMAP_INTCTL_MASK … #define DTE_IRQ_REMAP_INTCTL … #define DTE_IRQ_REMAP_ENABLE … /* * AMD IOMMU hardware only support 512 IRTEs despite * the architectural limitation of 2048 entries. */ #define DTE_INTTAB_ALIGNMENT … #define DTE_INTTABLEN_VALUE … #define DTE_INTTABLEN … #define DTE_INTTABLEN_MASK … #define MAX_IRQS_PER_TABLE … #define PAGE_MODE_NONE … #define PAGE_MODE_1_LEVEL … #define PAGE_MODE_2_LEVEL … #define PAGE_MODE_3_LEVEL … #define PAGE_MODE_4_LEVEL … #define PAGE_MODE_5_LEVEL … #define PAGE_MODE_6_LEVEL … #define PAGE_MODE_7_LEVEL … #define GUEST_PGTABLE_4_LEVEL … #define GUEST_PGTABLE_5_LEVEL … #define PM_LEVEL_SHIFT(x) … #define PM_LEVEL_SIZE(x) … #define PM_LEVEL_INDEX(x, a) … #define PM_LEVEL_ENC(x) … #define PM_LEVEL_PDE(x, a) … #define PM_PTE_LEVEL(pte) … #define PM_MAP_4k … #define PM_ADDR_MASK … #define PM_MAP_MASK(lvl) … #define PM_ALIGNED(lvl, addr) … /* * Returns the page table level to use for a given page size * Pagesize is expected to be a power-of-two */ #define PAGE_SIZE_LEVEL(pagesize) … /* * Returns the number of ptes to use for a given page size * Pagesize is expected to be a power-of-two */ #define PAGE_SIZE_PTE_COUNT(pagesize) … /* * Aligns a given io-virtual address to a given page size * Pagesize is expected to be a power-of-two */ #define PAGE_SIZE_ALIGN(address, pagesize) … /* * Creates an IOMMU PTE for an address and a given pagesize * The PTE has no permission bits set * Pagesize is expected to be a power-of-two larger than 4096 */ #define PAGE_SIZE_PTE(address, pagesize) … /* * Takes a PTE value with mode=0x07 and returns the page size it maps */ #define PTE_PAGE_SIZE(pte) … /* * Takes a page-table level and returns the default page-size for this level */ #define PTE_LEVEL_PAGE_SIZE(level) … /* * The IOPTE dirty bit */ #define IOMMU_PTE_HD_BIT … /* * Bit value definition for I/O PTE fields */ #define IOMMU_PTE_PR … #define IOMMU_PTE_HD … #define IOMMU_PTE_U … #define IOMMU_PTE_FC … #define IOMMU_PTE_IR … #define IOMMU_PTE_IW … /* * Bit value definition for DTE fields */ #define DTE_FLAG_V … #define DTE_FLAG_TV … #define DTE_FLAG_HAD … #define DTE_FLAG_GIOV … #define DTE_FLAG_GV … #define DTE_GLX_SHIFT … #define DTE_GLX_MASK … #define DTE_FLAG_IR … #define DTE_FLAG_IW … #define DTE_FLAG_IOTLB … #define DTE_FLAG_MASK … #define DEV_DOMID_MASK … #define DTE_GCR3_VAL_A(x) … #define DTE_GCR3_VAL_B(x) … #define DTE_GCR3_VAL_C(x) … #define DTE_GCR3_SHIFT_A … #define DTE_GCR3_SHIFT_B … #define DTE_GCR3_SHIFT_C … #define DTE_GPT_LEVEL_SHIFT … #define GCR3_VALID … #define IOMMU_PAGE_MASK … #define IOMMU_PTE_PRESENT(pte) … #define IOMMU_PTE_DIRTY(pte) … #define IOMMU_PTE_PAGE(pte) … #define IOMMU_PTE_MODE(pte) … #define IOMMU_PROT_MASK … #define IOMMU_PROT_IR … #define IOMMU_PROT_IW … #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE … /* IOMMU capabilities */ #define IOMMU_CAP_IOTLB … #define IOMMU_CAP_NPCACHE … #define IOMMU_CAP_EFR … /* IOMMU IVINFO */ #define IOMMU_IVINFO_OFFSET … #define IOMMU_IVINFO_EFRSUP … #define IOMMU_IVINFO_DMA_REMAP … /* IOMMU Feature Reporting Field (for IVHD type 10h */ #define IOMMU_FEAT_GASUP_SHIFT … /* IOMMU Extended Feature Register (EFR) */ #define IOMMU_EFR_XTSUP_SHIFT … #define IOMMU_EFR_GASUP_SHIFT … #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT … #define MAX_DOMAIN_ID … /* Timeout stuff */ #define LOOP_TIMEOUT … #define MMIO_STATUS_TIMEOUT … extern bool amd_iommu_dump; #define DUMP_printk(format, arg...) … /* global flag if IOMMUs cache non-present entries */ extern bool amd_iommu_np_cache; /* Only true if all IOMMUs support device IOTLBs */ extern bool amd_iommu_iotlb_sup; struct irq_remap_table { … }; /* Interrupt remapping feature used? */ extern bool amd_iommu_irq_remap; extern const struct iommu_ops amd_iommu_ops; /* IVRS indicates that pre-boot remapping was enabled */ extern bool amdr_ivrs_remap_support; /* kmem_cache to get tables with 128 byte alignement */ extern struct kmem_cache *amd_iommu_irq_cache; #define PCI_SBDF_TO_SEGID(sbdf) … #define PCI_SBDF_TO_DEVID(sbdf) … #define PCI_SEG_DEVID_TO_SBDF(seg, devid) … /* Make iterating over all pci segment easier */ #define for_each_pci_segment(pci_seg) … #define for_each_pci_segment_safe(pci_seg, next) … /* * Make iterating over all IOMMUs easier */ #define for_each_iommu(iommu) … #define for_each_iommu_safe(iommu, next) … /* Making iterating over protection_domain->dev_data_list easier */ #define for_each_pdom_dev_data(pdom_dev_data, pdom) … #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) … struct amd_iommu; struct iommu_domain; struct irq_domain; struct amd_irte_ops; #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED … #define io_pgtable_to_data(x) … #define io_pgtable_ops_to_data(x) … #define io_pgtable_ops_to_domain(x) … #define io_pgtable_cfg_to_data(x) … struct gcr3_tbl_info { … }; struct amd_io_pgtable { … }; enum protection_domain_mode { … }; /* Track dev_data/PASID list for the protection domain */ struct pdom_dev_data { … }; /* * This structure contains generic data for IOMMU protection domains * independent of their use. */ struct protection_domain { … }; /* * This structure contains information about one PCI segment in the system. */ struct amd_iommu_pci_seg { … }; /* * Structure where we save information about one hardware AMD IOMMU in the * system. */ struct amd_iommu { … }; static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) { … } #define ACPIHID_UID_LEN … #define ACPIHID_HID_LEN … struct acpihid_map_entry { … }; struct devid_map { … }; #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP … #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP … #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP … /* Device may request execution on memory pages */ #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP … /* Device may request super-user privileges */ #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP … /* * This struct contains device specific data for the IOMMU */ struct iommu_dev_data { … }; /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ extern struct list_head ioapic_map; extern struct list_head hpet_map; extern struct list_head acpihid_map; /* * List with all PCI segments in the system. This list is not locked because * it is only written at driver initialization time */ extern struct list_head amd_iommu_pci_seg_list; /* * List with all IOMMUs in the system. This list is not locked because it is * only written and read at driver initialization or suspend time */ extern struct list_head amd_iommu_list; /* * Array with pointers to each IOMMU struct * The indices are referenced in the protection domains */ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; /* * Structure defining one entry in the device table */ struct dev_table_entry { … }; /* * One entry for unity mappings parsed out of the ACPI table. */ struct unity_map_entry { … }; /* * Data structures for device handling */ /* size of the dma_ops aperture as power of 2 */ extern unsigned amd_iommu_aperture_order; /* allocation bitmap for domain ids */ extern unsigned long *amd_iommu_pd_alloc_bitmap; extern bool amd_iommu_force_isolation; /* Max levels of glxval supported */ extern int amd_iommu_max_glx_val; /* Global EFR and EFR2 registers */ extern u64 amd_iommu_efr; extern u64 amd_iommu_efr2; static inline int get_ioapic_devid(int id) { … } static inline int get_hpet_devid(int id) { … } enum amd_iommu_intr_mode_type { … }; #define AMD_IOMMU_GUEST_IR_GA(x) … #define AMD_IOMMU_GUEST_IR_VAPIC(x) … irte; #define APICID_TO_IRTE_DEST_LO(x) … #define APICID_TO_IRTE_DEST_HI(x) … irte_ga_lo; irte_ga_hi; struct irte_ga { … }; struct irq_2_irte { … }; struct amd_ir_data { … }; struct amd_irte_ops { … }; #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; #endif #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
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