/* SPDX-License-Identifier: GPL-2.0 */ /* * pasid.h - PASID idr, table and entry header * * Copyright (C) 2018 Intel Corporation * * Author: Lu Baolu <[email protected]> */ #ifndef __INTEL_PASID_H #define __INTEL_PASID_H #define PASID_MAX … #define PASID_PTE_MASK … #define PASID_PTE_PRESENT … #define PASID_PTE_FPD … #define PDE_PFN_MASK … #define PASID_PDE_SHIFT … #define MAX_NR_PASID_BITS … #define PASID_TBL_ENTRIES … #define is_pasid_enabled(entry) … #define get_pasid_dir_size(entry) … /* * Domain ID reserved for pasid entries programmed for first-level * only and pass-through transfer modes. */ #define FLPT_DEFAULT_DID … #define NUM_RESERVED_DID … #define PASID_FLAG_NESTED … #define PASID_FLAG_PAGE_SNOOP … /* * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first- * level translation, otherwise, 4-level paging will be used. */ #define PASID_FLAG_FL5LP … struct pasid_dir_entry { … }; struct pasid_entry { … }; #define PASID_ENTRY_PGTT_FL_ONLY … #define PASID_ENTRY_PGTT_SL_ONLY … #define PASID_ENTRY_PGTT_NESTED … #define PASID_ENTRY_PGTT_PT … /* The representative of a PASID table */ struct pasid_table { … }; /* Get PRESENT bit of a PASID directory entry. */ static inline bool pasid_pde_is_present(struct pasid_dir_entry *pde) { … } /* Get PASID table from a PASID directory entry. */ static inline struct pasid_entry * get_pasid_table_from_pde(struct pasid_dir_entry *pde) { … } /* Get PRESENT bit of a PASID table entry. */ static inline bool pasid_pte_is_present(struct pasid_entry *pte) { … } /* Get PGTT field of a PASID table entry */ static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte) { … } static inline void pasid_clear_entry(struct pasid_entry *pe) { … } static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe) { … } static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits) { … } static inline u64 pasid_get_bits(u64 *ptr) { … } /* * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode * PASID entry. */ static inline void pasid_set_domain_id(struct pasid_entry *pe, u64 value) { … } /* * Get domain ID value of a scalable mode PASID entry. */ static inline u16 pasid_get_domain_id(struct pasid_entry *pe) { … } /* * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63) * of a scalable mode PASID entry. */ static inline void pasid_set_slptr(struct pasid_entry *pe, u64 value) { … } /* * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID * entry. */ static inline void pasid_set_address_width(struct pasid_entry *pe, u64 value) { … } /* * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8) * of a scalable mode PASID entry. */ static inline void pasid_set_translation_type(struct pasid_entry *pe, u64 value) { … } /* * Enable fault processing by clearing the FPD(Fault Processing * Disable) field (Bit 1) of a scalable mode PASID entry. */ static inline void pasid_set_fault_enable(struct pasid_entry *pe) { … } /* * Enable second level A/D bits by setting the SLADE (Second Level * Access Dirty Enable) field (Bit 9) of a scalable mode PASID * entry. */ static inline void pasid_set_ssade(struct pasid_entry *pe) { … } /* * Disable second level A/D bits by clearing the SLADE (Second Level * Access Dirty Enable) field (Bit 9) of a scalable mode PASID * entry. */ static inline void pasid_clear_ssade(struct pasid_entry *pe) { … } /* * Checks if second level A/D bits specifically the SLADE (Second Level * Access Dirty Enable) field (Bit 9) of a scalable mode PASID * entry is set. */ static inline bool pasid_get_ssade(struct pasid_entry *pe) { … } /* * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a * scalable mode PASID entry. */ static inline void pasid_set_sre(struct pasid_entry *pe) { … } /* * Setup the WPE(Write Protect Enable) field (Bit 132) of a * scalable mode PASID entry. */ static inline void pasid_set_wpe(struct pasid_entry *pe) { … } /* * Setup the P(Present) field (Bit 0) of a scalable mode PASID * entry. */ static inline void pasid_set_present(struct pasid_entry *pe) { … } /* * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID * entry. */ static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value) { … } /* * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode * PASID entry. */ static inline void pasid_set_pgsnp(struct pasid_entry *pe) { … } /* * Setup the First Level Page table Pointer field (Bit 140~191) * of a scalable mode PASID entry. */ static inline void pasid_set_flptr(struct pasid_entry *pe, u64 value) { … } /* * Setup the First Level Paging Mode field (Bit 130~131) of a * scalable mode PASID entry. */ static inline void pasid_set_flpm(struct pasid_entry *pe, u64 value) { … } /* * Setup the Extended Access Flag Enable (EAFE) field (Bit 135) * of a scalable mode PASID entry. */ static inline void pasid_set_eafe(struct pasid_entry *pe) { … } extern unsigned int intel_pasid_max_id; int intel_pasid_alloc_table(struct device *dev); void intel_pasid_free_table(struct device *dev); struct pasid_table *intel_pasid_get_table(struct device *dev); int intel_pasid_setup_first_level(struct intel_iommu *iommu, struct device *dev, pgd_t *pgd, u32 pasid, u16 did, int flags); int intel_pasid_setup_second_level(struct intel_iommu *iommu, struct dmar_domain *domain, struct device *dev, u32 pasid); int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool enabled); int intel_pasid_setup_pass_through(struct intel_iommu *iommu, struct device *dev, u32 pasid); int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev, u32 pasid, struct dmar_domain *domain); void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool fault_ignore); void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu, struct device *dev, u32 pasid); int intel_pasid_setup_sm_context(struct device *dev); void intel_pasid_teardown_sm_context(struct device *dev); #endif /* __INTEL_PASID_H */
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