/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- * * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Fremont, California. * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Kevin E. Martin <[email protected]> * Gareth Hughes <[email protected]> * Keith Whitwell <[email protected]> */ #ifndef __RADEON_DRM_H__ #define __RADEON_DRM_H__ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif /* WARNING: If you change any of these defines, make sure to change the * defines in the X server file (radeon_sarea.h) */ #ifndef __RADEON_SAREA_DEFINES__ #define __RADEON_SAREA_DEFINES__ /* Old style state flags, required for sarea interface (1.1 and 1.2 * clears) and 1.2 drm_vertex2 ioctl. */ #define RADEON_UPLOAD_CONTEXT … #define RADEON_UPLOAD_VERTFMT … #define RADEON_UPLOAD_LINE … #define RADEON_UPLOAD_BUMPMAP … #define RADEON_UPLOAD_MASKS … #define RADEON_UPLOAD_VIEWPORT … #define RADEON_UPLOAD_SETUP … #define RADEON_UPLOAD_TCL … #define RADEON_UPLOAD_MISC … #define RADEON_UPLOAD_TEX0 … #define RADEON_UPLOAD_TEX1 … #define RADEON_UPLOAD_TEX2 … #define RADEON_UPLOAD_TEX0IMAGES … #define RADEON_UPLOAD_TEX1IMAGES … #define RADEON_UPLOAD_TEX2IMAGES … #define RADEON_UPLOAD_CLIPRECTS … #define RADEON_REQUIRE_QUIESCENCE … #define RADEON_UPLOAD_ZBIAS … #define RADEON_UPLOAD_ALL … #define RADEON_UPLOAD_CONTEXT_ALL … /* New style per-packet identifiers for use in cmd_buffer ioctl with * the RADEON_EMIT_PACKET command. Comments relate new packets to old * state bits and the packet size: */ #define RADEON_EMIT_PP_MISC … #define RADEON_EMIT_PP_CNTL … #define RADEON_EMIT_RB3D_COLORPITCH … #define RADEON_EMIT_RE_LINE_PATTERN … #define RADEON_EMIT_SE_LINE_WIDTH … #define RADEON_EMIT_PP_LUM_MATRIX … #define RADEON_EMIT_PP_ROT_MATRIX_0 … #define RADEON_EMIT_RB3D_STENCILREFMASK … #define RADEON_EMIT_SE_VPORT_XSCALE … #define RADEON_EMIT_SE_CNTL … #define RADEON_EMIT_SE_CNTL_STATUS … #define RADEON_EMIT_RE_MISC … #define RADEON_EMIT_PP_TXFILTER_0 … #define RADEON_EMIT_PP_BORDER_COLOR_0 … #define RADEON_EMIT_PP_TXFILTER_1 … #define RADEON_EMIT_PP_BORDER_COLOR_1 … #define RADEON_EMIT_PP_TXFILTER_2 … #define RADEON_EMIT_PP_BORDER_COLOR_2 … #define RADEON_EMIT_SE_ZBIAS_FACTOR … #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT … #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED … #define R200_EMIT_PP_TXCBLEND_0 … #define R200_EMIT_PP_TXCBLEND_1 … #define R200_EMIT_PP_TXCBLEND_2 … #define R200_EMIT_PP_TXCBLEND_3 … #define R200_EMIT_PP_TXCBLEND_4 … #define R200_EMIT_PP_TXCBLEND_5 … #define R200_EMIT_PP_TXCBLEND_6 … #define R200_EMIT_PP_TXCBLEND_7 … #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 … #define R200_EMIT_TFACTOR_0 … #define R200_EMIT_VTX_FMT_0 … #define R200_EMIT_VAP_CTL … #define R200_EMIT_MATRIX_SELECT_0 … #define R200_EMIT_TEX_PROC_CTL_2 … #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL … #define R200_EMIT_PP_TXFILTER_0 … #define R200_EMIT_PP_TXFILTER_1 … #define R200_EMIT_PP_TXFILTER_2 … #define R200_EMIT_PP_TXFILTER_3 … #define R200_EMIT_PP_TXFILTER_4 … #define R200_EMIT_PP_TXFILTER_5 … #define R200_EMIT_PP_TXOFFSET_0 … #define R200_EMIT_PP_TXOFFSET_1 … #define R200_EMIT_PP_TXOFFSET_2 … #define R200_EMIT_PP_TXOFFSET_3 … #define R200_EMIT_PP_TXOFFSET_4 … #define R200_EMIT_PP_TXOFFSET_5 … #define R200_EMIT_VTE_CNTL … #define R200_EMIT_OUTPUT_VTX_COMP_SEL … #define R200_EMIT_PP_TAM_DEBUG3 … #define R200_EMIT_PP_CNTL_X … #define R200_EMIT_RB3D_DEPTHXY_OFFSET … #define R200_EMIT_RE_AUX_SCISSOR_CNTL … #define R200_EMIT_RE_SCISSOR_TL_0 … #define R200_EMIT_RE_SCISSOR_TL_1 … #define R200_EMIT_RE_SCISSOR_TL_2 … #define R200_EMIT_SE_VAP_CNTL_STATUS … #define R200_EMIT_SE_VTX_STATE_CNTL … #define R200_EMIT_RE_POINTSIZE … #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 … #define R200_EMIT_PP_CUBIC_FACES_0 … #define R200_EMIT_PP_CUBIC_OFFSETS_0 … #define R200_EMIT_PP_CUBIC_FACES_1 … #define R200_EMIT_PP_CUBIC_OFFSETS_1 … #define R200_EMIT_PP_CUBIC_FACES_2 … #define R200_EMIT_PP_CUBIC_OFFSETS_2 … #define R200_EMIT_PP_CUBIC_FACES_3 … #define R200_EMIT_PP_CUBIC_OFFSETS_3 … #define R200_EMIT_PP_CUBIC_FACES_4 … #define R200_EMIT_PP_CUBIC_OFFSETS_4 … #define R200_EMIT_PP_CUBIC_FACES_5 … #define R200_EMIT_PP_CUBIC_OFFSETS_5 … #define RADEON_EMIT_PP_TEX_SIZE_0 … #define RADEON_EMIT_PP_TEX_SIZE_1 … #define RADEON_EMIT_PP_TEX_SIZE_2 … #define R200_EMIT_RB3D_BLENDCOLOR … #define R200_EMIT_TCL_POINT_SPRITE_CNTL … #define RADEON_EMIT_PP_CUBIC_FACES_0 … #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 … #define RADEON_EMIT_PP_CUBIC_FACES_1 … #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 … #define RADEON_EMIT_PP_CUBIC_FACES_2 … #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 … #define R200_EMIT_PP_TRI_PERF_CNTL … #define R200_EMIT_PP_AFS_0 … #define R200_EMIT_PP_AFS_1 … #define R200_EMIT_ATF_TFACTOR … #define R200_EMIT_PP_TXCTLALL_0 … #define R200_EMIT_PP_TXCTLALL_1 … #define R200_EMIT_PP_TXCTLALL_2 … #define R200_EMIT_PP_TXCTLALL_3 … #define R200_EMIT_PP_TXCTLALL_4 … #define R200_EMIT_PP_TXCTLALL_5 … #define R200_EMIT_VAP_PVS_CNTL … #define RADEON_MAX_STATE_PACKETS … /* Commands understood by cmd_buffer ioctl. More can be added but * obviously these can't be removed or changed: */ #define RADEON_CMD_PACKET … #define RADEON_CMD_SCALARS … #define RADEON_CMD_VECTORS … #define RADEON_CMD_DMA_DISCARD … #define RADEON_CMD_PACKET3 … #define RADEON_CMD_PACKET3_CLIP … #define RADEON_CMD_SCALARS2 … #define RADEON_CMD_WAIT … #define RADEON_CMD_VECLINEAR … drm_radeon_cmd_header_t; #define RADEON_WAIT_2D … #define RADEON_WAIT_3D … /* Allowed parameters for R300_CMD_PACKET3 */ #define R300_CMD_PACKET3_CLEAR … #define R300_CMD_PACKET3_RAW … /* Commands understood by cmd_buffer ioctl for R300. * The interface has not been stabilized, so some of these may be removed * and eventually reordered before stabilization. */ #define R300_CMD_PACKET0 … #define R300_CMD_VPU … #define R300_CMD_PACKET3 … #define R300_CMD_END3D … #define R300_CMD_CP_DELAY … #define R300_CMD_DMA_DISCARD … #define R300_CMD_WAIT … #define R300_WAIT_2D … #define R300_WAIT_3D … /* these two defines are DOING IT WRONG - however * we have userspace which relies on using these. * The wait interface is backwards compat new * code should use the NEW_WAIT defines below * THESE ARE NOT BIT FIELDS */ #define R300_WAIT_2D_CLEAN … #define R300_WAIT_3D_CLEAN … #define R300_NEW_WAIT_2D_3D … #define R300_NEW_WAIT_2D_2D_CLEAN … #define R300_NEW_WAIT_3D_3D_CLEAN … #define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN … #define R300_CMD_SCRATCH … #define R300_CMD_R500FP … drm_r300_cmd_header_t; #define RADEON_FRONT … #define RADEON_BACK … #define RADEON_DEPTH … #define RADEON_STENCIL … #define RADEON_CLEAR_FASTZ … #define RADEON_USE_HIERZ … #define RADEON_USE_COMP_ZBUF … #define R500FP_CONSTANT_TYPE … #define R500FP_CONSTANT_CLAMP … /* Primitive types */ #define RADEON_POINTS … #define RADEON_LINES … #define RADEON_LINE_STRIP … #define RADEON_TRIANGLES … #define RADEON_TRIANGLE_FAN … #define RADEON_TRIANGLE_STRIP … /* Vertex/indirect buffer size */ #define RADEON_BUFFER_SIZE … /* Byte offsets for indirect buffer data */ #define RADEON_INDEX_PRIM_OFFSET … #define RADEON_SCRATCH_REG_OFFSET … #define R600_SCRATCH_REG_OFFSET … #define RADEON_NR_SAREA_CLIPRECTS … /* There are 2 heaps (local/GART). Each region within a heap is a * minimum of 64k, and there are at most 64 of them per heap. */ #define RADEON_LOCAL_TEX_HEAP … #define RADEON_GART_TEX_HEAP … #define RADEON_NR_TEX_HEAPS … #define RADEON_NR_TEX_REGIONS … #define RADEON_LOG_TEX_GRANULARITY … #define RADEON_MAX_TEXTURE_LEVELS … #define RADEON_MAX_TEXTURE_UNITS … #define RADEON_MAX_SURFACES … /* Blits have strict offset rules. All blit offset must be aligned on * a 1K-byte boundary. */ #define RADEON_OFFSET_SHIFT … #define RADEON_OFFSET_ALIGN … #define RADEON_OFFSET_MASK … #endif /* __RADEON_SAREA_DEFINES__ */ radeon_color_regs_t; drm_radeon_context_regs_t; drm_radeon_context2_regs_t; /* Setup registers for each texture unit */ drm_radeon_texture_regs_t; drm_radeon_prim_t; drm_radeon_state_t; drm_radeon_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) * * KW: actually it's illegal to change any of this (backwards compatibility). */ /* Radeon specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_RADEON_CP_INIT … #define DRM_RADEON_CP_START … #define DRM_RADEON_CP_STOP … #define DRM_RADEON_CP_RESET … #define DRM_RADEON_CP_IDLE … #define DRM_RADEON_RESET … #define DRM_RADEON_FULLSCREEN … #define DRM_RADEON_SWAP … #define DRM_RADEON_CLEAR … #define DRM_RADEON_VERTEX … #define DRM_RADEON_INDICES … #define DRM_RADEON_NOT_USED #define DRM_RADEON_STIPPLE … #define DRM_RADEON_INDIRECT … #define DRM_RADEON_TEXTURE … #define DRM_RADEON_VERTEX2 … #define DRM_RADEON_CMDBUF … #define DRM_RADEON_GETPARAM … #define DRM_RADEON_FLIP … #define DRM_RADEON_ALLOC … #define DRM_RADEON_FREE … #define DRM_RADEON_INIT_HEAP … #define DRM_RADEON_IRQ_EMIT … #define DRM_RADEON_IRQ_WAIT … #define DRM_RADEON_CP_RESUME … #define DRM_RADEON_SETPARAM … #define DRM_RADEON_SURF_ALLOC … #define DRM_RADEON_SURF_FREE … /* KMS ioctl */ #define DRM_RADEON_GEM_INFO … #define DRM_RADEON_GEM_CREATE … #define DRM_RADEON_GEM_MMAP … #define DRM_RADEON_GEM_PREAD … #define DRM_RADEON_GEM_PWRITE … #define DRM_RADEON_GEM_SET_DOMAIN … #define DRM_RADEON_GEM_WAIT_IDLE … #define DRM_RADEON_CS … #define DRM_RADEON_INFO … #define DRM_RADEON_GEM_SET_TILING … #define DRM_RADEON_GEM_GET_TILING … #define DRM_RADEON_GEM_BUSY … #define DRM_RADEON_GEM_VA … #define DRM_RADEON_GEM_OP … #define DRM_RADEON_GEM_USERPTR … #define DRM_IOCTL_RADEON_CP_INIT … #define DRM_IOCTL_RADEON_CP_START … #define DRM_IOCTL_RADEON_CP_STOP … #define DRM_IOCTL_RADEON_CP_RESET … #define DRM_IOCTL_RADEON_CP_IDLE … #define DRM_IOCTL_RADEON_RESET … #define DRM_IOCTL_RADEON_FULLSCREEN … #define DRM_IOCTL_RADEON_SWAP … #define DRM_IOCTL_RADEON_CLEAR … #define DRM_IOCTL_RADEON_VERTEX … #define DRM_IOCTL_RADEON_INDICES … #define DRM_IOCTL_RADEON_STIPPLE … #define DRM_IOCTL_RADEON_INDIRECT … #define DRM_IOCTL_RADEON_TEXTURE … #define DRM_IOCTL_RADEON_VERTEX2 … #define DRM_IOCTL_RADEON_CMDBUF … #define DRM_IOCTL_RADEON_GETPARAM … #define DRM_IOCTL_RADEON_FLIP … #define DRM_IOCTL_RADEON_ALLOC … #define DRM_IOCTL_RADEON_FREE … #define DRM_IOCTL_RADEON_INIT_HEAP … #define DRM_IOCTL_RADEON_IRQ_EMIT … #define DRM_IOCTL_RADEON_IRQ_WAIT … #define DRM_IOCTL_RADEON_CP_RESUME … #define DRM_IOCTL_RADEON_SETPARAM … #define DRM_IOCTL_RADEON_SURF_ALLOC … #define DRM_IOCTL_RADEON_SURF_FREE … /* KMS */ #define DRM_IOCTL_RADEON_GEM_INFO … #define DRM_IOCTL_RADEON_GEM_CREATE … #define DRM_IOCTL_RADEON_GEM_MMAP … #define DRM_IOCTL_RADEON_GEM_PREAD … #define DRM_IOCTL_RADEON_GEM_PWRITE … #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN … #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE … #define DRM_IOCTL_RADEON_CS … #define DRM_IOCTL_RADEON_INFO … #define DRM_IOCTL_RADEON_GEM_SET_TILING … #define DRM_IOCTL_RADEON_GEM_GET_TILING … #define DRM_IOCTL_RADEON_GEM_BUSY … #define DRM_IOCTL_RADEON_GEM_VA … #define DRM_IOCTL_RADEON_GEM_OP … #define DRM_IOCTL_RADEON_GEM_USERPTR … drm_radeon_init_t; drm_radeon_cp_stop_t; drm_radeon_fullscreen_t; #define CLEAR_X1 … #define CLEAR_Y1 … #define CLEAR_X2 … #define CLEAR_Y2 … #define CLEAR_DEPTH … drm_radeon_clear_rect_t; drm_radeon_clear_t; drm_radeon_vertex_t; drm_radeon_indices_t; /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices * - allows multiple primitives and state changes in a single ioctl * - supports driver change to emit native primitives */ drm_radeon_vertex2_t; /* v1.3 - obsoletes drm_radeon_vertex2 * - allows arbitrarily large cliprect list * - allows updating of tcl packet, vector and scalar state * - allows memory-efficient description of state updates * - allows state to be emitted without a primitive * (for clears, ctx switches) * - allows more than one dma buffer to be referenced per ioctl * - supports tcl driver * - may be extended in future versions with new cmd types, packets */ drm_radeon_cmd_buffer_t; drm_radeon_tex_image_t; drm_radeon_texture_t; drm_radeon_stipple_t; drm_radeon_indirect_t; /* enum for card type parameters */ #define RADEON_CARD_PCI … #define RADEON_CARD_AGP … #define RADEON_CARD_PCIE … /* 1.3: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define RADEON_PARAM_GART_BUFFER_OFFSET … #define RADEON_PARAM_LAST_FRAME … #define RADEON_PARAM_LAST_DISPATCH … #define RADEON_PARAM_LAST_CLEAR … /* Added with DRM version 1.6. */ #define RADEON_PARAM_IRQ_NR … #define RADEON_PARAM_GART_BASE … /* Added with DRM version 1.8. */ #define RADEON_PARAM_REGISTER_HANDLE … #define RADEON_PARAM_STATUS_HANDLE … #define RADEON_PARAM_SAREA_HANDLE … #define RADEON_PARAM_GART_TEX_HANDLE … #define RADEON_PARAM_SCRATCH_OFFSET … #define RADEON_PARAM_CARD_TYPE … #define RADEON_PARAM_VBLANK_CRTC … #define RADEON_PARAM_FB_LOCATION … #define RADEON_PARAM_NUM_GB_PIPES … #define RADEON_PARAM_DEVICE_ID … #define RADEON_PARAM_NUM_Z_PIPES … drm_radeon_getparam_t; /* 1.6: Set up a memory manager for regions of shared memory: */ #define RADEON_MEM_REGION_GART … #define RADEON_MEM_REGION_FB … drm_radeon_mem_alloc_t; drm_radeon_mem_free_t; drm_radeon_mem_init_heap_t; /* 1.6: Userspace can request & wait on irq's: */ drm_radeon_irq_emit_t; drm_radeon_irq_wait_t; /* 1.10: Clients tell the DRM where they think the framebuffer is located in * the card's address space, via a new generic ioctl to set parameters */ drm_radeon_setparam_t; #define RADEON_SETPARAM_FB_LOCATION … #define RADEON_SETPARAM_SWITCH_TILING … #define RADEON_SETPARAM_PCIGART_LOCATION … #define RADEON_SETPARAM_NEW_MEMMAP … #define RADEON_SETPARAM_PCIGART_TABLE_SIZE … #define RADEON_SETPARAM_VBLANK_CRTC … /* 1.14: Clients can allocate/free a surface */ drm_radeon_surface_alloc_t; drm_radeon_surface_free_t; #define DRM_RADEON_VBLANK_CRTC1 … #define DRM_RADEON_VBLANK_CRTC2 … /* * Kernel modesetting world below. */ #define RADEON_GEM_DOMAIN_CPU … #define RADEON_GEM_DOMAIN_GTT … #define RADEON_GEM_DOMAIN_VRAM … struct drm_radeon_gem_info { … }; #define RADEON_GEM_NO_BACKING_STORE … #define RADEON_GEM_GTT_UC … #define RADEON_GEM_GTT_WC … /* BO is expected to be accessed by the CPU */ #define RADEON_GEM_CPU_ACCESS … /* CPU access is not expected to work for this BO */ #define RADEON_GEM_NO_CPU_ACCESS … struct drm_radeon_gem_create { … }; /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to * perform any operation. */ #define RADEON_GEM_USERPTR_READONLY … #define RADEON_GEM_USERPTR_ANONONLY … #define RADEON_GEM_USERPTR_VALIDATE … #define RADEON_GEM_USERPTR_REGISTER … struct drm_radeon_gem_userptr { … }; #define RADEON_TILING_MACRO … #define RADEON_TILING_MICRO … #define RADEON_TILING_SWAP_16BIT … #define RADEON_TILING_SWAP_32BIT … /* this object requires a surface when mapped - i.e. front buffer */ #define RADEON_TILING_SURFACE … #define RADEON_TILING_MICRO_SQUARE … #define RADEON_TILING_EG_BANKW_SHIFT … #define RADEON_TILING_EG_BANKW_MASK … #define RADEON_TILING_EG_BANKH_SHIFT … #define RADEON_TILING_EG_BANKH_MASK … #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT … #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK … #define RADEON_TILING_EG_TILE_SPLIT_SHIFT … #define RADEON_TILING_EG_TILE_SPLIT_MASK … #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT … #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK … struct drm_radeon_gem_set_tiling { … }; struct drm_radeon_gem_get_tiling { … }; struct drm_radeon_gem_mmap { … }; struct drm_radeon_gem_set_domain { … }; struct drm_radeon_gem_wait_idle { … }; struct drm_radeon_gem_busy { … }; struct drm_radeon_gem_pread { … }; struct drm_radeon_gem_pwrite { … }; /* Sets or returns a value associated with a buffer. */ struct drm_radeon_gem_op { … }; #define RADEON_GEM_OP_GET_INITIAL_DOMAIN … #define RADEON_GEM_OP_SET_INITIAL_DOMAIN … #define RADEON_VA_MAP … #define RADEON_VA_UNMAP … #define RADEON_VA_RESULT_OK … #define RADEON_VA_RESULT_ERROR … #define RADEON_VA_RESULT_VA_EXIST … #define RADEON_VM_PAGE_VALID … #define RADEON_VM_PAGE_READABLE … #define RADEON_VM_PAGE_WRITEABLE … #define RADEON_VM_PAGE_SYSTEM … #define RADEON_VM_PAGE_SNOOPED … struct drm_radeon_gem_va { … }; #define RADEON_CHUNK_ID_RELOCS … #define RADEON_CHUNK_ID_IB … #define RADEON_CHUNK_ID_FLAGS … #define RADEON_CHUNK_ID_CONST_IB … /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ #define RADEON_CS_KEEP_TILING_FLAGS … #define RADEON_CS_USE_VM … #define RADEON_CS_END_OF_FRAME … /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ #define RADEON_CS_RING_GFX … #define RADEON_CS_RING_COMPUTE … #define RADEON_CS_RING_DMA … #define RADEON_CS_RING_UVD … #define RADEON_CS_RING_VCE … /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ /* 0 = normal, + = higher priority, - = lower priority */ struct drm_radeon_cs_chunk { … }; /* drm_radeon_cs_reloc.flags */ #define RADEON_RELOC_PRIO_MASK … struct drm_radeon_cs_reloc { … }; struct drm_radeon_cs { … }; #define RADEON_INFO_DEVICE_ID … #define RADEON_INFO_NUM_GB_PIPES … #define RADEON_INFO_NUM_Z_PIPES … #define RADEON_INFO_ACCEL_WORKING … #define RADEON_INFO_CRTC_FROM_ID … #define RADEON_INFO_ACCEL_WORKING2 … #define RADEON_INFO_TILING_CONFIG … #define RADEON_INFO_WANT_HYPERZ … #define RADEON_INFO_WANT_CMASK … #define RADEON_INFO_CLOCK_CRYSTAL_FREQ … #define RADEON_INFO_NUM_BACKENDS … #define RADEON_INFO_NUM_TILE_PIPES … #define RADEON_INFO_FUSION_GART_WORKING … #define RADEON_INFO_BACKEND_MAP … /* virtual address start, va < start are reserved by the kernel */ #define RADEON_INFO_VA_START … /* maximum size of ib using the virtual memory cs */ #define RADEON_INFO_IB_VM_MAX_SIZE … /* max pipes - needed for compute shaders */ #define RADEON_INFO_MAX_PIPES … /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ #define RADEON_INFO_TIMESTAMP … /* max shader engines (SE) - needed for geometry shaders, etc. */ #define RADEON_INFO_MAX_SE … /* max SH per SE */ #define RADEON_INFO_MAX_SH_PER_SE … /* fast fb access is enabled */ #define RADEON_INFO_FASTFB_WORKING … /* query if a RADEON_CS_RING_* submission is supported */ #define RADEON_INFO_RING_WORKING … /* SI tile mode array */ #define RADEON_INFO_SI_TILE_MODE_ARRAY … /* query if CP DMA is supported on the compute ring */ #define RADEON_INFO_SI_CP_DMA_COMPUTE … /* CIK macrotile mode array */ #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY … /* query the number of render backends */ #define RADEON_INFO_SI_BACKEND_ENABLED_MASK … /* max engine clock - needed for OpenCL */ #define RADEON_INFO_MAX_SCLK … /* version of VCE firmware */ #define RADEON_INFO_VCE_FW_VERSION … /* version of VCE feedback */ #define RADEON_INFO_VCE_FB_VERSION … #define RADEON_INFO_NUM_BYTES_MOVED … #define RADEON_INFO_VRAM_USAGE … #define RADEON_INFO_GTT_USAGE … #define RADEON_INFO_ACTIVE_CU_COUNT … #define RADEON_INFO_CURRENT_GPU_TEMP … #define RADEON_INFO_CURRENT_GPU_SCLK … #define RADEON_INFO_CURRENT_GPU_MCLK … #define RADEON_INFO_READ_REG … #define RADEON_INFO_VA_UNMAP_WORKING … #define RADEON_INFO_GPU_RESET_COUNTER … struct drm_radeon_info { … }; /* Those correspond to the tile index to use, this is to explicitly state * the API that is implicitly defined by the tile mode array. */ #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED … #define SI_TILE_MODE_COLOR_1D … #define SI_TILE_MODE_COLOR_1D_SCANOUT … #define SI_TILE_MODE_COLOR_2D_8BPP … #define SI_TILE_MODE_COLOR_2D_16BPP … #define SI_TILE_MODE_COLOR_2D_32BPP … #define SI_TILE_MODE_COLOR_2D_64BPP … #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP … #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP … #define SI_TILE_MODE_DEPTH_STENCIL_1D … #define SI_TILE_MODE_DEPTH_STENCIL_2D … #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA … #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA … #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA … #define CIK_TILE_MODE_DEPTH_STENCIL_1D … #if defined(__cplusplus) } #endif #endif
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