linux/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "amdgpu.h"
#include "nbio/nbio_2_3_offset.h"
#include "nbio/nbio_2_3_sh_mask.h"
#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "soc15.h"
#include "navi10_ih.h"
#include "soc15_common.h"
#include "mxgpu_nv.h"

#include "amdgpu_reset.h"

static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
{ … }

static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
{ … }

/*
 * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
 * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1
 * by host.
 *
 * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
 * correct value since it doesn't return the RCV_DW0 under the case that
 * RCV_MSG_VALID is set by host.
 */
static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)
{ … }


static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
				   enum idh_event event)
{ … }

static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)
{ … }

static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
{ … }

static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
{ … }

static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
	      enum idh_request req, u32 data1, u32 data2, u32 data3)
{ … }

static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev,
			enum idh_request req, u32 data1, u32 data2, u32 data3)
{ … }

static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
					enum idh_request req)
{ … }

static int xgpu_nv_request_reset(struct amdgpu_device *adev)
{ … }

static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,
					   bool init)
{ … }

static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,
					   bool init)
{ … }

static int xgpu_nv_request_init_data(struct amdgpu_device *adev)
{ … }

static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					struct amdgpu_iv_entry *entry)
{ … }

static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{ … }

static void xgpu_nv_ready_to_reset(struct amdgpu_device *adev)
{ … }

static int xgpu_nv_wait_reset(struct amdgpu_device *adev)
{ … }

static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
{ … }

static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
				       struct amdgpu_irq_src *src,
				       unsigned type,
				       enum amdgpu_interrupt_state state)
{ … }

static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,
				   struct amdgpu_irq_src *source,
				   struct amdgpu_iv_entry *entry)
{ … }

static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = …;

static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = …;

void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)
{ … }

int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)
{ … }

int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)
{ … }

void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
{ … }

static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev,
		enum amdgpu_ras_block block)
{ … }

static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev)
{ … }

const struct amdgpu_virt_ops xgpu_nv_virt_ops = …;