/* * DCE_10_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef DCE_10_0_SH_MASK_H #define DCE_10_0_SH_MASK_H #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK … #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT … #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK … #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT … #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK … #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT … #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK … #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT … #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK … #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT … #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK … #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT … #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK … #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT … #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK … #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT … #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK … #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT … #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK … #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT … #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK … #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT … #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK … #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT … #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK … #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT … #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK … #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT … #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK … #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT … #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK … #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT … #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK … #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT … #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK … #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT … #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK … #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT … #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK … #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT … #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK … #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT … #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK … #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT … #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK … #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT … #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK … #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT … #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK … #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT … #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK … #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT … #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK … #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT … #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK … #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT … #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK … #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT … #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK … #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT … #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK … #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT … #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK … #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT … #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK … #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT … #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK … #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT … #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK … #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT … #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK … #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT … #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK … #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT … #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK … #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT … #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK … #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT … #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK … #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT … #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK … #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT … #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK … #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT … #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK … #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT … #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK … #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT … #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK … #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT … #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK … #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT … #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK … #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT … #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK … #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT … #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK … #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT … #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK … #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT … #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK … #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT … #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK … #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT … #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK … #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT … #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK … #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT … #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK … #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT … #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK … #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT … #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK … #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT … #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK … #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT … #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK … #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT … #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK … #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK … #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK … #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK … #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT … #define DC_ABM1_CNTL__ABM1_EN_MASK … #define DC_ABM1_CNTL__ABM1_EN__SHIFT … #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK … #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT … #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK … #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK … #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK … #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT … #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK … #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT … #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK … #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT … #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK … #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT … #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK … #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT … #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK … #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK … #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT … #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK … #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT … #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK … #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT … #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK … #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT … #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK … #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT … #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK … #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT … #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK … #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT … #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK … #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT … #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK … #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK … #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT … #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK … #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT … #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK … #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK … #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK … #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT … #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK … #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT … #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK … #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT … #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK … #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT … #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK … #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT … #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK … #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT … #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK … #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT … #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK … #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT … #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK … #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT … #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK … #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT … #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK … #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT … #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK … #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT … #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK … #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT … #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK … #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT … #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK … #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT … #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK … #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT … #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK … #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT … #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK … #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT … #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK … #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT … #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK … #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT … #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK … #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT … #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK … #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT … #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK … #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT … #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK … #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT … #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK … #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT … #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK … #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT … #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK … #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT … #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK … #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT … #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK … #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT … #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK … #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK … #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT … #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK … #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT … #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK … #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT … #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK … #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT … #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK … #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK … #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT … #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK … #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT … #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK … #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT … #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK … #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK … #define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT … #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT … #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK … #define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT … #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK … #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT … #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK … #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT … #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK … #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT … #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK … #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT … #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK … #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT … #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK … #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT … #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK … #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT … #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK … #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT … #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK … #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT … #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK … #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT … #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK … #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT … #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK … #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT … #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK … #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT … #define CRTC_VBI_END__CRTC_VBI_V_END_MASK … #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT … #define CRTC_VBI_END__CRTC_VBI_H_END_MASK … #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT … #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK … #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT … #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK … #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT … #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK … #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT … #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK … #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT … #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK … #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK … #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT … #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK … #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT … #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK … #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT … #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK … #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT … #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK … #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT … #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK … #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT … #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK … #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT … #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK … #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT … #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK … #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT … #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK … #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT … #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK … #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT … #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK … #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT … #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK … #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT … #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK … #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT … #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK … #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK … #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT … #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK … #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK … #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT … #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK … #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK … #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK … #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK … #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT … #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK … #define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT … #define CRTC_CONTROL__CRTC_MASTER_EN_MASK … #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT … #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK … #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT … #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK … #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT … #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK … #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT … #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK … #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT … #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK … #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT … #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK … #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT … #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK … #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT … #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK … #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT … #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK … #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT … #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK … #define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT … #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK … #define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT … #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK … #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT … #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK … #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT … #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK … #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT … #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK … #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT … #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK … #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT … #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK … #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT … #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK … #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT … #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK … #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT … #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK … #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT … #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK … #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT … #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK … #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT … #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK … #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT … #define CRTC_STATUS__CRTC_V_BLANK_MASK … #define CRTC_STATUS__CRTC_V_BLANK__SHIFT … #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK … #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT … #define CRTC_STATUS__CRTC_V_SYNC_A_MASK … #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT … #define CRTC_STATUS__CRTC_V_UPDATE_MASK … #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT … #define CRTC_STATUS__CRTC_V_START_LINE_MASK … #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT … #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK … #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT … #define CRTC_STATUS__CRTC_H_BLANK_MASK … #define CRTC_STATUS__CRTC_H_BLANK__SHIFT … #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK … #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT … #define CRTC_STATUS__CRTC_H_SYNC_A_MASK … #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT … #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK … #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT … #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK … #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT … #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK … #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT … #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK … #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT … #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK … #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT … #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK … #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT … #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK … #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT … #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK … #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT … #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK … #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT … #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK … #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT … #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK … #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT … #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK … #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT … #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK … #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT … #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK … #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT … #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK … #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT … #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK … #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT … #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK … #define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT … #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK … #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK … #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK … #define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK … #define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT … #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK … #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK … #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT … #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK … #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT … #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK … #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT … #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK … #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT … #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK … #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT … #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK … #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT … #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK … #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT … #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK … #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT … #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK … #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT … #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK … #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT … #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK … #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT … #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK … #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK … #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT … #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK … #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK … #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK … #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT … #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK … #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT … #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK … #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT … #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK … #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT … #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK … #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT … #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK … #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT … #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK … #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT … #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK … #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT … #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK … #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT … #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK … #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT … #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK … #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT … #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK … #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT … #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK … #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT … #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK … #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT … #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK … #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT … #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK … #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT … #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK … #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT … #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK … #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT … #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK … #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK … #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK … #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK … #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK … #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK … #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK … #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK … #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK … #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK … #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK … #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK … #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK … #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK … #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK … #define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK … #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK … #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK … #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK … #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK … #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT … #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK … #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT … #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK … #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT … #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK … #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT … #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK … #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT … #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK … #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT … #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK … #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT … #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK … #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT … #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK … #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT … #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK … #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT … #define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK … #define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT … #define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK … #define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT … #define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK … #define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT … #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK … #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT … #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK … #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT … #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK … #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT … #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK … #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT … #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK … #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT … #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK … #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT … #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK … #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT … #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK … #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT … #define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK … #define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT … #define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK … #define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT … #define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK … #define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK … #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT … #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK … #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT … #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK … #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT … #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK … #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT … #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK … #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK … #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK … #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK … #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK … #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK … #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK … #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT … #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK … #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT … #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK … #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT … #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK … #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT … #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK … #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT … #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK … #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT … #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK … #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT … #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK … #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT … #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK … #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT … #define DAC_ENABLE__DAC_ENABLE_MASK … #define DAC_ENABLE__DAC_ENABLE__SHIFT … #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK … #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT … #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK … #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT … #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK … #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT … #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK … #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT … #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK … #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT … #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK … #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT … #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK … #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT … #define DAC_CRC_EN__DAC_CRC_EN_MASK … #define DAC_CRC_EN__DAC_CRC_EN__SHIFT … #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK … #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT … #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK … #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT … #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK … #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK … #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT … #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK … #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK … #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT … #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK … #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT … #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK … #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT … #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK … #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT … #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK … #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT … #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK … #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK … #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT … #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK … #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT … #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK … #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT … #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK … #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT … #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK … #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK … #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT … #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK … #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT … #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK … #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK … #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT … #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK … #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT … #define DAC_POWERDOWN__DAC_POWERDOWN_MASK … #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT … #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK … #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT … #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK … #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT … #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK … #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT … #define DAC_CONTROL__DAC_DFORCE_EN_MASK … #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT … #define DAC_CONTROL__DAC_TV_ENABLE_MASK … #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT … #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK … #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT … #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK … #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT … #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK … #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT … #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK … #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT … #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK … #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT … #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK … #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK … #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT … #define DAC_PWR_CNTL__DAC_BG_MODE_MASK … #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT … #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK … #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT … #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK … #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT … #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK … #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT … #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK … #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT … #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK … #define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT … #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK … #define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK … #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK … #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT … #define PERFMON_CNTL__PERFMON_STATE_MASK … #define PERFMON_CNTL__PERFMON_STATE__SHIFT … #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK … #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT … #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK … #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT … #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK … #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK … #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT … #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK … #define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK … #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT … #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK … #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT … #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK … #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT … #define PERFMON_HI__PERFMON_HI_MASK … #define PERFMON_HI__PERFMON_HI__SHIFT … #define PERFMON_HI__PERFMON_READ_SEL_MASK … #define PERFMON_HI__PERFMON_READ_SEL__SHIFT … #define PERFMON_LOW__PERFMON_LOW_MASK … #define PERFMON_LOW__PERFMON_LOW__SHIFT … #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK … #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT … #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK … #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT … #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK … #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT … #define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK … #define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT … #define REFCLK_CNTL__REFCLK_SRC_SEL_MASK … #define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT … #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK … #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT … #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK … #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT … #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK … #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT … #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK … #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT … #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK … #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT … #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK … #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT … #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK … #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT … #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK … #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT … #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK … #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT … #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK … #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT … #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK … #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT … #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK … #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK … #define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK … #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK … #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK … #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK … #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT … #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK … #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT … #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK … #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK … #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT … #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK … #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT … #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK … #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT … #define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT … #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK … #define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT … #define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK … #define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK … #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT … #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK … #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT … #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK … #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT … #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK … #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT … #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK … #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT … #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK … #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT … #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK … #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT … #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK … #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT … #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK … #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT … #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK … #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT … #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK … #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT … #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK … #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT … #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK … #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT … #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK … #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT … #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK … #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT … #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK … #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT … #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK … #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT … #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK … #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT … #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK … #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT … #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK … #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT … #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK … #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT … #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK … #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT … #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK … #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK … #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT … #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK … #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT … #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK … #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT … #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK … #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT … #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK … #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK … #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT … #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK … #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT … #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK … #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT … #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK … #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT … #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK … #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK … #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK … #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK … #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK … #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT … #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK … #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK … #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK … #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK … #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK … #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT … #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK … #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK … #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK … #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK … #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK … #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT … #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK … #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK … #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK … #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK … #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK … #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT … #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK … #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK … #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK … #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK … #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK … #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT … #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK … #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK … #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK … #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK … #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT … #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK … #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT … #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK … #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT … #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK … #define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT … #define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK … #define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT … #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT … #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK … #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK … #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK … #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK … #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK … #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK … #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK … #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT … #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK … #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT … #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK … #define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT … #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK … #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT … #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK … #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT … #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK … #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT … #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK … #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT … #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK … #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK … #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT … #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK … #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT … #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK … #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT … #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK … #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT … #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK … #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT … #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK … #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT … #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK … #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT … #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK … #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK … #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT … #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK … #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT … #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK … #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT … #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK … #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT … #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK … #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT … #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK … #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT … #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK … #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT … #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK … #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK … #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT … #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK … #define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT … #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK … #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK … #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT … #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK … #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT … #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK … #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT … #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK … #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT … #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK … #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT … #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK … #define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK … #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT … #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK … #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT … #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK … #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT … #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK … #define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT … #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK … #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT … #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK … #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT … #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK … #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT … #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK … #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT … #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK … #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT … #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK … #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT … #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK … #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT … #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK … #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT … #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK … #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT … #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK … #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT … #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK … #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT … #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK … #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT … #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK … #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT … #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK … #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT … #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK … #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT … #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK … #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT … #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK … #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT … #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK … #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT … #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK … #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK … #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT … #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK … #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT … #define DMIF_STATUS__DMIF_UNDERFLOW_MASK … #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT … #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK … #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT … #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK … #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT … #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK … #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT … #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK … #define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE0_MASK … #define DMIF_P_VMID__P_VMID_PIPE0__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE1_MASK … #define DMIF_P_VMID__P_VMID_PIPE1__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE2_MASK … #define DMIF_P_VMID__P_VMID_PIPE2__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE3_MASK … #define DMIF_P_VMID__P_VMID_PIPE3__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE4_MASK … #define DMIF_P_VMID__P_VMID_PIPE4__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE5_MASK … #define DMIF_P_VMID__P_VMID_PIPE5__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE6_MASK … #define DMIF_P_VMID__P_VMID_PIPE6__SHIFT … #define DMIF_P_VMID__P_VMID_PIPE7_MASK … #define DMIF_P_VMID__P_VMID_PIPE7__SHIFT … #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK … #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT … #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK … #define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT … #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK … #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT … #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK … #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT … #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK … #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT … #define DMIF_DEBUG02_CORE0__DB_DATA_MASK … #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT … #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK … #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT … #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK … #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT … #define DMIF_DEBUG02_CORE1__DB_DATA_MASK … #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT … #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK … #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT … #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK … #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT … #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK … #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT … #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK … #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT … #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT … #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK … #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT … #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK … #define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK … #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT … #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK … #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT … #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK … #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT … #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK … #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT … #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK … #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT … #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK … #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT … #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK … #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT … #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK … #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT … #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK … #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT … #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK … #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT … #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK … #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT … #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK … #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT … #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK … #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT … #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK … #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT … #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK … #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT … #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK … #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT … #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK … #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT … #define MCIF_VMID__MCIF_WR_VMID_MASK … #define MCIF_VMID__MCIF_WR_VMID__SHIFT … #define MCIF_VMID__VIP_WR_VMID_MASK … #define MCIF_VMID__VIP_WR_VMID__SHIFT … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK … #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT … #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK … #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT … #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK … #define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT … #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK … #define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK … #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK … #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK … #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK … #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK … #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT … #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK … #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT … #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK … #define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK … #define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT … #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK … #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT … #define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK … #define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT … #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK … #define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT … #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK … #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT … #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK … #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT … #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK … #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT … #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT … #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK … #define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT … #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK … #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT … #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK … #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK … #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__VPCLK_POL_MASK … #define DCI_CLK_CNTL__VPCLK_POL__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK … #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK … #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK … #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK … #define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT … #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK … #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT … #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK … #define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT … #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK … #define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT … #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK … #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK … #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK … #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK … #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK … #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK … #define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK … #define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT … #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK … #define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT … #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK … #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT … #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK … #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT … #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK … #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT … #define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK … #define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT … #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK … #define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT … #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK … #define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT … #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK … #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT … #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK … #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT … #define DC_GENERICA__GENERICA_EN_MASK … #define DC_GENERICA__GENERICA_EN__SHIFT … #define DC_GENERICA__GENERICA_SEL_MASK … #define DC_GENERICA__GENERICA_SEL__SHIFT … #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK … #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK … #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT … #define DC_GENERICB__GENERICB_EN_MASK … #define DC_GENERICB__GENERICB_EN__SHIFT … #define DC_GENERICB__GENERICB_SEL_MASK … #define DC_GENERICB__GENERICB_SEL__SHIFT … #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK … #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK … #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT … #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK … #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT … #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK … #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT … #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK … #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK … #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT … #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK … #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT … #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK … #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT … #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK … #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT … #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK … #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT … #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK … #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT … #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK … #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK … #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK … #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK … #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK … #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK … #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK … #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK … #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT … #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK … #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT … #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK … #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT … #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK … #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT … #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK … #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT … #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK … #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT … #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK … #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT … #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK … #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT … #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK … #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT … #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK … #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT … #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK … #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT … #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK … #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT … #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK … #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT … #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK … #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT … #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK … #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT … #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK … #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK … #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT … #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK … #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT … #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK … #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT … #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK … #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK … #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT … #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK … #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT … #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK … #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT … #define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK … #define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT … #define DCIO_WRCMD_DELAY__DAC_DELAY_MASK … #define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT … #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK … #define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT … #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK … #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT … #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK … #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT … #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK … #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT … #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK … #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT … #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK … #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT … #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK … #define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT … #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK … #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT … #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK … #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT … #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK … #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK … #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK … #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK … #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT … #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK … #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK … #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT … #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK … #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT … #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK … #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT … #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK … #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT … #define BL_PWM_CNTL__BL_PWM_EN_MASK … #define BL_PWM_CNTL__BL_PWM_EN__SHIFT … #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK … #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT … #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK … #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT … #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK … #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT … #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK … #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT … #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK … #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT … #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK … #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK … #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK … #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK … #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT … #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK … #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT … #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK … #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK … #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT … #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK … #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT … #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK … #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK … #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT … #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK … #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT … #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK … #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT … #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK … #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK … #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK … #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT … #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK … #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK … #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT … #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK … #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT … #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK … #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT … #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK … #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT … #define DCIO_DEBUG__DCIO_DEBUG_MASK … #define DCIO_DEBUG__DCIO_DEBUG__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK … #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT … #define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK … #define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT … #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK … #define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT … #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK … #define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT … #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK … #define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT … #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK … #define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT … #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT … #define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK … #define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT … #define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK … #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT … #define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK … #define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT … #define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK … #define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT … #define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK … #define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT … #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK … #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT … #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK … #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT … #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK … #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK … #define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK … #define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT … #define DCIO_DEBUG2__DCIO_DEBUG2_MASK … #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT … #define DCIO_DEBUG3__DCIO_DEBUG3_MASK … #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT … #define DCIO_DEBUG4__DCIO_DEBUG4_MASK … #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT … #define DCIO_DEBUG5__DCIO_DEBUG5_MASK … #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT … #define DCIO_DEBUG6__DCIO_DEBUG6_MASK … #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT … #define DCIO_DEBUG7__DCIO_DEBUG7_MASK … #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT … #define DCIO_DEBUG8__DCIO_DEBUG8_MASK … #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT … #define DCIO_DEBUG9__DCIO_DEBUG9_MASK … #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT … #define DCIO_DEBUGA__DCIO_DEBUGA_MASK … #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT … #define DCIO_DEBUGB__DCIO_DEBUGB_MASK … #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT … #define DCIO_DEBUGC__DCIO_DEBUGC_MASK … #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT … #define DCIO_DEBUGD__DCIO_DEBUGD_MASK … #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT … #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK … #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT … #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK … #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT … #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK … #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT … #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK … #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT … #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK … #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT … #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK … #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT … #define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK … #define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT … #define DCIO_DEBUG15__DCIO_DEBUG15_MASK … #define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT … #define DCIO_DEBUG16__DCIO_DEBUG16_MASK … #define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT … #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK … #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK … #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK … #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK … #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK … #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK … #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT … #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK … #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT … #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK … #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT … #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK … #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT … #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK … #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT … #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK … #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK … #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT … #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK … #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK … #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT … #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK … #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT … #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK … #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT … #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK … #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT … #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK … #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK … #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT … #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK … #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT … #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK … #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT … #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK … #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT … #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK … #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT … #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK … #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT … #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK … #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT … #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK … #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT … #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK … #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT … #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK … #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK … #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT … #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK … #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT … #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK … #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT … #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK … #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT … #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK … #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT … #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK … #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT … #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK … #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT … #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK … #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT … #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK … #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT … #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK … #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK … #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT … #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK … #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT … #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK … #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT … #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK … #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT … #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK … #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT … #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK … #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT … #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK … #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT … #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK … #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT … #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK … #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT … #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK … #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK … #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT … #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK … #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT … #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK … #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT … #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK … #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT … #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK … #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT … #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK … #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT … #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK … #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT … #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK … #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT … #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK … #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT … #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK … #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK … #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT … #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK … #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT … #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK … #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT … #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK … #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT … #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK … #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT … #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK … #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT … #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK … #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT … #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK … #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT … #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK … #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT … #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK … #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK … #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT … #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK … #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT … #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK … #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT … #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK … #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT … #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK … #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT … #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK … #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT … #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK … #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT … #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK … #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT … #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK … #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT … #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK … #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK … #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT … #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK … #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT … #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK … #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT … #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK … #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT … #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK … #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT … #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK … #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT … #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK … #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK … #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT … #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK … #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT … #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK … #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT … #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK … #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT … #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK … #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT … #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK … #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT … #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK … #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK … #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT … #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK … #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT … #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK … #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT … #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK … #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT … #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK … #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT … #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK … #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT … #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK … #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT … #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK … #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT … #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK … #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT … #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK … #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT … #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK … #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT … #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK … #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT … #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK … #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK … #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT … #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK … #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT … #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK … #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT … #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK … #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT … #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK … #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT … #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK … #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT … #define DC_GPIO_HPD_EN__HPD1_SEL0_MASK … #define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT … #define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK … #define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT … #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK … #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT … #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK … #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK … #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT … #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK … #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT … #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK … #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT … #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK … #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT … #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK … #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT … #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK … #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK … #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK … #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK … #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK … #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK … #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK … #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK … #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT … #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK … #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK … #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK … #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK … #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK … #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK … #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK … #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT … #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK … #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT … #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK … #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT … #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK … #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT … #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK … #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK … #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT … #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK … #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT … #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK … #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT … #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK … #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT … #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK … #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT … #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK … #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT … #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK … #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT … #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK … #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT … #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK … #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT … #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK … #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT … #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK … #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT … #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK … #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT … #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK … #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT … #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK … #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT … #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK … #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT … #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK … #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT … #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK … #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT … #define DVO_STRENGTH_CONTROL__DVO_SP_MASK … #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT … #define DVO_STRENGTH_CONTROL__DVO_SN_MASK … #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT … #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK … #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT … #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK … #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT … #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK … #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT … #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK … #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT … #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK … #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT … #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK … #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT … #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK … #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT … #define DVO_VREF_CONTROL__DVO_VREFPON_MASK … #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT … #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK … #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT … #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK … #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT … #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK … #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT … #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK … #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT … #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK … #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT … #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK … #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT … #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK … #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK … #define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK … #define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK … #define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT … #define GRPH_ENABLE__GRPH_ENABLE_MASK … #define GRPH_ENABLE__GRPH_ENABLE__SHIFT … #define GRPH_CONTROL__GRPH_DEPTH_MASK … #define GRPH_CONTROL__GRPH_DEPTH__SHIFT … #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK … #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT … #define GRPH_CONTROL__GRPH_Z_MASK … #define GRPH_CONTROL__GRPH_Z__SHIFT … #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK … #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT … #define GRPH_CONTROL__GRPH_FORMAT_MASK … #define GRPH_CONTROL__GRPH_FORMAT__SHIFT … #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK … #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT … #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK … #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT … #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK … #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT … #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK … #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT … #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK … #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT … #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK … #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT … #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK … #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT … #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK … #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT … #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK … #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT … #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK … #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT … #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK … #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT … #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK … #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT … #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK … #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT … #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK … #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT … #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK … #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT … #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK … #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT … #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK … #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT … #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK … #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT … #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK … #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT … #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK … #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT … #define GRPH_PITCH__GRPH_PITCH_MASK … #define GRPH_PITCH__GRPH_PITCH__SHIFT … #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK … #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT … #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK … #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT … #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK … #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT … #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK … #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT … #define GRPH_X_START__GRPH_X_START_MASK … #define GRPH_X_START__GRPH_X_START__SHIFT … #define GRPH_Y_START__GRPH_Y_START_MASK … #define GRPH_Y_START__GRPH_Y_START__SHIFT … #define GRPH_X_END__GRPH_X_END_MASK … #define GRPH_X_END__GRPH_X_END__SHIFT … #define GRPH_Y_END__GRPH_Y_END_MASK … #define GRPH_Y_END__GRPH_Y_END__SHIFT … #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK … #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT … #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK … #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT … #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK … #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT … #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK … #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT … #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK … #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT … #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK … #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT … #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK … #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT … #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK … #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT … #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK … #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT … #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK … #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT … #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK … #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT … #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK … #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT … #define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK … #define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT … #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK … #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT … #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK … #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT … #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK … #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT … #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK … #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT … #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK … #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT … #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK … #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT … #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK … #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT … #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK … #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK … #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT … #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK … #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT … #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK … #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT … #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK … #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT … #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK … #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT … #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK … #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT … #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK … #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT … #define OVL_ENABLE__OVL_ENABLE_MASK … #define OVL_ENABLE__OVL_ENABLE__SHIFT … #define OVL_ENABLE__OVLSCL_EN_MASK … #define OVL_ENABLE__OVLSCL_EN__SHIFT … #define OVL_CONTROL1__OVL_DEPTH_MASK … #define OVL_CONTROL1__OVL_DEPTH__SHIFT … #define OVL_CONTROL1__OVL_NUM_BANKS_MASK … #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT … #define OVL_CONTROL1__OVL_Z_MASK … #define OVL_CONTROL1__OVL_Z__SHIFT … #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK … #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT … #define OVL_CONTROL1__OVL_FORMAT_MASK … #define OVL_CONTROL1__OVL_FORMAT__SHIFT … #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK … #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT … #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK … #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT … #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK … #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT … #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK … #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT … #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK … #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT … #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK … #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT … #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK … #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT … #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK … #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT … #define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK … #define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT … #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK … #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT … #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK … #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT … #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK … #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT … #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK … #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT … #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK … #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT … #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK … #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT … #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK … #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT … #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK … #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT … #define OVL_PITCH__OVL_PITCH_MASK … #define OVL_PITCH__OVL_PITCH__SHIFT … #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK … #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT … #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK … #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT … #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK … #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT … #define OVL_START__OVL_Y_START_MASK … #define OVL_START__OVL_Y_START__SHIFT … #define OVL_START__OVL_X_START_MASK … #define OVL_START__OVL_X_START__SHIFT … #define OVL_END__OVL_Y_END_MASK … #define OVL_END__OVL_Y_END__SHIFT … #define OVL_END__OVL_X_END_MASK … #define OVL_END__OVL_X_END__SHIFT … #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK … #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT … #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK … #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT … #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK … #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT … #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK … #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT … #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK … #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT … #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK … #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT … #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK … #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT … #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK … #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT … #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK … #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT … #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK … #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT … #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK … #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT … #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK … #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT … #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK … #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK … #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK … #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT … #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK … #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT … #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK … #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT … #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK … #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT … #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK … #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT … #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK … #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT … #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK … #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK … #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT … #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK … #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT … #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK … #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT … #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK … #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT … #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK … #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT … #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK … #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT … #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK … #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT … #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK … #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT … #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK … #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT … #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK … #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT … #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK … #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT … #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK … #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT … #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK … #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT … #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK … #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT … #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK … #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT … #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK … #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT … #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK … #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT … #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK … #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT … #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK … #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT … #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK … #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT … #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK … #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT … #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK … #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT … #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK … #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT … #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK … #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT … #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK … #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT … #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK … #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT … #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK … #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT … #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK … #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT … #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK … #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT … #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK … #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT … #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK … #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT … #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK … #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT … #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK … #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT … #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK … #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT … #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK … #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT … #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK … #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT … #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK … #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT … #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK … #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT … #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK … #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT … #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK … #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT … #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK … #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT … #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK … #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT … #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK … #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT … #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK … #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT … #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK … #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT … #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK … #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT … #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK … #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT … #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK … #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT … #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK … #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT … #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK … #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT … #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK … #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT … #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK … #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT … #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK … #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT … #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK … #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT … #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK … #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT … #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK … #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT … #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK … #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT … #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK … #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT … #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK … #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT … #define DENORM_CONTROL__DENORM_MODE_MASK … #define DENORM_CONTROL__DENORM_MODE__SHIFT … #define DENORM_CONTROL__DENORM_14BIT_OUT_MASK … #define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT … #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK … #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT … #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK … #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT … #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK … #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT … #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK … #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT … #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK … #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT … #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK … #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT … #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK … #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT … #define KEY_CONTROL__KEY_SELECT_MASK … #define KEY_CONTROL__KEY_SELECT__SHIFT … #define KEY_CONTROL__KEY_MODE_MASK … #define KEY_CONTROL__KEY_MODE__SHIFT … #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK … #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT … #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK … #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT … #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK … #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT … #define KEY_RANGE_RED__KEY_RED_LOW_MASK … #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT … #define KEY_RANGE_RED__KEY_RED_HIGH_MASK … #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT … #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK … #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT … #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK … #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT … #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK … #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT … #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK … #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT … #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK … #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT … #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK … #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT … #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK … #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT … #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK … #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT … #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK … #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT … #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK … #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT … #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK … #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT … #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK … #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT … #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK … #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT … #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK … #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT … #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK … #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT … #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK … #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT … #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK … #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT … #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK … #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT … #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK … #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT … #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK … #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT … #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK … #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT … #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK … #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT … #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK … #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT … #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK … #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT … #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK … #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT … #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK … #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT … #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK … #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT … #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK … #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT … #define CUR_CONTROL__CURSOR_EN_MASK … #define CUR_CONTROL__CURSOR_EN__SHIFT … #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK … #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT … #define CUR_CONTROL__CURSOR_MODE_MASK … #define CUR_CONTROL__CURSOR_MODE__SHIFT … #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK … #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT … #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK … #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT … #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK … #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT … #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK … #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT … #define CUR_SIZE__CURSOR_HEIGHT_MASK … #define CUR_SIZE__CURSOR_HEIGHT__SHIFT … #define CUR_SIZE__CURSOR_WIDTH_MASK … #define CUR_SIZE__CURSOR_WIDTH__SHIFT … #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK … #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT … #define CUR_POSITION__CURSOR_Y_POSITION_MASK … #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT … #define CUR_POSITION__CURSOR_X_POSITION_MASK … #define CUR_POSITION__CURSOR_X_POSITION__SHIFT … #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK … #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT … #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK … #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT … #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK … #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT … #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK … #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT … #define CUR_COLOR1__CUR_COLOR1_RED_MASK … #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT … #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK … #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT … #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK … #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT … #define CUR_COLOR2__CUR_COLOR2_RED_MASK … #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT … #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK … #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT … #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK … #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT … #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK … #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT … #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK … #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT … #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK … #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT … #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK … #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT … #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK … #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT … #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK … #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT … #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK … #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT … #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK … #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT … #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK … #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT … #define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK … #define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT … #define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK … #define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT … #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK … #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT … #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK … #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT … #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK … #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT … #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK … #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK … #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT … #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK … #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT … #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK … #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT … #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK … #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT … #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK … #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT … #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK … #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT … #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK … #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT … #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK … #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT … #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK … #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT … #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK … #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT … #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK … #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT … #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK … #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT … #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK … #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT … #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK … #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT … #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK … #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT … #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK … #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT … #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK … #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT … #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK … #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT … #define DCP_CRC_MASK__DCP_CRC_MASK_MASK … #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT … #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK … #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT … #define DCP_CRC_LAST__DCP_CRC_LAST_MASK … #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT … #define DCP_DEBUG__DCP_DEBUG_MASK … #define DCP_DEBUG__DCP_DEBUG__SHIFT … #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK … #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT … #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK … #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK … #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK … #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK … #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK … #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK … #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK … #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK … #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK … #define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK … #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK … #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT … #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK … #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT … #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK … #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT … #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK … #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT … #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK … #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT … #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK … #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT … #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK … #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT … #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK … #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK … #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT … #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK … #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT … #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK … #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT … #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK … #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT … #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK … #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT … #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK … #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT … #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK … #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK … #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT … #define DCP_DEBUG2__DCP_DEBUG2_MASK … #define DCP_DEBUG2__DCP_DEBUG2__SHIFT … #define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK … #define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT … #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK … #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT … #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK … #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT … #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK … #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT … #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK … #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT … #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK … #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT … #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK … #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT … #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK … #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT … #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK … #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT … #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK … #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT … #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK … #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT … #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK … #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK … #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT … #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK … #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT … #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK … #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT … #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK … #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT … #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK … #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT … #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK … #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK … #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT … #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK … #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT … #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK … #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT … #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK … #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT … #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK … #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK … #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT … #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK … #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT … #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK … #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT … #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK … #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT … #define DIG_FE_CNTL__DIG_START_MASK … #define DIG_FE_CNTL__DIG_START__SHIFT … #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK … #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT … #define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK … #define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT … #define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK … #define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK … #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT … #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK … #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT … #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK … #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT … #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK … #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT … #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK … #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT … #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK … #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT … #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK … #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT … #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK … #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT … #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK … #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT … #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK … #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT … #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK … #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT … #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK … #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT … #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK … #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT … #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK … #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT … #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK … #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK … #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT … #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK … #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT … #define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK … #define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT … #define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK … #define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT … #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK … #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT … #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK … #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT … #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK … #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT … #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK … #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT … #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK … #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT … #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK … #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT … #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK … #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT … #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK … #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT … #define HDMI_STATUS__HDMI_ERROR_INT_MASK … #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK … #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK … #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK … #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT … #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK … #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT … #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK … #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT … #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK … #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT … #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK … #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK … #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT … #define HDMI_GC__HDMI_GC_AVMUTE_MASK … #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT … #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK … #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT … #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK … #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT … #define HDMI_GC__HDMI_PACKING_PHASE_MASK … #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT … #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK … #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK … #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT … #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK … #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT … #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK … #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT … #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK … #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK … #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK … #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK … #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK … #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK … #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK … #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK … #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK … #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK … #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK … #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT … #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK … #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT … #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK … #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT … #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK … #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT … #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK … #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK … #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK … #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK … #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK … #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK … #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK … #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK … #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK … #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK … #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK … #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK … #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK … #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT … #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK … #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT … #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK … #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT … #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK … #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT … #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK … #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT … #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK … #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT … #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK … #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT … #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK … #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT … #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK … #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK … #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK … #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_A_MASK … #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_B_MASK … #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_C_MASK … #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_D_MASK … #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK … #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK … #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK … #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK … #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK … #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT … #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK … #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT … #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK … #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT … #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK … #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT … #define AFMT_60958_1__AFMT_60958_VALID_L_MASK … #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT … #define AFMT_60958_1__AFMT_60958_VALID_R_MASK … #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT … #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK … #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK … #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT … #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK … #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT … #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK … #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT … #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK … #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT … #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK … #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT … #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK … #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT … #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK … #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK … #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT … #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK … #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT … #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK … #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT … #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK … #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT … #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK … #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT … #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK … #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT … #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK … #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK … #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK … #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT … #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK … #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT … #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK … #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT … #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK … #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT … #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK … #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK … #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT … #define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK … #define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT … #define DIG_BE_CNTL__DIG_SWAP_MASK … #define DIG_BE_CNTL__DIG_SWAP__SHIFT … #define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK … #define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT … #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK … #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT … #define DIG_BE_CNTL__DIG_MODE_MASK … #define DIG_BE_CNTL__DIG_MODE__SHIFT … #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK … #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT … #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK … #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT … #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK … #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT … #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK … #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK … #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT … #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK … #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT … #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK … #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT … #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK … #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT … #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK … #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT … #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK … #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT … #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK … #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT … #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK … #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK … #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK … #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK … #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK … #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK … #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK … #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT … #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK … #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT … #define TMDS_CTL_BITS__TMDS_CTL0_MASK … #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT … #define TMDS_CTL_BITS__TMDS_CTL1_MASK … #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT … #define TMDS_CTL_BITS__TMDS_CTL2_MASK … #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT … #define TMDS_CTL_BITS__TMDS_CTL3_MASK … #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT … #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK … #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK … #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT … #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK … #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK … #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK … #define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK … #define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK … #define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT … #define TMDS_DEBUG7__DBG_DIG_TMDS7_MASK … #define TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT … #define TMDS_DEBUG8__DBG_DIG_TMDS8_MASK … #define TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT … #define TMDS_DEBUG9__DBG_DIG_TMDS9_MASK … #define TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT … #define TMDS_DEBUG10__DBG_DIG_TMDS10_MASK … #define TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT … #define TMDS_DEBUG11__DBG_DIG_TMDS11_MASK … #define TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT … #define TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK … #define TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT … #define TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK … #define TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT … #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK … #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT … #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK … #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK … #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT … #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK … #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT … #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK … #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT … #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK … #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT … #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK … #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT … #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK … #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT … #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK … #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT … #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK … #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT … #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK … #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT … #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK … #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT … #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK … #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT … #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK … #define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT … #define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK … #define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT … #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK … #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT … #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK … #define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT … #define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK … #define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT … #define DMCU_CTRL__RESET_UC_MASK … #define DMCU_CTRL__RESET_UC__SHIFT … #define DMCU_CTRL__IGNORE_PWRMGT_MASK … #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT … #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK … #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT … #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK … #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT … #define DMCU_CTRL__DMCU_ENABLE_MASK … #define DMCU_CTRL__DMCU_ENABLE__SHIFT … #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK … #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT … #define DMCU_STATUS__UC_IN_RESET_MASK … #define DMCU_STATUS__UC_IN_RESET__SHIFT … #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK … #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT … #define DMCU_STATUS__UC_IN_STOP_MODE_MASK … #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT … #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK … #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT … #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK … #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT … #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK … #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT … #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK … #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT … #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK … #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT … #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK … #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT … #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK … #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT … #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK … #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT … #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK … #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT … #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK … #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT … #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK … #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT … #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK … #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT … #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK … #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT … #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK … #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT … #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK … #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT … #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK … #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT … #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK … #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT … #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK … #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT … #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK … #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT … #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK … #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT … #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK … #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT … #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK … #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT … #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK … #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT … #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK … #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT … #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK … #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT … #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK … #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT … #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK … #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT … #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK … #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT … #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK … #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT … #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK … #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT … #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK … #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT … #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK … #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK … #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK … #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT … #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK … #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK … #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK … #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT … #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK … #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT … #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK … #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT … #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK … #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT … #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK … #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT … #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK … #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT … #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK … #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT … #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK … #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT … #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK … #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT … #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK … #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK … #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK … #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK … #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK … #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK … #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK … #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK … #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK … #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK … #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT … #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK … #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT … #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK … #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT … #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK … #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT … #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK … #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT … #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK … #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK … #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK … #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK … #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK … #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT … #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK … #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT … #define DP_LINK_CNTL__DP_LINK_STATUS_MASK … #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT … #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK … #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT … #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK … #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT … #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK … #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT … #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK … #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT … #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK … #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT … #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK … #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT … #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK … #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT … #define DP_CONFIG__DP_UDI_LANES_MASK … #define DP_CONFIG__DP_UDI_LANES__SHIFT … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK … #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT … #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK … #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK … #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT … #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK … #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT … #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK … #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT … #define DP_MSA_MISC__DP_MSA_MISC1_MASK … #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT … #define DP_MSA_MISC__DP_MSA_MISC2_MASK … #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT … #define DP_MSA_MISC__DP_MSA_MISC3_MASK … #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT … #define DP_MSA_MISC__DP_MSA_MISC4_MASK … #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT … #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK … #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT … #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK … #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT … #define DP_VID_TIMING__DP_VID_N_DIV_MASK … #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT … #define DP_VID_N__DP_VID_N_MASK … #define DP_VID_N__DP_VID_N__SHIFT … #define DP_VID_M__DP_VID_M_MASK … #define DP_VID_M__DP_VID_M__SHIFT … #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK … #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT … #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK … #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT … #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK … #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT … #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK … #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT … #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK … #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT … #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK … #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT … #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK … #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK … #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK … #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT … #define DP_DPHY_CNTL__DPHY_BYPASS_MASK … #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT … #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK … #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT … #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK … #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT … #define DP_DPHY_SYM0__DPHY_SYM1_MASK … #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT … #define DP_DPHY_SYM0__DPHY_SYM2_MASK … #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT … #define DP_DPHY_SYM0__DPHY_SYM3_MASK … #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT … #define DP_DPHY_SYM1__DPHY_SYM4_MASK … #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT … #define DP_DPHY_SYM1__DPHY_SYM5_MASK … #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT … #define DP_DPHY_SYM1__DPHY_SYM6_MASK … #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT … #define DP_DPHY_SYM2__DPHY_SYM7_MASK … #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT … #define DP_DPHY_SYM2__DPHY_SYM8_MASK … #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK … #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK … #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT … #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK … #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT … #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK … #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT … #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK … #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT … #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK … #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT … #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK … #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT … #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK … #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT … #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK … #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT … #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK … #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK … #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT … #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK … #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT … #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK … #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK … #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT … #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK … #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT … #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK … #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK … #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK … #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT … #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK … #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT … #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK … #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT … #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK … #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT … #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK … #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT … #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT … #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK … #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT … #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK … #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT … #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK … #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT … #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK … #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT … #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK … #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT … #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK … #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT … #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK … #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT … #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK … #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT … #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK … #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT … #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK … #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT … #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK … #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT … #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK … #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT … #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK … #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT … #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK … #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT … #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK … #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT … #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK … #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT … #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK … #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT … #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK … #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK … #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT … #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK … #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT … #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK … #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT … #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK … #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT … #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK … #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT … #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK … #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT … #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK … #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT … #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK … #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT … #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK … #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT … #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK … #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT … #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK … #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT … #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK … #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT … #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK … #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT … #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK … #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT … #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK … #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT … #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK … #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT … #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK … #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT … #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK … #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT … #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK … #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT … #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK … #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT … #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK … #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT … #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK … #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT … #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK … #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT … #define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK … #define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT … #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK … #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT … #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK … #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT … #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK … #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT … #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK … #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT … #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK … #define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT … #define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK … #define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT … #define AUX_CONTROL__AUX_EN_MASK … #define AUX_CONTROL__AUX_EN__SHIFT … #define AUX_CONTROL__AUX_LS_READ_EN_MASK … #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT … #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK … #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT … #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK … #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT … #define AUX_CONTROL__AUX_MODE_DET_EN_MASK … #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT … #define AUX_CONTROL__AUX_HPD_SEL_MASK … #define AUX_CONTROL__AUX_HPD_SEL__SHIFT … #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK … #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT … #define AUX_CONTROL__AUX_TEST_MODE_MASK … #define AUX_CONTROL__AUX_TEST_MODE__SHIFT … #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK … #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT … #define AUX_CONTROL__SPARE_0_MASK … #define AUX_CONTROL__SPARE_0__SHIFT … #define AUX_CONTROL__SPARE_1_MASK … #define AUX_CONTROL__SPARE_1__SHIFT … #define AUX_SW_CONTROL__AUX_SW_GO_MASK … #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT … #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK … #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT … #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK … #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT … #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK … #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT … #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK … #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT … #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK … #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT … #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK … #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT … #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK … #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT … #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK … #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT … #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK … #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT … #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK … #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT … #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK … #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT … #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK … #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT … #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK … #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK … #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT … #define AUX_SW_STATUS__AUX_SW_DONE_MASK … #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT … #define AUX_SW_STATUS__AUX_SW_REQ_MASK … #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK … #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK … #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK … #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT … #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK … #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK … #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT … #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK … #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK … #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK … #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK … #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK … #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK … #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK … #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK … #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT … #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK … #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT … #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK … #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT … #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK … #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT … #define AUX_LS_STATUS__AUX_LS_DONE_MASK … #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT … #define AUX_LS_STATUS__AUX_LS_REQ_MASK … #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK … #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK … #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK … #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT … #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK … #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK … #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT … #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK … #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK … #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK … #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK … #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK … #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK … #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK … #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK … #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT … #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK … #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT … #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK … #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT … #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK … #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT … #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK … #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT … #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK … #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT … #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK … #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT … #define AUX_SW_DATA__AUX_SW_DATA_MASK … #define AUX_SW_DATA__AUX_SW_DATA__SHIFT … #define AUX_SW_DATA__AUX_SW_INDEX_MASK … #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT … #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK … #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT … #define AUX_LS_DATA__AUX_LS_DATA_MASK … #define AUX_LS_DATA__AUX_LS_DATA__SHIFT … #define AUX_LS_DATA__AUX_LS_INDEX_MASK … #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK … #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT … #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK … #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT … #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK … #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT … #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK … #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT … #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK … #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT … #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK … #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT … #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK … #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT … #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK … #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT … #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK … #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT … #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK … #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT … #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK … #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT … #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK … #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT … #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK … #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK … #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK … #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK … #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT … #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK … #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT … #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK … #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT … #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK … #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT … #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK … #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT … #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK … #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT … #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK … #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT … #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK … #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT … #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK … #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT … #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK … #define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT … #define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK … #define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT … #define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK … #define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT … #define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK … #define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT … #define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK … #define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT … #define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK … #define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT … #define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK … #define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT … #define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK … #define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT … #define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK … #define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT … #define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK … #define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT … #define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK … #define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT … #define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK … #define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT … #define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK … #define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT … #define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK … #define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT … #define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK … #define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT … #define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK … #define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT … #define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK … #define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT … #define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK … #define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT … #define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK … #define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT … #define DVO_ENABLE__DVO_ENABLE_MASK … #define DVO_ENABLE__DVO_ENABLE__SHIFT … #define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK … #define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT … #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK … #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT … #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK … #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT … #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK … #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT … #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK … #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT … #define DVO_CONTROL__DVO_RATE_SELECT_MASK … #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT … #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK … #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT … #define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK … #define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT … #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK … #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT … #define DVO_CONTROL__DVO_RESET_FIFO_MASK … #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT … #define DVO_CONTROL__DVO_SYNC_PHASE_MASK … #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT … #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK … #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT … #define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK … #define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT … #define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK … #define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT … #define DVO_CONTROL__DVO_DE_POLARITY_MASK … #define DVO_CONTROL__DVO_DE_POLARITY__SHIFT … #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK … #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT … #define DVO_CONTROL__DVO_CTL3_MASK … #define DVO_CONTROL__DVO_CTL3__SHIFT … #define DVO_CRC_EN__DVO_CRC2_EN_MASK … #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT … #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK … #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT … #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK … #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK … #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT … #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK … #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT … #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK … #define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT … #define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK … #define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT … #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK … #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT … #define FBC_CNTL__FBC_SRC_SEL_MASK … #define FBC_CNTL__FBC_SRC_SEL__SHIFT … #define FBC_CNTL__FBC_COHERENCY_MODE_MASK … #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT … #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK … #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT … #define FBC_CNTL__FBC_EN_MASK … #define FBC_CNTL__FBC_EN__SHIFT … #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK … #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT … #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK … #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT … #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK … #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT … #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK … #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT … #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK … #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT … #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK … #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT … #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK … #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT … #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK … #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT … #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK … #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT … #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK … #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT … #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK … #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT … #define FBC_COMP_MODE__FBC_RLE_EN_MASK … #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT … #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK … #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT … #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK … #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT … #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK … #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT … #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK … #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT … #define FBC_COMP_MODE__FBC_IND_EN_MASK … #define FBC_COMP_MODE__FBC_IND_EN__SHIFT … #define FBC_DEBUG0__FBC_PERF_MUX0_MASK … #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT … #define FBC_DEBUG0__FBC_PERF_MUX1_MASK … #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT … #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK … #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT … #define FBC_DEBUG0__FBC_DEBUG0_MASK … #define FBC_DEBUG0__FBC_DEBUG0__SHIFT … #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK … #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT … #define FBC_DEBUG1__FBC_DEBUG1_MASK … #define FBC_DEBUG1__FBC_DEBUG1__SHIFT … #define FBC_DEBUG2__FBC_DEBUG2_MASK … #define FBC_DEBUG2__FBC_DEBUG2__SHIFT … #define FBC_IND_LUT0__FBC_IND_LUT0_MASK … #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT … #define FBC_IND_LUT1__FBC_IND_LUT1_MASK … #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT … #define FBC_IND_LUT2__FBC_IND_LUT2_MASK … #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT … #define FBC_IND_LUT3__FBC_IND_LUT3_MASK … #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT … #define FBC_IND_LUT4__FBC_IND_LUT4_MASK … #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT … #define FBC_IND_LUT5__FBC_IND_LUT5_MASK … #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT … #define FBC_IND_LUT6__FBC_IND_LUT6_MASK … #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT … #define FBC_IND_LUT7__FBC_IND_LUT7_MASK … #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT … #define FBC_IND_LUT8__FBC_IND_LUT8_MASK … #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT … #define FBC_IND_LUT9__FBC_IND_LUT9_MASK … #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT … #define FBC_IND_LUT10__FBC_IND_LUT10_MASK … #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT … #define FBC_IND_LUT11__FBC_IND_LUT11_MASK … #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT … #define FBC_IND_LUT12__FBC_IND_LUT12_MASK … #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT … #define FBC_IND_LUT13__FBC_IND_LUT13_MASK … #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT … #define FBC_IND_LUT14__FBC_IND_LUT14_MASK … #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT … #define FBC_IND_LUT15__FBC_IND_LUT15_MASK … #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT … #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK … #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT … #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK … #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT … #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK … #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT … #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK … #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT … #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK … #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK … #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK … #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK … #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK … #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK … #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT … #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK … #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK … #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT … #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK … #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT … #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK … #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT … #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK … #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT … #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK … #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT … #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK … #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT … #define FBC_MISC__FBC_STOP_ON_ERROR_MASK … #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT … #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK … #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT … #define FBC_MISC__FBC_ERROR_PIXEL_MASK … #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT … #define FBC_MISC__FBC_DIVIDE_X_MASK … #define FBC_MISC__FBC_DIVIDE_X__SHIFT … #define FBC_MISC__FBC_DIVIDE_Y_MASK … #define FBC_MISC__FBC_DIVIDE_Y__SHIFT … #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK … #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT … #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK … #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT … #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK … #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT … #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK … #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT … #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK … #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT … #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK … #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT … #define FBC_STATUS__FBC_ENABLE_STATUS_MASK … #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT … #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK … #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT … #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK … #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT … #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK … #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT … #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK … #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT … #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK … #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT … #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK … #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT … #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK … #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT … #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK … #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT … #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK … #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT … #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK … #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT … #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK … #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT … #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK … #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT … #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK … #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT … #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK … #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT … #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK … #define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT … #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK … #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT … #define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK … #define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT … #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK … #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT … #define FMT_CONTROL__FMT_SRC_SELECT_MASK … #define FMT_CONTROL__FMT_SRC_SELECT__SHIFT … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY_MASK … #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY__SHIFT … #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK … #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT … #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK … #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT … #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK … #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT … #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK … #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT … #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK … #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT … #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK … #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT … #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK … #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT … #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK … #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT … #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK … #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT … #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK … #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT … #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK … #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT … #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK … #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT … #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK … #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT … #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK … #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT … #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK … #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT … #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK … #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT … #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK … #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_EN_MASK … #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT … #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK … #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK … #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK … #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK … #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK … #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK … #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT … #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK … #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT … #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK … #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT … #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK … #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT … #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK … #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT … #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK … #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT … #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK … #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT … #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK … #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT … #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK … #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT … #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK … #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT … #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK … #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT … #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK … #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT … #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK … #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT … #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK … #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT … #define FMT_DEBUG0__FMT_DEBUG0_MASK … #define FMT_DEBUG0__FMT_DEBUG0__SHIFT … #define FMT_DEBUG1__FMT_DEBUG1_MASK … #define FMT_DEBUG1__FMT_DEBUG1__SHIFT … #define FMT_DEBUG2__FMT_DEBUG2_MASK … #define FMT_DEBUG2__FMT_DEBUG2__SHIFT … #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK … #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT … #define LB_DATA_FORMAT__PIXEL_DEPTH_MASK … #define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT … #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK … #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT … #define LB_DATA_FORMAT__INTERLEAVE_EN_MASK … #define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT … #define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK … #define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT … #define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK … #define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT … #define LB_DATA_FORMAT__PREFETCH_MASK … #define LB_DATA_FORMAT__PREFETCH__SHIFT … #define LB_DATA_FORMAT__REQUEST_MODE_MASK … #define LB_DATA_FORMAT__REQUEST_MODE__SHIFT … #define LB_DATA_FORMAT__ALPHA_EN_MASK … #define LB_DATA_FORMAT__ALPHA_EN__SHIFT … #define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK … #define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT … #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK … #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT … #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK … #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT … #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK … #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT … #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK … #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT … #define LB_VLINE_START_END__VLINE_START_MASK … #define LB_VLINE_START_END__VLINE_START__SHIFT … #define LB_VLINE_START_END__VLINE_END_MASK … #define LB_VLINE_START_END__VLINE_END__SHIFT … #define LB_VLINE_START_END__VLINE_INV_MASK … #define LB_VLINE_START_END__VLINE_INV__SHIFT … #define LB_VLINE2_START_END__VLINE2_START_MASK … #define LB_VLINE2_START_END__VLINE2_START__SHIFT … #define LB_VLINE2_START_END__VLINE2_END_MASK … #define LB_VLINE2_START_END__VLINE2_END__SHIFT … #define LB_VLINE2_START_END__VLINE2_INV_MASK … #define LB_VLINE2_START_END__VLINE2_INV__SHIFT … #define LB_V_COUNTER__V_COUNTER_MASK … #define LB_V_COUNTER__V_COUNTER__SHIFT … #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK … #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT … #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK … #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT … #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK … #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT … #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK … #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT … #define LB_VLINE_STATUS__VLINE_OCCURRED_MASK … #define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT … #define LB_VLINE_STATUS__VLINE_ACK_MASK … #define LB_VLINE_STATUS__VLINE_ACK__SHIFT … #define LB_VLINE_STATUS__VLINE_STAT_MASK … #define LB_VLINE_STATUS__VLINE_STAT__SHIFT … #define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK … #define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT … #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK … #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT … #define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK … #define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT … #define LB_VLINE2_STATUS__VLINE2_ACK_MASK … #define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT … #define LB_VLINE2_STATUS__VLINE2_STAT_MASK … #define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT … #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK … #define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT … #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK … #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT … #define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK … #define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT … #define LB_VBLANK_STATUS__VBLANK_ACK_MASK … #define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT … #define LB_VBLANK_STATUS__VBLANK_STAT_MASK … #define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT … #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK … #define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT … #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK … #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK … #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT … #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK … #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT … #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK … #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT … #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK … #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT … #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK … #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT … #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK … #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT … #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK … #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT … #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK … #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT … #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK … #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT … #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK … #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT … #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK … #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT … #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK … #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT … #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK … #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT … #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK … #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT … #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK … #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT … #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK … #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT … #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK … #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT … #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK … #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT … #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK … #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT … #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK … #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT … #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK … #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK … #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT … #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK … #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT … #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK … #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK … #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK … #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT … #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK … #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT … #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK … #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT … #define LB_DEBUG__LB_DEBUG_MASK … #define LB_DEBUG__LB_DEBUG__SHIFT … #define LB_DEBUG2__LB_DEBUG2_MASK … #define LB_DEBUG2__LB_DEBUG2__SHIFT … #define LB_DEBUG3__LB_DEBUG3_MASK … #define LB_DEBUG3__LB_DEBUG3__SHIFT … #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK … #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT … #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK … #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT … #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK … #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT … #define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK … #define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT … #define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK … #define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT … #define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK … #define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT … #define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK … #define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT … #define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK … #define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT … #define LBV_DATA_FORMAT__DITHER_EN_MASK … #define LBV_DATA_FORMAT__DITHER_EN__SHIFT … #define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK … #define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT … #define LBV_DATA_FORMAT__PREFETCH_MASK … #define LBV_DATA_FORMAT__PREFETCH__SHIFT … #define LBV_DATA_FORMAT__REQUEST_MODE_MASK … #define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT … #define LBV_DATA_FORMAT__ALPHA_EN_MASK … #define LBV_DATA_FORMAT__ALPHA_EN__SHIFT … #define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK … #define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT … #define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK … #define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT … #define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK … #define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT … #define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK … #define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT … #define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK … #define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT … #define LBV_VLINE_START_END__VLINE_START_MASK … #define LBV_VLINE_START_END__VLINE_START__SHIFT … #define LBV_VLINE_START_END__VLINE_END_MASK … #define LBV_VLINE_START_END__VLINE_END__SHIFT … #define LBV_VLINE_START_END__VLINE_INV_MASK … #define LBV_VLINE_START_END__VLINE_INV__SHIFT … #define LBV_VLINE2_START_END__VLINE2_START_MASK … #define LBV_VLINE2_START_END__VLINE2_START__SHIFT … #define LBV_VLINE2_START_END__VLINE2_END_MASK … #define LBV_VLINE2_START_END__VLINE2_END__SHIFT … #define LBV_VLINE2_START_END__VLINE2_INV_MASK … #define LBV_VLINE2_START_END__VLINE2_INV__SHIFT … #define LBV_V_COUNTER__V_COUNTER_MASK … #define LBV_V_COUNTER__V_COUNTER__SHIFT … #define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK … #define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT … #define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK … #define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT … #define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK … #define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT … #define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK … #define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT … #define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK … #define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT … #define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK … #define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT … #define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK … #define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT … #define LBV_VLINE_STATUS__VLINE_ACK_MASK … #define LBV_VLINE_STATUS__VLINE_ACK__SHIFT … #define LBV_VLINE_STATUS__VLINE_STAT_MASK … #define LBV_VLINE_STATUS__VLINE_STAT__SHIFT … #define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK … #define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT … #define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK … #define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT … #define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK … #define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT … #define LBV_VLINE2_STATUS__VLINE2_ACK_MASK … #define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT … #define LBV_VLINE2_STATUS__VLINE2_STAT_MASK … #define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT … #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK … #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT … #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK … #define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT … #define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK … #define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT … #define LBV_VBLANK_STATUS__VBLANK_ACK_MASK … #define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT … #define LBV_VBLANK_STATUS__VBLANK_STAT_MASK … #define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT … #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK … #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT … #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK … #define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK … #define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT … #define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK … #define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT … #define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK … #define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT … #define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK … #define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT … #define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK … #define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT … #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK … #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT … #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK … #define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT … #define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK … #define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT … #define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK … #define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT … #define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK … #define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT … #define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK … #define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT … #define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK … #define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT … #define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK … #define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT … #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK … #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT … #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK … #define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT … #define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK … #define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT … #define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK … #define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT … #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK … #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT … #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK … #define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT … #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK … #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT … #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK … #define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK … #define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT … #define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK … #define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT … #define LBV_DEBUG__LB_DEBUG_MASK … #define LBV_DEBUG__LB_DEBUG__SHIFT … #define LBV_DEBUG2__LB_DEBUG2_MASK … #define LBV_DEBUG2__LB_DEBUG2__SHIFT … #define LBV_DEBUG3__LB_DEBUG3_MASK … #define LBV_DEBUG3__LB_DEBUG3__SHIFT … #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK … #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT … #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK … #define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT … #define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK … #define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT … #define MVP_CONTROL1__MVP_EN_MASK … #define MVP_CONTROL1__MVP_EN__SHIFT … #define MVP_CONTROL1__MVP_MIXER_MODE_MASK … #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT … #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK … #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT … #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK … #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT … #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK … #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT … #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK … #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT … #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK … #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT … #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK … #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT … #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK … #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT … #define MVP_CONTROL1__MVP_30BPP_EN_MASK … #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT … #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK … #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT … #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK … #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT … #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK … #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT … #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK … #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT … #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK … #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT … #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK … #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT … #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK … #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT … #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK … #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT … #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK … #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT … #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK … #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT … #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK … #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT … #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK … #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT … #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK … #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT … #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK … #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT … #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK … #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT … #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK … #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT … #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK … #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT … #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK … #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT … #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK … #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK … #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT … #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK … #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT … #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK … #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT … #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK … #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT … #define MVP_CRC_CNTL__MVP_CRC_EN_MASK … #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT … #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK … #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT … #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK … #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT … #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK … #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT … #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK … #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT … #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK … #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT … #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK … #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT … #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK … #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT … #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK … #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT … #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK … #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT … #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK … #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT … #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK … #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT … #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK … #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT … #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK … #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK … #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT … #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK … #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT … #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK … #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT … #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK … #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT … #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK … #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT … #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK … #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT … #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK … #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT … #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK … #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT … #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK … #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT … #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK … #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT … #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK … #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT … #define MVP_DEBUG__MVP_DEBUG_BITS_MASK … #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT … #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK … #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT … #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK … #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT … #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK … #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT … #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK … #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT … #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK … #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT … #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK … #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT … #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK … #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT … #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK … #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT … #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK … #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT … #define MVP_DEBUG_13__IDED_START_READ_B_MASK … #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT … #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK … #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT … #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK … #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT … #define MVP_DEBUG_14__IDEE_READ_ADD_MASK … #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT … #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK … #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT … #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK … #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT … #define MVP_DEBUG_14__IDEE_START_READ_MASK … #define MVP_DEBUG_14__IDEE_START_READ__SHIFT … #define MVP_DEBUG_14__IDEE_START_READ_B_MASK … #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT … #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK … #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT … #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK … #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT … #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK … #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT … #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK … #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT … #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK … #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK … #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT … #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK … #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT … #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK … #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT … #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK … #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT … #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK … #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT … #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK … #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK … #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK … #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK … #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK … #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT … #define SCL_MODE__SCL_MODE_MASK … #define SCL_MODE__SCL_MODE__SHIFT … #define SCL_MODE__SCL_PSCL_EN_MASK … #define SCL_MODE__SCL_PSCL_EN__SHIFT … #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK … #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT … #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK … #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT … #define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK … #define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT … #define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK … #define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT … #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK … #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT … #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK … #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT … #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK … #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT … #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK … #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT … #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK … #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT … #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK … #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT … #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK … #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT … #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK … #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT … #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK … #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT … #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK … #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT … #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK … #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT … #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK … #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT … #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK … #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT … #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK … #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT … #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK … #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT … #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK … #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT … #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK … #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT … #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK … #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT … #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK … #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT … #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK … #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT … #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK … #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT … #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK … #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT … #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK … #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT … #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK … #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT … #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK … #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT … #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK … #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT … #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK … #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT … #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK … #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK … #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT … #define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK … #define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT … #define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK … #define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT … #define VIEWPORT_START__VIEWPORT_Y_START_MASK … #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT … #define VIEWPORT_START__VIEWPORT_X_START_MASK … #define VIEWPORT_START__VIEWPORT_X_START__SHIFT … #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK … #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT … #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK … #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT … #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK … #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT … #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK … #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT … #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK … #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT … #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK … #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT … #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK … #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT … #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK … #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT … #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK … #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT … #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK … #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT … #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK … #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT … #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK … #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT … #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK … #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT … #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK … #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT … #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK … #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT … #define SCL_DEBUG2__SCL_DEBUG2_MASK … #define SCL_DEBUG2__SCL_DEBUG2__SHIFT … #define SCL_DEBUG__SCL_DEBUG_MASK … #define SCL_DEBUG__SCL_DEBUG__SHIFT … #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK … #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT … #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK … #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT … #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK … #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK … #define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK … #define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT … #define SCLV_MODE__SCL_MODE_MASK … #define SCLV_MODE__SCL_MODE__SHIFT … #define SCLV_MODE__SCL_PSCL_EN_MASK … #define SCLV_MODE__SCL_PSCL_EN__SHIFT … #define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK … #define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT … #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK … #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT … #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK … #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT … #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK … #define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT … #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK … #define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT … #define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK … #define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT … #define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK … #define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT … #define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK … #define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT … #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK … #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT … #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK … #define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT … #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK … #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT … #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK … #define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT … #define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK … #define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT … #define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK … #define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT … #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK … #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT … #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK … #define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT … #define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK … #define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT … #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK … #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT … #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK … #define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT … #define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK … #define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT … #define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK … #define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT … #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK … #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT … #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK … #define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT … #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK … #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT … #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK … #define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT … #define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK … #define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT … #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK … #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT … #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK … #define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT … #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK … #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT … #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK … #define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT … #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK … #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT … #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK … #define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT … #define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK … #define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT … #define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK … #define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT … #define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK … #define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT … #define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK … #define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT … #define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK … #define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT … #define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK … #define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT … #define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK … #define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT … #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK … #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT … #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK … #define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT … #define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK … #define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT … #define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK … #define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT … #define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK … #define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT … #define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK … #define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT … #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK … #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT … #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK … #define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT … #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK … #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT … #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK … #define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT … #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK … #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT … #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK … #define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT … #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK … #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT … #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK … #define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT … #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK … #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT … #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK … #define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT … #define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK … #define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT … #define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK … #define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT … #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK … #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT … #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK … #define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT … #define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK … #define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT … #define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK … #define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT … #define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK … #define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT … #define SCLV_DEBUG2__SCL_DEBUG2_MASK … #define SCLV_DEBUG2__SCL_DEBUG2__SHIFT … #define SCLV_DEBUG__SCL_DEBUG_MASK … #define SCLV_DEBUG__SCL_DEBUG__SHIFT … #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK … #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT … #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK … #define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT … #define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK … #define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT … #define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK … #define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT … #define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK … #define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT … #define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK … #define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT … #define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK … #define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK … #define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT … #define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK … #define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT … #define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK … #define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT … #define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK … #define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT … #define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK … #define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT … #define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK … #define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT … #define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK … #define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT … #define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK … #define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT … #define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK … #define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT … #define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK … #define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT … #define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK … #define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT … #define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK … #define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT … #define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK … #define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT … #define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK … #define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT … #define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK … #define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT … #define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK … #define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT … #define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK … #define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT … #define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK … #define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT … #define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK … #define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT … #define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK … #define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT … #define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK … #define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT … #define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK … #define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT … #define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK … #define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT … #define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK … #define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT … #define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK … #define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT … #define PRESCALE_CONTROL__PRESCALE_MODE_MASK … #define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT … #define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK … #define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT … #define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK … #define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT … #define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK … #define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT … #define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK … #define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT … #define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK … #define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT … #define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK … #define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT … #define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK … #define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT … #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK … #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT … #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK … #define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT … #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK … #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT … #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK … #define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT … #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK … #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT … #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK … #define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT … #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK … #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT … #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK … #define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT … #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK … #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT … #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK … #define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT … #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK … #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT … #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK … #define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT … #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK … #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT … #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK … #define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT … #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK … #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT … #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK … #define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT … #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK … #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT … #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK … #define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT … #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK … #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT … #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK … #define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT … #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK … #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT … #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK … #define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT … #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK … #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT … #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK … #define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT … #define DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK … #define DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT … #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK … #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT … #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK … #define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT … #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK … #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT … #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK … #define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT … #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK … #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT … #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK … #define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT … #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK … #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT … #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK … #define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT … #define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK … #define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT … #define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK … #define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT … #define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK … #define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT … #define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK … #define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT … #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK … #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT … #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK … #define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT … #define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK … #define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT … #define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK … #define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT … #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK … #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT … #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK … #define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK … #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT … #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK … #define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT … #define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK … #define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT … #define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK … #define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT … #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK … #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT … #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK … #define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK … #define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT … #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK … #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT … #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK … #define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT … #define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK … #define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT … #define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK … #define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT … #define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK … #define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT … #define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK … #define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT … #define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK … #define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT … #define UNP_GRPH_CONTROL__GRPH_Z_MASK … #define UNP_GRPH_CONTROL__GRPH_Z__SHIFT … #define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK … #define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT … #define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK … #define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT … #define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK … #define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT … #define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK … #define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT … #define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK … #define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT … #define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK … #define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT … #define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK … #define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT … #define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK … #define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT … #define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK … #define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT … #define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK … #define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT … #define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK … #define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT … #define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK … #define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT … #define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK … #define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT … #define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK … #define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT … #define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK … #define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT … #define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK … #define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK … #define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK … #define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK … #define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK … #define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT … #define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK … #define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT … #define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK … #define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT … #define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK … #define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT … #define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK … #define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT … #define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK … #define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT … #define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK … #define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT … #define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK … #define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT … #define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK … #define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT … #define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK … #define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT … #define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK … #define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT … #define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK … #define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT … #define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK … #define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT … #define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK … #define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT … #define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK … #define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT … #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK … #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT … #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK … #define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT … #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK … #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT … #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK … #define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT … #define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK … #define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT … #define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK … #define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT … #define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK … #define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT … #define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK … #define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT … #define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK … #define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT … #define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK … #define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT … #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK … #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT … #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK … #define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK … #define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT … #define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK … #define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT … #define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK … #define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT … #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK … #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT … #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK … #define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT … #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK … #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT … #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK … #define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT … #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK … #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT … #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK … #define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK … #define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT … #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK … #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT … #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK … #define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT … #define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK … #define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT … #define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK … #define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT … #define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK … #define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT … #define UNP_CRC_MASK__UNP_CRC_MASK_MASK … #define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT … #define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK … #define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT … #define UNP_CRC_LAST__UNP_CRC_LAST_MASK … #define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT … #define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK … #define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT … #define UNP_HW_ROTATION__ROTATION_ANGLE_MASK … #define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT … #define UNP_HW_ROTATION__PIXEL_DROP_MASK … #define UNP_HW_ROTATION__PIXEL_DROP__SHIFT … #define UNP_HW_ROTATION__BUFFER_MODE_MASK … #define UNP_HW_ROTATION__BUFFER_MODE__SHIFT … #define UNP_DEBUG__UNP_DEBUG_MASK … #define UNP_DEBUG__UNP_DEBUG__SHIFT … #define UNP_DEBUG2__UNP_DEBUG2_MASK … #define UNP_DEBUG2__UNP_DEBUG2__SHIFT … #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK … #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT … #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK … #define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT … #define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK … #define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT … #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK … #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT … #define GENMO_WT__VGA_RAM_EN_MASK … #define GENMO_WT__VGA_RAM_EN__SHIFT … #define GENMO_WT__VGA_CKSEL_MASK … #define GENMO_WT__VGA_CKSEL__SHIFT … #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK … #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT … #define GENMO_WT__VGA_HSYNC_POL_MASK … #define GENMO_WT__VGA_HSYNC_POL__SHIFT … #define GENMO_WT__VGA_VSYNC_POL_MASK … #define GENMO_WT__VGA_VSYNC_POL__SHIFT … #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK … #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT … #define GENMO_RD__VGA_RAM_EN_MASK … #define GENMO_RD__VGA_RAM_EN__SHIFT … #define GENMO_RD__VGA_CKSEL_MASK … #define GENMO_RD__VGA_CKSEL__SHIFT … #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK … #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT … #define GENMO_RD__VGA_HSYNC_POL_MASK … #define GENMO_RD__VGA_HSYNC_POL__SHIFT … #define GENMO_RD__VGA_VSYNC_POL_MASK … #define GENMO_RD__VGA_VSYNC_POL__SHIFT … #define GENENB__BLK_IO_BASE_MASK … #define GENENB__BLK_IO_BASE__SHIFT … #define GENFC_WT__VSYNC_SEL_W_MASK … #define GENFC_WT__VSYNC_SEL_W__SHIFT … #define GENFC_RD__VSYNC_SEL_R_MASK … #define GENFC_RD__VSYNC_SEL_R__SHIFT … #define GENS0__SENSE_SWITCH_MASK … #define GENS0__SENSE_SWITCH__SHIFT … #define GENS0__CRT_INTR_MASK … #define GENS0__CRT_INTR__SHIFT … #define GENS1__NO_DISPLAY_MASK … #define GENS1__NO_DISPLAY__SHIFT … #define GENS1__VGA_VSTATUS_MASK … #define GENS1__VGA_VSTATUS__SHIFT … #define GENS1__PIXEL_READ_BACK_MASK … #define GENS1__PIXEL_READ_BACK__SHIFT … #define DAC_DATA__DAC_DATA_MASK … #define DAC_DATA__DAC_DATA__SHIFT … #define DAC_MASK__DAC_MASK_MASK … #define DAC_MASK__DAC_MASK__SHIFT … #define DAC_R_INDEX__DAC_R_INDEX_MASK … #define DAC_R_INDEX__DAC_R_INDEX__SHIFT … #define DAC_W_INDEX__DAC_W_INDEX_MASK … #define DAC_W_INDEX__DAC_W_INDEX__SHIFT … #define SEQ8_IDX__SEQ_IDX_MASK … #define SEQ8_IDX__SEQ_IDX__SHIFT … #define SEQ8_DATA__SEQ_DATA_MASK … #define SEQ8_DATA__SEQ_DATA__SHIFT … #define SEQ00__SEQ_RST0B_MASK … #define SEQ00__SEQ_RST0B__SHIFT … #define SEQ00__SEQ_RST1B_MASK … #define SEQ00__SEQ_RST1B__SHIFT … #define SEQ01__SEQ_DOT8_MASK … #define SEQ01__SEQ_DOT8__SHIFT … #define SEQ01__SEQ_SHIFT2_MASK … #define SEQ01__SEQ_SHIFT2__SHIFT … #define SEQ01__SEQ_PCLKBY2_MASK … #define SEQ01__SEQ_PCLKBY2__SHIFT … #define SEQ01__SEQ_SHIFT4_MASK … #define SEQ01__SEQ_SHIFT4__SHIFT … #define SEQ01__SEQ_MAXBW_MASK … #define SEQ01__SEQ_MAXBW__SHIFT … #define SEQ02__SEQ_MAP0_EN_MASK … #define SEQ02__SEQ_MAP0_EN__SHIFT … #define SEQ02__SEQ_MAP1_EN_MASK … #define SEQ02__SEQ_MAP1_EN__SHIFT … #define SEQ02__SEQ_MAP2_EN_MASK … #define SEQ02__SEQ_MAP2_EN__SHIFT … #define SEQ02__SEQ_MAP3_EN_MASK … #define SEQ02__SEQ_MAP3_EN__SHIFT … #define SEQ03__SEQ_FONT_B1_MASK … #define SEQ03__SEQ_FONT_B1__SHIFT … #define SEQ03__SEQ_FONT_B2_MASK … #define SEQ03__SEQ_FONT_B2__SHIFT … #define SEQ03__SEQ_FONT_A1_MASK … #define SEQ03__SEQ_FONT_A1__SHIFT … #define SEQ03__SEQ_FONT_A2_MASK … #define SEQ03__SEQ_FONT_A2__SHIFT … #define SEQ03__SEQ_FONT_B0_MASK … #define SEQ03__SEQ_FONT_B0__SHIFT … #define SEQ03__SEQ_FONT_A0_MASK … #define SEQ03__SEQ_FONT_A0__SHIFT … #define SEQ04__SEQ_256K_MASK … #define SEQ04__SEQ_256K__SHIFT … #define SEQ04__SEQ_ODDEVEN_MASK … #define SEQ04__SEQ_ODDEVEN__SHIFT … #define SEQ04__SEQ_CHAIN_MASK … #define SEQ04__SEQ_CHAIN__SHIFT … #define CRTC8_IDX__VCRTC_IDX_MASK … #define CRTC8_IDX__VCRTC_IDX__SHIFT … #define CRTC8_DATA__VCRTC_DATA_MASK … #define CRTC8_DATA__VCRTC_DATA__SHIFT … #define CRT00__H_TOTAL_MASK … #define CRT00__H_TOTAL__SHIFT … #define CRT01__H_DISP_END_MASK … #define CRT01__H_DISP_END__SHIFT … #define CRT02__H_BLANK_START_MASK … #define CRT02__H_BLANK_START__SHIFT … #define CRT03__H_BLANK_END_MASK … #define CRT03__H_BLANK_END__SHIFT … #define CRT03__H_DE_SKEW_MASK … #define CRT03__H_DE_SKEW__SHIFT … #define CRT03__CR10CR11_R_DIS_B_MASK … #define CRT03__CR10CR11_R_DIS_B__SHIFT … #define CRT04__H_SYNC_START_MASK … #define CRT04__H_SYNC_START__SHIFT … #define CRT05__H_SYNC_END_MASK … #define CRT05__H_SYNC_END__SHIFT … #define CRT05__H_SYNC_SKEW_MASK … #define CRT05__H_SYNC_SKEW__SHIFT … #define CRT05__H_BLANK_END_B5_MASK … #define CRT05__H_BLANK_END_B5__SHIFT … #define CRT06__V_TOTAL_MASK … #define CRT06__V_TOTAL__SHIFT … #define CRT07__V_TOTAL_B8_MASK … #define CRT07__V_TOTAL_B8__SHIFT … #define CRT07__V_DISP_END_B8_MASK … #define CRT07__V_DISP_END_B8__SHIFT … #define CRT07__V_SYNC_START_B8_MASK … #define CRT07__V_SYNC_START_B8__SHIFT … #define CRT07__V_BLANK_START_B8_MASK … #define CRT07__V_BLANK_START_B8__SHIFT … #define CRT07__LINE_CMP_B8_MASK … #define CRT07__LINE_CMP_B8__SHIFT … #define CRT07__V_TOTAL_B9_MASK … #define CRT07__V_TOTAL_B9__SHIFT … #define CRT07__V_DISP_END_B9_MASK … #define CRT07__V_DISP_END_B9__SHIFT … #define CRT07__V_SYNC_START_B9_MASK … #define CRT07__V_SYNC_START_B9__SHIFT … #define CRT08__ROW_SCAN_START_MASK … #define CRT08__ROW_SCAN_START__SHIFT … #define CRT08__BYTE_PAN_MASK … #define CRT08__BYTE_PAN__SHIFT … #define CRT09__MAX_ROW_SCAN_MASK … #define CRT09__MAX_ROW_SCAN__SHIFT … #define CRT09__V_BLANK_START_B9_MASK … #define CRT09__V_BLANK_START_B9__SHIFT … #define CRT09__LINE_CMP_B9_MASK … #define CRT09__LINE_CMP_B9__SHIFT … #define CRT09__DOUBLE_CHAR_HEIGHT_MASK … #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT … #define CRT0A__CURSOR_START_MASK … #define CRT0A__CURSOR_START__SHIFT … #define CRT0A__CURSOR_DISABLE_MASK … #define CRT0A__CURSOR_DISABLE__SHIFT … #define CRT0B__CURSOR_END_MASK … #define CRT0B__CURSOR_END__SHIFT … #define CRT0B__CURSOR_SKEW_MASK … #define CRT0B__CURSOR_SKEW__SHIFT … #define CRT0C__DISP_START_MASK … #define CRT0C__DISP_START__SHIFT … #define CRT0D__DISP_START_MASK … #define CRT0D__DISP_START__SHIFT … #define CRT0E__CURSOR_LOC_HI_MASK … #define CRT0E__CURSOR_LOC_HI__SHIFT … #define CRT0F__CURSOR_LOC_LO_MASK … #define CRT0F__CURSOR_LOC_LO__SHIFT … #define CRT10__V_SYNC_START_MASK … #define CRT10__V_SYNC_START__SHIFT … #define CRT11__V_SYNC_END_MASK … #define CRT11__V_SYNC_END__SHIFT … #define CRT11__V_INTR_CLR_MASK … #define CRT11__V_INTR_CLR__SHIFT … #define CRT11__V_INTR_EN_MASK … #define CRT11__V_INTR_EN__SHIFT … #define CRT11__SEL5_REFRESH_CYC_MASK … #define CRT11__SEL5_REFRESH_CYC__SHIFT … #define CRT11__C0T7_WR_ONLY_MASK … #define CRT11__C0T7_WR_ONLY__SHIFT … #define CRT12__V_DISP_END_MASK … #define CRT12__V_DISP_END__SHIFT … #define CRT13__DISP_PITCH_MASK … #define CRT13__DISP_PITCH__SHIFT … #define CRT14__UNDRLN_LOC_MASK … #define CRT14__UNDRLN_LOC__SHIFT … #define CRT14__ADDR_CNT_BY4_MASK … #define CRT14__ADDR_CNT_BY4__SHIFT … #define CRT14__DOUBLE_WORD_MASK … #define CRT14__DOUBLE_WORD__SHIFT … #define CRT15__V_BLANK_START_MASK … #define CRT15__V_BLANK_START__SHIFT … #define CRT16__V_BLANK_END_MASK … #define CRT16__V_BLANK_END__SHIFT … #define CRT17__RA0_AS_A13B_MASK … #define CRT17__RA0_AS_A13B__SHIFT … #define CRT17__RA1_AS_A14B_MASK … #define CRT17__RA1_AS_A14B__SHIFT … #define CRT17__VCOUNT_BY2_MASK … #define CRT17__VCOUNT_BY2__SHIFT … #define CRT17__ADDR_CNT_BY2_MASK … #define CRT17__ADDR_CNT_BY2__SHIFT … #define CRT17__WRAP_A15TOA0_MASK … #define CRT17__WRAP_A15TOA0__SHIFT … #define CRT17__BYTE_MODE_MASK … #define CRT17__BYTE_MODE__SHIFT … #define CRT17__CRTC_SYNC_EN_MASK … #define CRT17__CRTC_SYNC_EN__SHIFT … #define CRT18__LINE_CMP_MASK … #define CRT18__LINE_CMP__SHIFT … #define CRT1E__GRPH_DEC_RD1_MASK … #define CRT1E__GRPH_DEC_RD1__SHIFT … #define CRT1F__GRPH_DEC_RD0_MASK … #define CRT1F__GRPH_DEC_RD0__SHIFT … #define CRT22__GRPH_LATCH_DATA_MASK … #define CRT22__GRPH_LATCH_DATA__SHIFT … #define GRPH8_IDX__GRPH_IDX_MASK … #define GRPH8_IDX__GRPH_IDX__SHIFT … #define GRPH8_DATA__GRPH_DATA_MASK … #define GRPH8_DATA__GRPH_DATA__SHIFT … #define GRA00__GRPH_SET_RESET0_MASK … #define GRA00__GRPH_SET_RESET0__SHIFT … #define GRA00__GRPH_SET_RESET1_MASK … #define GRA00__GRPH_SET_RESET1__SHIFT … #define GRA00__GRPH_SET_RESET2_MASK … #define GRA00__GRPH_SET_RESET2__SHIFT … #define GRA00__GRPH_SET_RESET3_MASK … #define GRA00__GRPH_SET_RESET3__SHIFT … #define GRA01__GRPH_SET_RESET_ENA0_MASK … #define GRA01__GRPH_SET_RESET_ENA0__SHIFT … #define GRA01__GRPH_SET_RESET_ENA1_MASK … #define GRA01__GRPH_SET_RESET_ENA1__SHIFT … #define GRA01__GRPH_SET_RESET_ENA2_MASK … #define GRA01__GRPH_SET_RESET_ENA2__SHIFT … #define GRA01__GRPH_SET_RESET_ENA3_MASK … #define GRA01__GRPH_SET_RESET_ENA3__SHIFT … #define GRA02__GRPH_CCOMP_MASK … #define GRA02__GRPH_CCOMP__SHIFT … #define GRA03__GRPH_ROTATE_MASK … #define GRA03__GRPH_ROTATE__SHIFT … #define GRA03__GRPH_FN_SEL_MASK … #define GRA03__GRPH_FN_SEL__SHIFT … #define GRA04__GRPH_RMAP_MASK … #define GRA04__GRPH_RMAP__SHIFT … #define GRA05__GRPH_WRITE_MODE_MASK … #define GRA05__GRPH_WRITE_MODE__SHIFT … #define GRA05__GRPH_READ1_MASK … #define GRA05__GRPH_READ1__SHIFT … #define GRA05__CGA_ODDEVEN_MASK … #define GRA05__CGA_ODDEVEN__SHIFT … #define GRA05__GRPH_OES_MASK … #define GRA05__GRPH_OES__SHIFT … #define GRA05__GRPH_PACK_MASK … #define GRA05__GRPH_PACK__SHIFT … #define GRA06__GRPH_GRAPHICS_MASK … #define GRA06__GRPH_GRAPHICS__SHIFT … #define GRA06__GRPH_ODDEVEN_MASK … #define GRA06__GRPH_ODDEVEN__SHIFT … #define GRA06__GRPH_ADRSEL_MASK … #define GRA06__GRPH_ADRSEL__SHIFT … #define GRA07__GRPH_XCARE0_MASK … #define GRA07__GRPH_XCARE0__SHIFT … #define GRA07__GRPH_XCARE1_MASK … #define GRA07__GRPH_XCARE1__SHIFT … #define GRA07__GRPH_XCARE2_MASK … #define GRA07__GRPH_XCARE2__SHIFT … #define GRA07__GRPH_XCARE3_MASK … #define GRA07__GRPH_XCARE3__SHIFT … #define GRA08__GRPH_BMSK_MASK … #define GRA08__GRPH_BMSK__SHIFT … #define ATTRX__ATTR_IDX_MASK … #define ATTRX__ATTR_IDX__SHIFT … #define ATTRX__ATTR_PAL_RW_ENB_MASK … #define ATTRX__ATTR_PAL_RW_ENB__SHIFT … #define ATTRDW__ATTR_DATA_MASK … #define ATTRDW__ATTR_DATA__SHIFT … #define ATTRDR__ATTR_DATA_MASK … #define ATTRDR__ATTR_DATA__SHIFT … #define ATTR00__ATTR_PAL_MASK … #define ATTR00__ATTR_PAL__SHIFT … #define ATTR01__ATTR_PAL_MASK … #define ATTR01__ATTR_PAL__SHIFT … #define ATTR02__ATTR_PAL_MASK … #define ATTR02__ATTR_PAL__SHIFT … #define ATTR03__ATTR_PAL_MASK … #define ATTR03__ATTR_PAL__SHIFT … #define ATTR04__ATTR_PAL_MASK … #define ATTR04__ATTR_PAL__SHIFT … #define ATTR05__ATTR_PAL_MASK … #define ATTR05__ATTR_PAL__SHIFT … #define ATTR06__ATTR_PAL_MASK … #define ATTR06__ATTR_PAL__SHIFT … #define ATTR07__ATTR_PAL_MASK … #define ATTR07__ATTR_PAL__SHIFT … #define ATTR08__ATTR_PAL_MASK … #define ATTR08__ATTR_PAL__SHIFT … #define ATTR09__ATTR_PAL_MASK … #define ATTR09__ATTR_PAL__SHIFT … #define ATTR0A__ATTR_PAL_MASK … #define ATTR0A__ATTR_PAL__SHIFT … #define ATTR0B__ATTR_PAL_MASK … #define ATTR0B__ATTR_PAL__SHIFT … #define ATTR0C__ATTR_PAL_MASK … #define ATTR0C__ATTR_PAL__SHIFT … #define ATTR0D__ATTR_PAL_MASK … #define ATTR0D__ATTR_PAL__SHIFT … #define ATTR0E__ATTR_PAL_MASK … #define ATTR0E__ATTR_PAL__SHIFT … #define ATTR0F__ATTR_PAL_MASK … #define ATTR0F__ATTR_PAL__SHIFT … #define ATTR10__ATTR_GRPH_MODE_MASK … #define ATTR10__ATTR_GRPH_MODE__SHIFT … #define ATTR10__ATTR_MONO_EN_MASK … #define ATTR10__ATTR_MONO_EN__SHIFT … #define ATTR10__ATTR_LGRPH_EN_MASK … #define ATTR10__ATTR_LGRPH_EN__SHIFT … #define ATTR10__ATTR_BLINK_EN_MASK … #define ATTR10__ATTR_BLINK_EN__SHIFT … #define ATTR10__ATTR_PANTOPONLY_MASK … #define ATTR10__ATTR_PANTOPONLY__SHIFT … #define ATTR10__ATTR_PCLKBY2_MASK … #define ATTR10__ATTR_PCLKBY2__SHIFT … #define ATTR10__ATTR_CSEL_EN_MASK … #define ATTR10__ATTR_CSEL_EN__SHIFT … #define ATTR11__ATTR_OVSC_MASK … #define ATTR11__ATTR_OVSC__SHIFT … #define ATTR12__ATTR_MAP_EN_MASK … #define ATTR12__ATTR_MAP_EN__SHIFT … #define ATTR12__ATTR_VSMUX_MASK … #define ATTR12__ATTR_VSMUX__SHIFT … #define ATTR13__ATTR_PPAN_MASK … #define ATTR13__ATTR_PPAN__SHIFT … #define ATTR14__ATTR_CSEL1_MASK … #define ATTR14__ATTR_CSEL1__SHIFT … #define ATTR14__ATTR_CSEL2_MASK … #define ATTR14__ATTR_CSEL2__SHIFT … #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK … #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT … #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK … #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT … #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK … #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT … #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK … #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT … #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK … #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT … #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK … #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT … #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK … #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT … #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK … #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT … #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK … #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK … #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK … #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT … #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK … #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT … #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK … #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT … #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK … #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT … #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK … #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT … #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK … #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT … #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK … #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT … #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK … #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT … #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK … #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT … #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK … #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT … #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK … #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT … #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK … #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT … #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK … #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT … #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK … #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT … #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK … #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT … #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT … #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK … #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT … #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK … #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT … #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK … #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT … #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK … #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT … #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK … #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT … #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK … #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT … #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK … #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT … #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK … #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT … #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK … #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT … #define D1VGA_CONTROL__D1VGA_ROTATE_MASK … #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT … #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK … #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT … #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK … #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT … #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK … #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT … #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK … #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT … #define D2VGA_CONTROL__D2VGA_ROTATE_MASK … #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT … #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK … #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT … #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK … #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT … #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK … #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT … #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK … #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT … #define D3VGA_CONTROL__D3VGA_ROTATE_MASK … #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT … #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK … #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT … #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK … #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT … #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK … #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT … #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK … #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT … #define D4VGA_CONTROL__D4VGA_ROTATE_MASK … #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT … #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK … #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT … #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK … #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT … #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK … #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT … #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK … #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT … #define D5VGA_CONTROL__D5VGA_ROTATE_MASK … #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT … #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK … #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT … #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK … #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT … #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK … #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT … #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK … #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT … #define D6VGA_CONTROL__D6VGA_ROTATE_MASK … #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT … #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK … #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT … #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK … #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT … #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK … #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT … #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK … #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT … #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK … #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT … #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK … #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT … #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK … #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT … #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK … #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT … #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK … #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT … #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK … #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT … #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK … #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT … #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK … #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT … #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK … #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT … #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK … #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT … #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK … #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT … #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK … #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT … #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK … #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT … #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK … #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT … #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK … #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT … #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK … #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT … #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK … #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT … #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK … #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT … #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK … #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT … #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK … #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT … #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK … #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT … #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK … #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT … #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK … #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT … #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK … #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT … #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK … #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT … #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK … #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK … #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT … #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK … #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT … #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK … #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT … #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK … #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT … #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK … #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT … #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK … #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT … #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK … #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT … #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK … #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT … #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK … #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT … #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK … #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT … #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK … #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK … #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK … #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT … #define PLL_REF_DIV__PLL_REF_DIV_MASK … #define PLL_REF_DIV__PLL_REF_DIV__SHIFT … #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK … #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT … #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK … #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT … #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK … #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT … #define PLL_FB_DIV__PLL_FB_DIV_MASK … #define PLL_FB_DIV__PLL_FB_DIV__SHIFT … #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK … #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT … #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK … #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT … #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK … #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT … #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK … #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT … #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK … #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT … #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK … #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT … #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK … #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT … #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK … #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT … #define PLL_SS_CNTL__PLL_SS_EN_MASK … #define PLL_SS_CNTL__PLL_SS_EN__SHIFT … #define PLL_SS_CNTL__PLL_SS_MODE_MASK … #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT … #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK … #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT … #define PLL_DS_CNTL__PLL_DS_FRAC_MASK … #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT … #define PLL_DS_CNTL__PLL_DS_ORDER_MASK … #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT … #define PLL_DS_CNTL__PLL_DS_MODE_MASK … #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT … #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK … #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK … #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK … #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK … #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK … #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK … #define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK … #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT … #define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK … #define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT … #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK … #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT … #define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK … #define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT … #define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK … #define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT … #define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK … #define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT … #define PLL_CNTL__PLL_RESET_MASK … #define PLL_CNTL__PLL_RESET__SHIFT … #define PLL_CNTL__PLL_POWER_DOWN_MASK … #define PLL_CNTL__PLL_POWER_DOWN__SHIFT … #define PLL_CNTL__PLL_BYPASS_CAL_MASK … #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT … #define PLL_CNTL__PLL_POST_DIV_SRC_MASK … #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT … #define PLL_CNTL__PLL_VCOREF_MASK … #define PLL_CNTL__PLL_VCOREF__SHIFT … #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK … #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT … #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK … #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT … #define PLL_CNTL__PLL_CALREF_MASK … #define PLL_CNTL__PLL_CALREF__SHIFT … #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK … #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT … #define PLL_CNTL__PLL_REFCLK_SEL_MASK … #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT … #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK … #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT … #define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK … #define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT … #define PLL_CNTL__PLL_REF_DIV_SRC_MASK … #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT … #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK … #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT … #define PLL_CNTL__PLL_CALIB_DONE_MASK … #define PLL_CNTL__PLL_CALIB_DONE__SHIFT … #define PLL_CNTL__PLL_LOCKED_MASK … #define PLL_CNTL__PLL_LOCKED__SHIFT … #define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK … #define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT … #define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK … #define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT … #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK … #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT … #define PLL_CNTL__PLL_DIG_SPARE_MASK … #define PLL_CNTL__PLL_DIG_SPARE__SHIFT … #define PLL_ANALOG__PLL_CAL_MODE_MASK … #define PLL_ANALOG__PLL_CAL_MODE__SHIFT … #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK … #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT … #define PLL_ANALOG__PLL_CP_MASK … #define PLL_ANALOG__PLL_CP__SHIFT … #define PLL_ANALOG__PLL_LF_MODE_MASK … #define PLL_ANALOG__PLL_LF_MODE__SHIFT … #define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK … #define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT … #define PLL_ANALOG__PLL_IBIAS_MASK … #define PLL_ANALOG__PLL_IBIAS__SHIFT … #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK … #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT … #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK … #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT … #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK … #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT … #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK … #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK … #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK … #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT … #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK … #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT … #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK … #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT … #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK … #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT … #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK … #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT … #define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK … #define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT … #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK … #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT … #define PLL_XOR_LOCK__PLL_SPARE_MASK … #define PLL_XOR_LOCK__PLL_SPARE__SHIFT … #define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK … #define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK … #define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT … #define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK … #define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT … #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK … #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT … #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK … #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT … #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK … #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT … #define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK … #define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT … #define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK … #define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT … #define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK … #define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT … #define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK … #define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT … #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK … #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT … #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK … #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT … #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK … #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK … #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK … #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK … #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK … #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK … #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK … #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT … #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK … #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT … #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK … #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT … #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK … #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT … #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK … #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT … #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK … #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT … #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK … #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT … #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK … #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT … #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK … #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT … #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK … #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT … #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK … #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT … #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK … #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT … #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK … #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT … #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK … #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT … #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK … #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT … #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK … #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT … #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK … #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT … #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK … #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK … #define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT … #define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK … #define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT … #define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK … #define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT … #define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK … #define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK … #define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT … #define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK … #define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT … #define PPLL_SPARE0__PLL_SPARE0_MASK … #define PPLL_SPARE0__PLL_SPARE0__SHIFT … #define PPLL_SPARE1__PLL_SPARE1_MASK … #define PPLL_SPARE1__PLL_SPARE1__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK … #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT … #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK … #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT … #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK … #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK … #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK … #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT … #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK … #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT … #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK … #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT … #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK … #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT … #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK … #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT … #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK … #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK … #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK … #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK … #define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK … #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK … #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT … #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK … #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK … #define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT … #define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK … #define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK … #define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK … #define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK … #define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK … #define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK … #define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK … #define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK … #define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT … #define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK … #define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK … #define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT … #define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK … #define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT … #define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK … #define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK … #define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK … #define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT … #define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK … #define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT … #define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK … #define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT … #define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK … #define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT … #define UNIPHY_TMDP_REG4__RESERVED_MASK … #define UNIPHY_TMDP_REG4__RESERVED__SHIFT … #define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK … #define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT … #define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK … #define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT … #define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK … #define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT … #define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK … #define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT … #define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK … #define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT … #define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK … #define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT … #define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK … #define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT … #define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK … #define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT … #define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK … #define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT … #define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK … #define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT … #define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK … #define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT … #define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK … #define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT … #define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK … #define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT … #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK … #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT … #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK … #define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT … #define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK … #define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT … #define UNIPHY_DEBUG__DEBUG0_MASK … #define UNIPHY_DEBUG__DEBUG0__SHIFT … #define UNIPHY_DEBUG__DEBUG1_MASK … #define UNIPHY_DEBUG__DEBUG1__SHIFT … #define UNIPHY_DEBUG__DBG_SEL_MASK … #define UNIPHY_DEBUG__DBG_SEL__SHIFT … #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK … #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT … #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK … #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT … #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK … #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT … #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK … #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT … #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK … #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT … #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK … #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT … #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK … #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT … #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK … #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT … #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK … #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT … #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK … #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK … #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK … #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK … #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK … #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT … #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK … #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT … #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK … #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT … #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK … #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT … #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK … #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT … #define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK … #define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT … #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK … #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT … #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK … #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT … #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK … #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT … #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK … #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK … #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK … #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT … #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK … #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT … #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK … #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK … #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK … #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT … #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK … #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT … #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK … #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT … #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK … #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT … #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK … #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT … #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK … #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK … #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK … #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT … #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK … #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT … #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK … #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT … #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK … #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT … #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK … #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT … #define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK … #define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT … #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK … #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT … #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK … #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT … #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK … #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT … #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK … #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT … #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK … #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT … #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK … #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT … #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK … #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT … #define MINOR_VERSION__MINOR_VERSION_MASK … #define MINOR_VERSION__MINOR_VERSION__SHIFT … #define MAJOR_VERSION__MAJOR_VERSION_MASK … #define MAJOR_VERSION__MAJOR_VERSION__SHIFT … #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK … #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT … #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK … #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT … #define GLOBAL_CONTROL__CONTROLLER_RESET_MASK … #define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT … #define GLOBAL_CONTROL__FLUSH_CONTROL_MASK … #define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT … #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK … #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT … #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK … #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT … #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK … #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT … #define GLOBAL_STATUS__FLUSH_STATUS_MASK … #define GLOBAL_STATUS__FLUSH_STATUS__SHIFT … #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK … #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT … #define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK … #define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT … #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK … #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT … #define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT … #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK … #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT … #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK … #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT … #define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK … #define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT … #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK … #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT … #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK … #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT … #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK … #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT … #define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK … #define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT … #define CORB_READ_POINTER__CORB_READ_POINTER_MASK … #define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT … #define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK … #define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT … #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT … #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK … #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT … #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK … #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT … #define CORB_SIZE__CORB_SIZE_MASK … #define CORB_SIZE__CORB_SIZE__SHIFT … #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK … #define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT … #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK … #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT … #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK … #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT … #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK … #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT … #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK … #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT … #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK … #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT … #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK … #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT … #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK … #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT … #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK … #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT … #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK … #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT … #define RIRB_STATUS__RESPONSE_INTERRUPT_MASK … #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT … #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK … #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT … #define RIRB_SIZE__RIRB_SIZE_MASK … #define RIRB_SIZE__RIRB_SIZE__SHIFT … #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK … #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK … #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT … #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK … #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT … #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK … #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT … #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK … #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK … #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT … #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK … #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT … #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK … #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK … #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK … #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK … #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK … #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT … #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK … #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT … #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK … #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK … #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK … #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK … #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK … #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT … #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK … #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT … #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK … #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT … #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK … #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT … #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK … #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT … #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT … #define SINK_DESCRIPTION0__DESCRIPTION_MASK … #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION1__DESCRIPTION_MASK … #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION2__DESCRIPTION_MASK … #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION3__DESCRIPTION_MASK … #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION4__DESCRIPTION_MASK … #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION5__DESCRIPTION_MASK … #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION6__DESCRIPTION_MASK … #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION7__DESCRIPTION_MASK … #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION8__DESCRIPTION_MASK … #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION9__DESCRIPTION_MASK … #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION10__DESCRIPTION_MASK … #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION11__DESCRIPTION_MASK … #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION12__DESCRIPTION_MASK … #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION13__DESCRIPTION_MASK … #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION14__DESCRIPTION_MASK … #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION15__DESCRIPTION_MASK … #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION16__DESCRIPTION_MASK … #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT … #define SINK_DESCRIPTION17__DESCRIPTION_MASK … #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK … #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT … #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK … #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT … #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT … #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK … #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT … #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK … #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT … #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK … #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT … #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK … #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT … #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK … #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT … #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK … #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT … #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK … #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT … #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK … #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT … #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK … #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT … #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK … #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT … #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK … #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT … #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK … #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT … #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK … #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT … #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK … #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT … #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK … #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT … #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK … #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT … #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK … #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT … #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK … #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT … #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK … #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT … #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK … #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT … #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK … #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT … #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK … #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT … #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK … #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT … #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK … #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT … #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK … #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT … #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK … #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT … #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK … #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK … #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT … #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK … #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT … #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK … #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT … #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK … #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK … #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK … #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT … #define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK … #define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK … #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK … #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK … #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK … #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT … #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK … #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK … #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK … #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK … #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK … #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK … #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK … #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT … #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK … #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK … #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK … #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK … #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK … #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT … #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK … #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK … #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK … #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK … #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK … #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK … #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK … #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK … #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT … #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK … #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT … #define AZALIA_CRC0_CONTROL0__CRC_EN_MASK … #define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT … #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK … #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT … #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK … #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT … #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK … #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT … #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK … #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT … #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK … #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT … #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK … #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT … #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT … #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … #define AZALIA_CRC0_RESULT__CRC_RESULT_MASK … #define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT … #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK … #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT … #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK … #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT … #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK … #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT … #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK … #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT … #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK … #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT … #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK … #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT … #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK … #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT … #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK … #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT … #define AZALIA_CRC1_CONTROL0__CRC_EN_MASK … #define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT … #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK … #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT … #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK … #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT … #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK … #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT … #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK … #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT … #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK … #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT … #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK … #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT … #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK … #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT … #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK … #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … #define AZALIA_CRC1_RESULT__CRC_RESULT_MASK … #define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT … #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK … #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT … #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK … #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT … #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK … #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT … #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK … #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT … #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK … #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT … #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK … #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT … #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK … #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT … #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK … #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT … #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK … #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT … #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK … #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT … #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK … #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT … #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK … #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT … #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK … #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT … #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK … #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT … #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK … #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT … #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK … #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT … #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK … #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT … #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK … #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT … #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK … #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT … #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK … #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT … #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK … #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT … #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK … #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT … #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK … #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT … #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK … #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK … #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK … #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK … #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK … #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK … #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT … #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK … #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT … #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT … #define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK … #define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK … #define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK … #define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK … #define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK … #define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT … #define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK … #define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK … #define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT … #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK … #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK … #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK … #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK … #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT … #define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK … #define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT … #define BLND_CONTROL__BLND_MODE_MASK … #define BLND_CONTROL__BLND_MODE__SHIFT … #define BLND_CONTROL__BLND_STEREO_TYPE_MASK … #define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT … #define BLND_CONTROL__BLND_STEREO_POLARITY_MASK … #define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT … #define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK … #define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT … #define BLND_CONTROL__BLND_ALPHA_MODE_MASK … #define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT … #define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK … #define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT … #define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK … #define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT … #define SM_CONTROL2__SM_MODE_MASK … #define SM_CONTROL2__SM_MODE__SHIFT … #define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK … #define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT … #define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK … #define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT … #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK … #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT … #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK … #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT … #define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK … #define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT … #define BLND_CONTROL2__PTI_ENABLE_MASK … #define BLND_CONTROL2__PTI_ENABLE__SHIFT … #define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK … #define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT … #define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK … #define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT … #define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK … #define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT … #define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK … #define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT … #define BLND_UPDATE__BLND_UPDATE_PENDING_MASK … #define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT … #define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK … #define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT … #define BLND_UPDATE__BLND_UPDATE_LOCK_MASK … #define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK … #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK … #define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT … #define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK … #define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT … #define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK … #define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT … #define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK … #define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT … #define BLND_DEBUG__BLND_DEBUG_MASK … #define BLND_DEBUG__BLND_DEBUG__SHIFT … #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK … #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT … #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK … #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT … #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK … #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT … #define WB_ENABLE__WB_ENABLE_MASK … #define WB_ENABLE__WB_ENABLE__SHIFT … #define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT … #define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT … #define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT … #define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS__SHIFT … #define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS__SHIFT … #define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS_MASK … #define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS__SHIFT … #define WB_EC_CONFIG__WB_LB_LS_DIS_MASK … #define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT … #define WB_EC_CONFIG__WB_LB_SD_DIS_MASK … #define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT … #define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK … #define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT … #define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK … #define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK … #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT … #define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK … #define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT … #define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK … #define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT … #define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK … #define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT … #define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK … #define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT … #define CNV_MODE__CNV_WINDOW_CROP_EN_MASK … #define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT … #define CNV_MODE__CNV_STEREO_TYPE_MASK … #define CNV_MODE__CNV_STEREO_TYPE__SHIFT … #define CNV_MODE__CNV_INTERLACED_MODE_MASK … #define CNV_MODE__CNV_INTERLACED_MODE__SHIFT … #define CNV_MODE__CNV_EYE_SELECTION_MASK … #define CNV_MODE__CNV_EYE_SELECTION__SHIFT … #define CNV_MODE__CNV_STEREO_POLARITY_MASK … #define CNV_MODE__CNV_STEREO_POLARITY__SHIFT … #define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK … #define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT … #define CNV_MODE__CNV_STEREO_SPLIT_MASK … #define CNV_MODE__CNV_STEREO_SPLIT__SHIFT … #define CNV_MODE__CNV_NEW_CONTENT_MASK … #define CNV_MODE__CNV_NEW_CONTENT__SHIFT … #define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK … #define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT … #define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK … #define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT … #define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK … #define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT … #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK … #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT … #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK … #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT … #define CNV_UPDATE__CNV_UPDATE_PENDING_MASK … #define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT … #define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK … #define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT … #define CNV_UPDATE__CNV_UPDATE_LOCK_MASK … #define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT … #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK … #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT … #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK … #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT … #define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK … #define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT … #define CNV_CSC_C11_C12__CNV_CSC_C11_MASK … #define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT … #define CNV_CSC_C11_C12__CNV_CSC_C12_MASK … #define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT … #define CNV_CSC_C13_C14__CNV_CSC_C13_MASK … #define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT … #define CNV_CSC_C13_C14__CNV_CSC_C14_MASK … #define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT … #define CNV_CSC_C21_C22__CNV_CSC_C21_MASK … #define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT … #define CNV_CSC_C21_C22__CNV_CSC_C22_MASK … #define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT … #define CNV_CSC_C23_C24__CNV_CSC_C23_MASK … #define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT … #define CNV_CSC_C23_C24__CNV_CSC_C24_MASK … #define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT … #define CNV_CSC_C31_C32__CNV_CSC_C31_MASK … #define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT … #define CNV_CSC_C31_C32__CNV_CSC_C32_MASK … #define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT … #define CNV_CSC_C33_C34__CNV_CSC_C33_MASK … #define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT … #define CNV_CSC_C33_C34__CNV_CSC_C34_MASK … #define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT … #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK … #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT … #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK … #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT … #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK … #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT … #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK … #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT … #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK … #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT … #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK … #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT … #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK … #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT … #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK … #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT … #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK … #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT … #define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK … #define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT … #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK … #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT … #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK … #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT … #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK … #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT … #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK … #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT … #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK … #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT … #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK … #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT … #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK … #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT … #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK … #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT … #define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK … #define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT … #define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK … #define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT … #define WB_DBG_MODE__WB_DBG_MODE_EN_MASK … #define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT … #define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK … #define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT … #define WB_DBG_MODE__WB_DBG_36MODE_MASK … #define WB_DBG_MODE__WB_DBG_36MODE__SHIFT … #define WB_DBG_MODE__WB_DBG_CMAP_MASK … #define WB_DBG_MODE__WB_DBG_CMAP__SHIFT … #define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK … #define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT … #define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK … #define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT … #define WB_HW_DEBUG__WB_HW_DEBUG_MASK … #define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT … #define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK … #define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT … #define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK … #define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT … #define WB_SOFT_RESET__WB_SOFT_RESET_MASK … #define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT … #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK … #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT … #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK … #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT … #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK … #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT … #define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK … #define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT … #define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK … #define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT … #define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK … #define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT … #define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK … #define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT … #define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK … #define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT … #define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK … #define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT … #define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK … #define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT … #define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK … #define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT … #define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK … #define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT … #define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK … #define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT … #define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK … #define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT … #define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK … #define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK … #define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT … #define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK … #define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT … #define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK … #define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT … #define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT … #define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK … #define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK … #define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT … #define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK … #define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT … #define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK … #define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK … #define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK … #define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK … #define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK … #define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK … #define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK … #define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK … #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT … #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK … #define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT … #define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK … #define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT … #define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK … #define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT … #define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK … #define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT … #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK … #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT … #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK … #define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT … #define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK … #define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT … #define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK … #define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT … #define DC_HPD_CONTROL__DC_HPD_EN_MASK … #define DC_HPD_CONTROL__DC_HPD_EN__SHIFT … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK … #define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT … #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK … #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT … #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK … #define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT … #define DCO_SCRATCH0__DCO_SCRATCH0_MASK … #define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT … #define DCO_SCRATCH1__DCO_SCRATCH1_MASK … #define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT … #define DCO_SCRATCH2__DCO_SCRATCH2_MASK … #define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT … #define DCO_SCRATCH3__DCO_SCRATCH3_MASK … #define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT … #define DCO_SCRATCH4__DCO_SCRATCH4_MASK … #define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT … #define DCO_SCRATCH5__DCO_SCRATCH5_MASK … #define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT … #define DCO_SCRATCH6__DCO_SCRATCH6_MASK … #define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT … #define DCO_SCRATCH7__DCO_SCRATCH7_MASK … #define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT … #define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK … #define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT … #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK … #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT … #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK … #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT … #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK … #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT … #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK … #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT … #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK … #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT … #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK … #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT … #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK … #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK … #define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT … #define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK … #define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT … #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK … #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK … #define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK … #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT … #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK … #define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT … #define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK … #define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT … #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK … #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT … #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK … #define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT … #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK … #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK … #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT … #define DPDBG_CNTL__DPDBG_ENABLE_MASK … #define DPDBG_CNTL__DPDBG_ENABLE__SHIFT … #define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK … #define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT … #define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK … #define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT … #define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK … #define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT … #define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK … #define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK … #define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT … #define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK … #define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT … #define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK … #define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT … #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK … #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK … #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK … #define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK … #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK … #define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK … #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK … #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK … #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT … #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK … #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT … #define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK … #define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT … #define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK … #define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT … #define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK … #define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT … #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK … #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT … #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK … #define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT … #define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK … #define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT … #define DC_I2C_CONTROL__DC_I2C_GO_MASK … #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT … #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK … #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT … #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK … #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT … #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK … #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT … #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK … #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT … #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK … #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT … #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK … #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK … #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK … #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK … #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK … #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK … #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK … #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK … #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK … #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT … #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK … #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK … #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT … #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK … #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK … #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK … #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK … #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK … #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK … #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK … #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK … #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK … #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK … #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK … #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK … #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK … #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK … #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT … #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK … #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT … #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK … #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT … #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK … #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT … #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK … #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT … #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK … #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT … #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK … #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT … #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK … #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT … #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK … #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT … #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK … #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT … #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK … #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT … #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK … #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT … #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK … #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT … #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK … #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT … #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK … #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT … #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK … #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT … #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK … #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT … #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK … #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT … #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK … #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT … #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK … #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT … #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK … #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT … #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK … #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT … #define DC_I2C_DATA__DC_I2C_DATA_MASK … #define DC_I2C_DATA__DC_I2C_DATA__SHIFT … #define DC_I2C_DATA__DC_I2C_INDEX_MASK … #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT … #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK … #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK … #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK … #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK … #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK … #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK … #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT … #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK … #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT … #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK … #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT … #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK … #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT … #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK … #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT … #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK … #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK … #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT … #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK … #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT … #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK … #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT … #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK … #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT … #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK … #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT … #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK … #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT … #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK … #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT … #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK … #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT … #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK … #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT … #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK … #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT … #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK … #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK … #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT … #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK … #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT … #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK … #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT … #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK … #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT … #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK … #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT … #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK … #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT … #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK … #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK … #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK … #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK … #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK … #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK … #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK … #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK … #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK … #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK … #define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT … #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK … #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT … #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK … #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT … #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK … #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT … #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK … #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT … #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK … #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT … #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK … #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT … #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK … #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK … #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT … #define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK … #define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT … #define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK … #define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT … #define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK … #define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT … #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK … #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT … #define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK … #define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT … #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK … #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK … #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT … #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK … #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT … #define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK … #define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT … #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK … #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT … #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK … #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT … #define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK … #define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK … #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT … #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK … #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT … #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK … #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT … #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK … #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK … #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK … #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK … #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK … #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT … #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK … #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT … #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK … #define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK … #define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT … #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK … #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT … #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK … #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT … #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK … #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT … #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK … #define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT … #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK … #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT … #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK … #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT … #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK … #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT … #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK … #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT … #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK … #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT … #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK … #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT … #define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK … #define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT … #define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK … #define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK … #define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT … #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK … #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT … #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK … #define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK … #define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK … #define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT … #define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK … #define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK … #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT … #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK … #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT … #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK … #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK … #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK … #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT … #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK … #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT … #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK … #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT … #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK … #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT … #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK … #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT … #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK … #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT … #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK … #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK … #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK … #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK … #define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT … #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK … #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT … #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK … #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK … #define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT … #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK … #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT … #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK … #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT … #endif /* DCE_10_0_SH_MASK_H */
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