/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "soc15.h" #include "soc15_common.h" #include "amdgpu_reg_state.h" #include "amdgpu_xcp.h" #include "gfx_v9_4_3.h" #include "gfxhub_v1_2.h" #include "sdma_v4_4_2.h" #define XCP_INST_MASK(num_inst, xcp_id) … #define AMDGPU_XCP_OPS_KFD … void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) { … } static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev) { … } static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, uint32_t inst_idx, struct amdgpu_ring *ring) { … } static void aqua_vanjaram_xcp_gpu_sched_update( struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int sel_xcp_id) { … } static int aqua_vanjaram_xcp_sched_list_update( struct amdgpu_device *adev) { … } static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev) { … } static int aqua_vanjaram_select_scheds( struct amdgpu_device *adev, u32 hw_ip, u32 hw_prio, struct amdgpu_fpriv *fpriv, unsigned int *num_scheds, struct drm_gpu_scheduler ***scheds) { … } static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev, enum amd_hw_ip_block_type block, int8_t inst) { … } static uint32_t aqua_vanjaram_logical_to_dev_mask(struct amdgpu_device *adev, enum amd_hw_ip_block_type block, uint32_t mask) { … } static void aqua_vanjaram_populate_ip_map(struct amdgpu_device *adev, enum amd_hw_ip_block_type ip_block, uint32_t inst_mask) { … } void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev) { … } /* Fixed pattern for smn addressing on different AIDs: * bit[34]: indicate cross AID access * bit[33:32]: indicate target AID id * AID id range is 0 ~ 3 as maximum AID number is 4. */ u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id) { … } static enum amdgpu_gfx_partition __aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) { … } static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) { … } static int __aqua_vanjaram_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) { … } static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, enum AMDGPU_XCP_IP_BLOCK ip_id, struct amdgpu_xcp_ip *ip) { … } static enum amdgpu_gfx_partition __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) { … } static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, enum amdgpu_gfx_partition mode) { … } static int __aqua_vanjaram_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags) { … } static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags) { … } static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, int mode, int *num_xcps) { … } static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev, int xcc_id, uint8_t *mem_id) { … } static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, struct amdgpu_xcp *xcp, uint8_t *mem_id) { … } static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, enum AMDGPU_XCP_IP_BLOCK ip_id, struct amdgpu_xcp_ip *ip) { … } struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = …; static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) { … } int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev) { … } static void aqua_read_smn(struct amdgpu_device *adev, struct amdgpu_smn_reg_data *regdata, uint64_t smn_addr) { … } struct aqua_reg_list { … }; #define DW_ADDR_INCR … static void aqua_read_smn_ext(struct amdgpu_device *adev, struct amdgpu_smn_reg_data *regdata, uint64_t smn_addr, int i) { … } #define smnreg_0x1A340218 … #define smnreg_0x1A3402E4 … #define smnreg_0x1A340294 … #define smreg_0x1A380088 … #define NUM_PCIE_SMN_REGS … static struct aqua_reg_list pcie_reg_addrs[] = …; static ssize_t aqua_vanjaram_read_pcie_state(struct amdgpu_device *adev, void *buf, size_t max_size) { … } #define smnreg_0x11A00050 … #define smnreg_0x11A00180 … #define smnreg_0x11A00070 … #define smnreg_0x11A00200 … #define smnreg_0x11A0020C … #define smnreg_0x11A00210 … #define smnreg_0x11A00108 … #define XGMI_LINK_REG(smnreg, l) … #define NUM_XGMI_SMN_REGS … static struct aqua_reg_list xgmi_reg_addrs[] = …; static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev, void *buf, size_t max_size) { … } #define smnreg_0x11C00070 … #define smnreg_0x11C00210 … static struct aqua_reg_list wafl_reg_addrs[] = …; #define WAFL_LINK_REG(smnreg, l) … #define NUM_WAFL_SMN_REGS … static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev, void *buf, size_t max_size) { … } #define smnreg_0x1B311060 … #define smnreg_0x1B411060 … #define smnreg_0x1B511060 … #define smnreg_0x1B611060 … #define smnreg_0x1C307120 … #define smnreg_0x1C317120 … #define smnreg_0x1C320830 … #define smnreg_0x1C380830 … #define smnreg_0x1C3D0830 … #define smnreg_0x1C420830 … #define smnreg_0x1C320100 … #define smnreg_0x1C380100 … #define smnreg_0x1C3D0100 … #define smnreg_0x1C420100 … #define smnreg_0x1B310500 … #define smnreg_0x1C300400 … #define USR_CAKE_INCR … #define USR_LINK_INCR … #define USR_CP_INCR … #define NUM_USR_SMN_REGS … struct aqua_reg_list usr_reg_addrs[] = …; #define NUM_USR1_SMN_REGS … struct aqua_reg_list usr1_reg_addrs[] = …; static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev, void *buf, size_t max_size, int reg_state) { … } ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, enum amdgpu_reg_state reg_state, void *buf, size_t max_size) { … }
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