/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_atombios.h" #include "nbio_v6_1.h" #include "nbio/nbio_6_1_default.h" #include "nbio/nbio_6_1_offset.h" #include "nbio/nbio_6_1_sh_mask.h" #include "nbio/nbio_6_1_smn.h" #include "vega10_enum.h" #include <uapi/linux/kfd_ioctl.h> #define smnPCIE_LC_CNTL … #define smnPCIE_LC_CNTL3 … #define smnPCIE_LC_CNTL6 … #define smnPCIE_LC_CNTL7 … #define smnNBIF_MGCG_CTRL_LCLK … #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK … #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK … #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK … #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL … #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 … #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP … #define smnPSWUSP0_PCIE_LC_CNTL2 … #define smnRCC_BIF_STRAP2 … #define smnRCC_BIF_STRAP3 … #define smnRCC_BIF_STRAP5 … #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK … #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK … #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK … #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT … #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT … #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT … static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev) { … } static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) { … } static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) { … } static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) { … } static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index, int doorbell_size) { … } static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { … } static void nbio_v6_1_ih_control(struct amdgpu_device *adev) { … } static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { … } static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) { … } static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) { … } static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) { … } static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) { … } const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = …; static void nbio_v6_1_init_registers(struct amdgpu_device *adev) { … } #ifdef CONFIG_PCIEASPM static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) { … } #endif static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) { … } #define MMIO_REG_HOLE_OFFSET … static void nbio_v6_1_set_reg_remap(struct amdgpu_device *adev) { … } const struct amdgpu_nbio_funcs nbio_v6_1_funcs = …;
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