/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "df_v3_6.h" #include "df/df_3_6_default.h" #include "df/df_3_6_offset.h" #include "df/df_3_6_sh_mask.h" #define DF_3_6_SMN_REG_INST_DIST … #define DF_3_6_INST_CNT … /* Defined in global_features.h as FTI_PERFMON_VISIBLE */ #define DF_V3_6_MAX_COUNTERS … /* get flags from df perfmon config */ #define DF_V3_6_GET_EVENT(x) … #define DF_V3_6_GET_INSTANCE(x) … #define DF_V3_6_GET_UNITMASK(x) … #define DF_V3_6_PERFMON_OVERFLOW … static u32 df_v3_6_channel_number[] = …; static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, uint32_t ficaa_val) { … } static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, uint32_t ficadl_val, uint32_t ficadh_val) { … } /* * df_v3_6_perfmon_rreg - read perfmon lo and hi * * required to be atomic. no mmio method provided so subsequent reads for lo * and hi require to preserve df finite state machine */ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, uint32_t lo_addr, uint32_t *lo_val, uint32_t hi_addr, uint32_t *hi_val) { … } /* * df_v3_6_perfmon_wreg - write to perfmon lo and hi * * required to be atomic. no mmio method provided so subsequent reads after * data writes cannot occur to preserve data fabrics finite state machine. */ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) { … } /* same as perfmon_wreg but return status on write value check */ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, uint32_t lo_addr, uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) { … } /* * retry arming counters every 100 usecs within 1 millisecond interval. * if retry fails after time out, return error. */ #define ARM_RETRY_USEC_TIMEOUT … #define ARM_RETRY_USEC_INTERVAL … static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev, uint32_t lo_addr, uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) { … } /* get the number of df counters available */ static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev, struct device_attribute *attr, char *buf) { … } /* device attr for available perfmon counters */ static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL); static void df_v3_6_query_hashes(struct amdgpu_device *adev) { … } /* init perfmons */ static void df_v3_6_sw_init(struct amdgpu_device *adev) { … } static void df_v3_6_sw_fini(struct amdgpu_device *adev) { … } static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev, bool enable) { … } static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) { … } static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev) { … } static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { … } /* get assigned df perfmon ctr as int */ static bool df_v3_6_pmc_has_counter(struct amdgpu_device *adev, uint64_t config, int counter_idx) { … } /* get address based on counter assignment */ static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_ctrl, uint32_t *lo_base_addr, uint32_t *hi_base_addr) { … } /* get read counter address */ static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr) { … } /* get control counter settings i.e. address and values to set */ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr, uint32_t *lo_val, uint32_t *hi_val, bool is_enable) { … } /* add df performance counters for read */ static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev, uint64_t config) { … } #define DEFERRED_ARM_MASK … static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev, uint64_t config, int counter_idx, bool is_deferred) { … } static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev, uint64_t config, int counter_idx) { … } /* release performance counter */ static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev, uint64_t config, int counter_idx) { … } static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev, uint64_t config, int counter_idx) { … } /* return available counter if is_add == 1 otherwise return error status. */ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_add) { … } static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_remove) { … } static void df_v3_6_pmc_get_count(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint64_t *count) { … } static bool df_v3_6_query_ras_poison_mode(struct amdgpu_device *adev) { … } const struct amdgpu_df_funcs df_v3_6_funcs = …;
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