/* * Copyright (C) 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _df_4_3_SH_MASK_HEADER #define _df_4_3_SH_MASK_HEADER //DF_CS_UMC_AON0_HardwareAssertMaskLow #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk0__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk1__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk2__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk3__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk4__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk5__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk6__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk7__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk8__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk9__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk10__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk11__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk12__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk13__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk15__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk16__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk17__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk18__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk19__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk20__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk21__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk22__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk23__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk24__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk25__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk26__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk27__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk28__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk29__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk30__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk31__SHIFT … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk0_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk1_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk2_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk3_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk4_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk5_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk6_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk7_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk8_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk9_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk10_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk11_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk12_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk13_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk15_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk16_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk17_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk18_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk19_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk20_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk21_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk22_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk23_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk24_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk25_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk26_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk27_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk28_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk29_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk30_MASK … #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk31_MASK … //DF_NCS_PG0_HardwareAssertMaskHigh #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk0__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk1__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk2__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk3__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk4__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk5__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk6__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk7__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk8__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk9__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk10__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk11__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk12__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk13__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk15__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk16__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk17__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk18__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk19__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk20__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk21__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk22__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk23__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk24__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk25__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk26__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk27__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk28__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk29__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk30__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk31__SHIFT … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk0_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk1_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk2_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk3_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk4_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk5_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk6_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk7_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk8_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk9_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk10_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk11_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk12_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk13_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk15_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk16_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk17_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk18_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk19_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk20_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk21_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk22_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk23_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk24_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk25_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk26_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk27_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk28_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk29_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk30_MASK … #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk31_MASK … #endif
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