linux/drivers/gpu/drm/amd/include/ivsrcid/ivsrcid_vislands30.h

/*
 * Volcanic Islands IV SRC Register documentation
 *
 * Copyright (C) 2015  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _IVSRCID_VISLANDS30_H_
#define _IVSRCID_VISLANDS30_H_


// IV Source IDs

#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT
#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT

#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC

#define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL
#define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC

#define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL
#define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS

#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC

#define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL
#define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL

#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS

#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC

#define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL
#define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL

#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS

#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC

#define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL
#define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL

#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0

#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1

#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E

#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F

#define VISLANDS30_IV_SRCID_HPD_RX_A
#define VISLANDS30_IV_EXTID_HPD_RX_A

#define VISLANDS30_IV_SRCID_HPD_RX_B
#define VISLANDS30_IV_EXTID_HPD_RX_B

#define VISLANDS30_IV_SRCID_HPD_RX_C
#define VISLANDS30_IV_EXTID_HPD_RX_C

#define VISLANDS30_IV_SRCID_HPD_RX_D
#define VISLANDS30_IV_EXTID_HPD_RX_D

#define VISLANDS30_IV_SRCID_HPD_RX_E
#define VISLANDS30_IV_EXTID_HPD_RX_E

#define VISLANDS30_IV_SRCID_HPD_RX_F
#define VISLANDS30_IV_EXTID_HPD_RX_F

#define VISLANDS30_IV_SRCID_GPIO_19

#define VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR
#define VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH

#define VISLANDS30_IV_SRBM_REG_ACCESS_ERROR


#define VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP
#define VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE

#define VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID

#define VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK

#define VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT
#define VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT

#define VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT
#define VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT

#define VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT
#define VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT

#define VISLANDS30_IV_SRCID_ACP

#define VISLANDS30_IV_SRCID_VCE_TRAP
#define VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE
#define VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY
#define VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME

#define VISLANDS30_IV_SRCID_CP_INT_RB
#define VISLANDS30_IV_SRCID_CP_INT_IB1
#define VISLANDS30_IV_SRCID_CP_INT_IB2
#define VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR
#define VISLANDS30_IV_SRCID_CP_END_OF_PIPE
#define VISLANDS30_IV_SRCID_CP_BAD_OPCODE
#define VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT
#define VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT
#define VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT
#define VISLANDS30_IV_SRCID_CP_GUI_IDLE
#define VISLANDS30_IV_SRCID_CP_GUI_BUSY

#define VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS
#define VISLANDS30_IV_SRCID_CP_ECC_ERROR

#define CARRIZO_IV_SRCID_CP_COMPUTE_QUERY_STATUS

#define VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT
#define VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL
#define VISLANDS30_IV_SRCID_CP_PREEMPT_ACK
#define VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT
#define VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR
#define VISLANDS30_IV_SRCID_CP_ECC_ERROR

#define VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR

#define VISLANDS30_IV_SDMA_ATOMIC_SRC_ID

#define VISLANDS30_IV_SRCID_SDMA_ECC_ERROR

#define VISLANDS30_IV_SRCID_SDMA_TRAP
#define VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE
#define VISLANDS30_IV_SRCID_SDMA_SEM_WAIT


#define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER

#define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH
#define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW

#define VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR
#define VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE

#define VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG

#define VISLANDS30_IV_SRCID_SDMA_PREEMPT
#define VISLANDS30_IV_SRCID_SDMA_VM_HOLE
#define VISLANDS30_IV_SRCID_SDMA_CTXEMPTY
#define VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID
#define VISLANDS30_IV_SRCID_SDMA_FROZEN
#define VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT
#define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE

#define VISLANDS30_IV_SRCID_CG_THERMAL_TRIG

#define VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER

/* These are not "real" source ids defined by HW */
#define VISLANDS30_IV_SRCID_VM_CONTEXT_ALL
#define VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL
#define VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL


/* IV Extended IDs */
#define VISLANDS30_IV_EXTID_NONE
#define VISLANDS30_IV_EXTID_INVALID

#endif // _IVSRCID_VISLANDS30_H_