/* * GMC_8_2 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef GMC_8_2_D_H #define GMC_8_2_D_H #define mmMC_CONFIG … #define mmMC_ARB_ATOMIC … #define mmMC_ARB_AGE_CNTL … #define mmMC_ARB_RET_CREDITS2 … #define mmMC_ARB_FED_CNTL … #define mmMC_ARB_GECC2_STATUS … #define mmMC_ARB_GECC2_MISC … #define mmMC_ARB_GECC2_DEBUG … #define mmMC_ARB_GECC2_DEBUG2 … #define mmMC_ARB_PERF_CID … #define mmMC_ARB_SNOOP … #define mmMC_ARB_GRUB … #define mmMC_ARB_GECC2 … #define mmMC_ARB_GECC2_CLI … #define mmMC_ARB_ADDR_SWIZ0 … #define mmMC_ARB_ADDR_SWIZ1 … #define mmMC_ARB_MISC3 … #define mmMC_ARB_GRUB_PROMOTE … #define mmMC_ARB_RTT_DATA … #define mmMC_ARB_RTT_CNTL0 … #define mmMC_ARB_RTT_CNTL1 … #define mmMC_ARB_RTT_CNTL2 … #define mmMC_ARB_RTT_DEBUG … #define mmMC_ARB_CAC_CNTL … #define mmMC_ARB_MISC2 … #define mmMC_ARB_MISC … #define mmMC_ARB_BANKMAP … #define mmMC_ARB_RAMCFG … #define mmMC_ARB_POP … #define mmMC_ARB_MINCLKS … #define mmMC_ARB_SQM_CNTL … #define mmMC_ARB_ADDR_HASH … #define mmMC_ARB_DRAM_TIMING … #define mmMC_ARB_DRAM_TIMING2 … #define mmMC_ARB_WTM_CNTL_RD … #define mmMC_ARB_WTM_CNTL_WR … #define mmMC_ARB_WTM_GRPWT_RD … #define mmMC_ARB_WTM_GRPWT_WR … #define mmMC_ARB_TM_CNTL_RD … #define mmMC_ARB_TM_CNTL_WR … #define mmMC_ARB_LAZY0_RD … #define mmMC_ARB_LAZY0_WR … #define mmMC_ARB_LAZY1_RD … #define mmMC_ARB_LAZY1_WR … #define mmMC_ARB_AGE_RD … #define mmMC_ARB_AGE_WR … #define mmMC_ARB_RFSH_CNTL … #define mmMC_ARB_RFSH_RATE … #define mmMC_ARB_PM_CNTL … #define mmMC_ARB_GDEC_RD_CNTL … #define mmMC_ARB_GDEC_WR_CNTL … #define mmMC_ARB_LM_RD … #define mmMC_ARB_LM_WR … #define mmMC_ARB_REMREQ … #define mmMC_ARB_REPLAY … #define mmMC_ARB_RET_CREDITS_RD … #define mmMC_ARB_RET_CREDITS_WR … #define mmMC_ARB_MAX_LAT_CID … #define mmMC_ARB_MAX_LAT_RSLT0 … #define mmMC_ARB_MAX_LAT_RSLT1 … #define mmMC_ARB_GRUB_REALTIME_RD … #define mmMC_ARB_CG … #define mmMC_ARB_GRUB_REALTIME_WR … #define mmMC_ARB_DRAM_TIMING_1 … #define mmMC_ARB_BUSY_STATUS … #define mmMC_ARB_DRAM_TIMING2_1 … #define mmMC_ARB_GRUB2 … #define mmMC_ARB_BURST_TIME … #define mmMC_CITF_XTRA_ENABLE … #define mmCC_MC_MAX_CHANNEL … #define mmMC_CG_CONFIG … #define mmMC_CITF_CNTL … #define mmMC_CITF_CREDITS_VM … #define mmMC_CITF_CREDITS_ARB_RD … #define mmMC_CITF_CREDITS_ARB_WR … #define mmMC_CITF_DAGB_CNTL … #define mmMC_CITF_INT_CREDITS … #define mmMC_CITF_RET_MODE … #define mmMC_CITF_DAGB_DLY … #define mmMC_RD_GRP_EXT … #define mmMC_WR_GRP_EXT … #define mmMC_CITF_REMREQ … #define mmMC_WR_TC0 … #define mmMC_WR_TC1 … #define mmMC_CITF_INT_CREDITS_WR … #define mmMC_CITF_CREDITS_ARB_RD2 … #define mmMC_CITF_WTM_RD_CNTL … #define mmMC_CITF_WTM_WR_CNTL … #define mmMC_RD_CB … #define mmMC_RD_DB … #define mmMC_RD_TC0 … #define mmMC_RD_TC1 … #define mmMC_RD_HUB … #define mmMC_WR_CB … #define mmMC_WR_DB … #define mmMC_WR_HUB … #define mmMC_CITF_CREDITS_XBAR … #define mmMC_RD_GRP_LCL … #define mmMC_WR_GRP_LCL … #define mmMC_CITF_PERF_MON_CNTL2 … #define mmMC_CITF_PERF_MON_RSLT2 … #define mmMC_CITF_MISC_RD_CG … #define mmMC_CITF_MISC_WR_CG … #define mmMC_CITF_MISC_VM_CG … #define mmMC_HUB_MISC_POWER … #define mmMC_HUB_MISC_HUB_CG … #define mmMC_HUB_MISC_VM_CG … #define mmMC_HUB_MISC_SIP_CG … #define mmMC_HUB_MISC_STATUS … #define mmMC_HUB_MISC_OVERRIDE … #define mmMC_HUB_MISC_FRAMING … #define mmMC_HUB_WDP_CNTL … #define mmMC_HUB_WDP_ERR … #define mmMC_HUB_WDP_BP … #define mmMC_HUB_WDP_STATUS … #define mmMC_HUB_RDREQ_STATUS … #define mmMC_HUB_WRRET_STATUS … #define mmMC_HUB_RDREQ_CNTL … #define mmMC_HUB_WRRET_CNTL … #define mmMC_HUB_RDREQ_WTM_CNTL … #define mmMC_HUB_WDP_WTM_CNTL … #define mmMC_HUB_WDP_CREDITS … #define mmMC_HUB_WDP_CREDITS2 … #define mmMC_HUB_WDP_GBL0 … #define mmMC_HUB_WDP_GBL1 … #define mmMC_HUB_RDREQ_CREDITS … #define mmMC_HUB_RDREQ_CREDITS2 … #define mmMC_HUB_SHARED_DAGB_DLY … #define mmMC_HUB_MISC_IDLE_STATUS … #define mmMC_HUB_RDREQ_DMIF_LIMIT … #define mmMC_HUB_RDREQ_ACPG_LIMIT … #define mmMC_HUB_WDP_BYPASS_GBL0 … #define mmMC_HUB_WDP_BYPASS_GBL1 … #define mmMC_HUB_RDREQ_BYPASS_GBL0 … #define mmMC_HUB_WDP_SH2 … #define mmMC_HUB_WDP_SH3 … #define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS … #define mmMC_HUB_RDREQ_MCDW … #define mmMC_HUB_RDREQ_MCDX … #define mmMC_HUB_RDREQ_MCDY … #define mmMC_HUB_RDREQ_MCDZ … #define mmMC_HUB_RDREQ_SIP … #define mmMC_HUB_RDREQ_GBL0 … #define mmMC_HUB_RDREQ_GBL1 … #define mmMC_HUB_RDREQ_SMU … #define mmMC_HUB_RDREQ_SDMA0 … #define mmMC_HUB_RDREQ_HDP … #define mmMC_HUB_RDREQ_SDMA1 … #define mmMC_HUB_RDREQ_RLC … #define mmMC_HUB_RDREQ_SEM … #define mmMC_HUB_RDREQ_VCE0 … #define mmMC_HUB_RDREQ_UMC … #define mmMC_HUB_RDREQ_UVD … #define mmMC_HUB_RDREQ_DMIF … #define mmMC_HUB_RDREQ_MCIF … #define mmMC_HUB_RDREQ_VMC … #define mmMC_HUB_RDREQ_VCEU0 … #define mmMC_HUB_WDP_MCDW … #define mmMC_HUB_WDP_MCDX … #define mmMC_HUB_WDP_MCDY … #define mmMC_HUB_WDP_MCDZ … #define mmMC_HUB_WDP_SIP … #define mmMC_HUB_WDP_SDMA1 … #define mmMC_HUB_WDP_SH0 … #define mmMC_HUB_WDP_MCIF … #define mmMC_HUB_WDP_VCE0 … #define mmMC_HUB_WDP_XDP … #define mmMC_HUB_WDP_IH … #define mmMC_HUB_WDP_RLC … #define mmMC_HUB_WDP_SEM … #define mmMC_HUB_WDP_SMU … #define mmMC_HUB_WDP_SH1 … #define mmMC_HUB_WDP_UMC … #define mmMC_HUB_WDP_UVD … #define mmMC_HUB_WDP_HDP … #define mmMC_HUB_WDP_SDMA0 … #define mmMC_HUB_WRRET_MCDW … #define mmMC_HUB_WRRET_MCDX … #define mmMC_HUB_WRRET_MCDY … #define mmMC_HUB_WRRET_MCDZ … #define mmMC_HUB_WDP_VCEU0 … #define mmMC_HUB_WDP_XDMAM … #define mmMC_HUB_WDP_XDMA … #define mmMC_HUB_RDREQ_XDMAM … #define mmMC_HUB_RDREQ_ACPG … #define mmMC_HUB_RDREQ_ACPO … #define mmMC_HUB_RDREQ_SAMMSP … #define mmMC_HUB_RDREQ_VP8 … #define mmMC_HUB_RDREQ_VP8U … #define mmMC_HUB_WDP_ACPG … #define mmMC_HUB_WDP_ACPO … #define mmMC_HUB_WDP_SAMMSP … #define mmMC_HUB_WDP_VP8 … #define mmMC_HUB_WDP_VP8U … #define mmMC_HUB_RDREQ_ISP_SPM … #define mmMC_HUB_RDREQ_ISP_MPM … #define mmMC_HUB_RDREQ_ISP_CCPU … #define mmMC_HUB_WDP_ISP_SPM … #define mmMC_HUB_WDP_ISP_MPS … #define mmMC_HUB_WDP_ISP_MPM … #define mmMC_HUB_WDP_ISP_CCPU … #define mmMC_HUB_RDREQ_MCDS … #define mmMC_HUB_RDREQ_MCDT … #define mmMC_HUB_RDREQ_MCDU … #define mmMC_HUB_RDREQ_MCDV … #define mmMC_HUB_WDP_MCDS … #define mmMC_HUB_WDP_MCDT … #define mmMC_HUB_WDP_MCDU … #define mmMC_HUB_WDP_MCDV … #define mmMC_HUB_WRRET_MCDS … #define mmMC_HUB_WRRET_MCDT … #define mmMC_HUB_WRRET_MCDU … #define mmMC_HUB_WRRET_MCDV … #define mmMC_HUB_WDP_CREDITS_MCDW … #define mmMC_HUB_WDP_CREDITS_MCDX … #define mmMC_HUB_WDP_CREDITS_MCDY … #define mmMC_HUB_WDP_CREDITS_MCDZ … #define mmMC_HUB_WDP_CREDITS_MCDS … #define mmMC_HUB_WDP_CREDITS_MCDT … #define mmMC_HUB_WDP_CREDITS_MCDU … #define mmMC_HUB_WDP_CREDITS_MCDV … #define mmMC_HUB_WDP_BP2 … #define mmMC_HUB_RDREQ_VCE1 … #define mmMC_HUB_RDREQ_VCEU1 … #define mmMC_HUB_WDP_VCE1 … #define mmMC_HUB_WDP_VCEU1 … #define mmMC_RPB_CONF … #define mmMC_RPB_IF_CONF … #define mmMC_RPB_DBG1 … #define mmMC_RPB_EFF_CNTL … #define mmMC_RPB_ARB_CNTL … #define mmMC_RPB_BIF_CNTL … #define mmMC_RPB_WR_SWITCH_CNTL … #define mmMC_RPB_WR_COMBINE_CNTL … #define mmMC_RPB_RD_SWITCH_CNTL … #define mmMC_RPB_CID_QUEUE_WR … #define mmMC_RPB_CID_QUEUE_RD … #define mmMC_RPB_PERF_COUNTER_CNTL … #define mmMC_RPB_PERF_COUNTER_STATUS … #define mmMC_RPB_CID_QUEUE_EX … #define mmMC_RPB_CID_QUEUE_EX_DATA … #define mmMC_RPB_TCI_CNTL … #define mmMC_RPB_TCI_CNTL2 … #define mmMC_SHARED_CHMAP … #define mmMC_SHARED_CHREMAP … #define mmMC_RD_GRP_GFX … #define mmMC_WR_GRP_GFX … #define mmMC_RD_GRP_SYS … #define mmMC_WR_GRP_SYS … #define mmMC_RD_GRP_OTH … #define mmMC_WR_GRP_OTH … #define mmMC_VM_FB_LOCATION … #define mmMC_VM_AGP_TOP … #define mmMC_VM_AGP_BOT … #define mmMC_VM_AGP_BASE … #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR … #define mmMC_VM_DC_WRITE_CNTL … #define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR … #define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR … #define mmMC_VM_MX_L1_TLB_CNTL … #define mmMC_VM_FB_OFFSET … #define mmMC_VM_STEERING … #define mmMC_SHARED_CHREMAP2 … #define mmMC_SHARED_VF_ENABLE … #define mmMC_SHARED_VIRT_RESET_REQ … #define mmMC_SHARED_ACTIVE_FCN_ID … #define mmMC_CONFIG_MCD … #define mmMC_CG_CONFIG_MCD … #define mmMC_MEM_POWER_LS … #define mmMC_SHARED_BLACKOUT_CNTL … #define mmMC_VM_MB_L1_TLB0_DEBUG … #define mmMC_VM_MB_L1_TLB1_DEBUG … #define mmMC_VM_MB_L1_TLB2_DEBUG … #define mmMC_VM_MB_L1_TLB0_STATUS … #define mmMC_VM_MB_L1_TLB1_STATUS … #define mmMC_VM_MB_L1_TLB2_STATUS … #define mmMC_VM_MB_L2ARBITER_L2_CREDITS … #define mmMC_VM_MB_L1_TLB3_DEBUG … #define mmMC_VM_MB_L1_TLB3_STATUS … #define mmMC_VM_MD_L1_TLB0_DEBUG … #define mmMC_VM_MD_L1_TLB1_DEBUG … #define mmMC_VM_MD_L1_TLB2_DEBUG … #define mmMC_VM_MD_L1_TLB0_STATUS … #define mmMC_VM_MD_L1_TLB1_STATUS … #define mmMC_VM_MD_L1_TLB2_STATUS … #define mmMC_VM_MD_L2ARBITER_L2_CREDITS … #define mmMC_VM_MD_L1_TLB3_DEBUG … #define mmMC_VM_MD_L1_TLB3_STATUS … #define mmMC_XPB_RTR_SRC_APRTR0 … #define mmMC_XPB_RTR_SRC_APRTR1 … #define mmMC_XPB_RTR_SRC_APRTR2 … #define mmMC_XPB_RTR_SRC_APRTR3 … #define mmMC_XPB_RTR_SRC_APRTR4 … #define mmMC_XPB_RTR_SRC_APRTR5 … #define mmMC_XPB_RTR_SRC_APRTR6 … #define mmMC_XPB_RTR_SRC_APRTR7 … #define mmMC_XPB_RTR_SRC_APRTR8 … #define mmMC_XPB_RTR_SRC_APRTR9 … #define mmMC_XPB_XDMA_RTR_SRC_APRTR0 … #define mmMC_XPB_XDMA_RTR_SRC_APRTR1 … #define mmMC_XPB_XDMA_RTR_SRC_APRTR2 … #define mmMC_XPB_XDMA_RTR_SRC_APRTR3 … #define mmMC_XPB_RTR_DEST_MAP0 … #define mmMC_XPB_RTR_DEST_MAP1 … #define mmMC_XPB_RTR_DEST_MAP2 … #define mmMC_XPB_RTR_DEST_MAP3 … #define mmMC_XPB_RTR_DEST_MAP4 … #define mmMC_XPB_RTR_DEST_MAP5 … #define mmMC_XPB_RTR_DEST_MAP6 … #define mmMC_XPB_RTR_DEST_MAP7 … #define mmMC_XPB_RTR_DEST_MAP8 … #define mmMC_XPB_RTR_DEST_MAP9 … #define mmMC_XPB_XDMA_RTR_DEST_MAP0 … #define mmMC_XPB_XDMA_RTR_DEST_MAP1 … #define mmMC_XPB_XDMA_RTR_DEST_MAP2 … #define mmMC_XPB_XDMA_RTR_DEST_MAP3 … #define mmMC_XPB_CLG_CFG0 … #define mmMC_XPB_CLG_CFG1 … #define mmMC_XPB_CLG_CFG2 … #define mmMC_XPB_CLG_CFG3 … #define mmMC_XPB_CLG_CFG4 … #define mmMC_XPB_CLG_CFG5 … #define mmMC_XPB_CLG_CFG6 … #define mmMC_XPB_CLG_CFG7 … #define mmMC_XPB_CLG_CFG8 … #define mmMC_XPB_CLG_CFG9 … #define mmMC_XPB_CLG_CFG10 … #define mmMC_XPB_CLG_CFG11 … #define mmMC_XPB_CLG_CFG12 … #define mmMC_XPB_CLG_CFG13 … #define mmMC_XPB_CLG_CFG14 … #define mmMC_XPB_CLG_CFG15 … #define mmMC_XPB_CLG_CFG16 … #define mmMC_XPB_CLG_CFG17 … #define mmMC_XPB_CLG_CFG18 … #define mmMC_XPB_CLG_CFG19 … #define mmMC_XPB_CLG_EXTRA … #define mmMC_XPB_LB_ADDR … #define mmMC_XPB_UNC_THRESH_HST … #define mmMC_XPB_UNC_THRESH_SID … #define mmMC_XPB_WCB_STS … #define mmMC_XPB_WCB_CFG … #define mmMC_XPB_P2P_BAR_CFG … #define mmMC_XPB_P2P_BAR0 … #define mmMC_XPB_P2P_BAR1 … #define mmMC_XPB_P2P_BAR2 … #define mmMC_XPB_P2P_BAR3 … #define mmMC_XPB_P2P_BAR4 … #define mmMC_XPB_P2P_BAR5 … #define mmMC_XPB_P2P_BAR6 … #define mmMC_XPB_P2P_BAR7 … #define mmMC_XPB_P2P_BAR_SETUP … #define mmMC_XPB_P2P_BAR_DEBUG … #define mmMC_XPB_P2P_BAR_DELTA_ABOVE … #define mmMC_XPB_P2P_BAR_DELTA_BELOW … #define mmMC_XPB_PEER_SYS_BAR0 … #define mmMC_XPB_PEER_SYS_BAR1 … #define mmMC_XPB_PEER_SYS_BAR2 … #define mmMC_XPB_PEER_SYS_BAR3 … #define mmMC_XPB_PEER_SYS_BAR4 … #define mmMC_XPB_PEER_SYS_BAR5 … #define mmMC_XPB_PEER_SYS_BAR6 … #define mmMC_XPB_PEER_SYS_BAR7 … #define mmMC_XPB_PEER_SYS_BAR8 … #define mmMC_XPB_PEER_SYS_BAR9 … #define mmMC_XPB_XDMA_PEER_SYS_BAR0 … #define mmMC_XPB_XDMA_PEER_SYS_BAR1 … #define mmMC_XPB_XDMA_PEER_SYS_BAR2 … #define mmMC_XPB_XDMA_PEER_SYS_BAR3 … #define mmMC_XPB_CLK_GAT … #define mmMC_XPB_INTF_CFG … #define mmMC_XPB_INTF_STS … #define mmMC_XPB_PIPE_STS … #define mmMC_XPB_SUB_CTRL … #define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB … #define mmMC_XPB_PERF_KNOBS … #define mmMC_XPB_STICKY … #define mmMC_XPB_STICKY_W1C … #define mmMC_XPB_MISC_CFG … #define mmMC_XPB_CLG_CFG20 … #define mmMC_XPB_CLG_CFG21 … #define mmMC_XPB_CLG_CFG22 … #define mmMC_XPB_CLG_CFG23 … #define mmMC_XPB_CLG_CFG24 … #define mmMC_XPB_CLG_CFG25 … #define mmMC_XPB_CLG_CFG26 … #define mmMC_XPB_CLG_CFG27 … #define mmMC_XPB_CLG_CFG28 … #define mmMC_XPB_CLG_CFG29 … #define mmMC_XPB_CLG_CFG30 … #define mmMC_XPB_CLG_CFG31 … #define mmMC_XPB_INTF_CFG2 … #define mmMC_XPB_CLG_EXTRA_RD … #define mmMC_XPB_CLG_CFG32 … #define mmMC_XPB_CLG_CFG33 … #define mmMC_XPB_CLG_CFG34 … #define mmMC_XPB_CLG_CFG35 … #define mmMC_XPB_CLG_CFG36 … #define mmMC_XBAR_ADDR_DEC … #define mmMC_XBAR_REMOTE … #define mmMC_XBAR_WRREQ_CREDIT … #define mmMC_XBAR_RDREQ_CREDIT … #define mmMC_XBAR_RDREQ_PRI_CREDIT … #define mmMC_XBAR_WRRET_CREDIT1 … #define mmMC_XBAR_WRRET_CREDIT2 … #define mmMC_XBAR_RDRET_CREDIT1 … #define mmMC_XBAR_RDRET_CREDIT2 … #define mmMC_XBAR_RDRET_PRI_CREDIT1 … #define mmMC_XBAR_RDRET_PRI_CREDIT2 … #define mmMC_XBAR_CHTRIREMAP … #define mmMC_XBAR_TWOCHAN … #define mmMC_XBAR_ARB … #define mmMC_XBAR_ARB_MAX_BURST … #define mmMC_XBAR_FIFO_MON_CNTL0 … #define mmMC_XBAR_FIFO_MON_CNTL1 … #define mmMC_XBAR_FIFO_MON_CNTL2 … #define mmMC_XBAR_FIFO_MON_RSLT0 … #define mmMC_XBAR_FIFO_MON_RSLT1 … #define mmMC_XBAR_FIFO_MON_RSLT2 … #define mmMC_XBAR_FIFO_MON_RSLT3 … #define mmMC_XBAR_FIFO_MON_MAX_THSH … #define mmMC_XBAR_SPARE0 … #define mmMC_XBAR_SPARE1 … #define mmMC_CITF_PERFCOUNTER_LO … #define mmMC_HUB_PERFCOUNTER_LO … #define mmMC_RPB_PERFCOUNTER_LO … #define mmMC_MCBVM_PERFCOUNTER_LO … #define mmMC_MCDVM_PERFCOUNTER_LO … #define mmMC_VM_L2_PERFCOUNTER_LO … #define mmMC_ARB_PERFCOUNTER_LO … #define mmATC_PERFCOUNTER_LO … #define mmMC_CITF_PERFCOUNTER_HI … #define mmMC_HUB_PERFCOUNTER_HI … #define mmMC_MCBVM_PERFCOUNTER_HI … #define mmMC_MCDVM_PERFCOUNTER_HI … #define mmMC_RPB_PERFCOUNTER_HI … #define mmMC_VM_L2_PERFCOUNTER_HI … #define mmMC_ARB_PERFCOUNTER_HI … #define mmATC_PERFCOUNTER_HI … #define mmMC_CITF_PERFCOUNTER0_CFG … #define mmMC_CITF_PERFCOUNTER1_CFG … #define mmMC_CITF_PERFCOUNTER2_CFG … #define mmMC_CITF_PERFCOUNTER3_CFG … #define mmMC_HUB_PERFCOUNTER0_CFG … #define mmMC_HUB_PERFCOUNTER1_CFG … #define mmMC_HUB_PERFCOUNTER2_CFG … #define mmMC_HUB_PERFCOUNTER3_CFG … #define mmMC_RPB_PERFCOUNTER0_CFG … #define mmMC_RPB_PERFCOUNTER1_CFG … #define mmMC_RPB_PERFCOUNTER2_CFG … #define mmMC_RPB_PERFCOUNTER3_CFG … #define mmMC_ARB_PERFCOUNTER0_CFG … #define mmMC_ARB_PERFCOUNTER1_CFG … #define mmMC_ARB_PERFCOUNTER2_CFG … #define mmMC_ARB_PERFCOUNTER3_CFG … #define mmMC_MCBVM_PERFCOUNTER0_CFG … #define mmMC_MCBVM_PERFCOUNTER1_CFG … #define mmMC_MCBVM_PERFCOUNTER2_CFG … #define mmMC_MCBVM_PERFCOUNTER3_CFG … #define mmMC_MCDVM_PERFCOUNTER0_CFG … #define mmMC_MCDVM_PERFCOUNTER1_CFG … #define mmMC_MCDVM_PERFCOUNTER2_CFG … #define mmMC_MCDVM_PERFCOUNTER3_CFG … #define mmATC_PERFCOUNTER0_CFG … #define mmATC_PERFCOUNTER1_CFG … #define mmATC_PERFCOUNTER2_CFG … #define mmATC_PERFCOUNTER3_CFG … #define mmMC_VM_L2_PERFCOUNTER0_CFG … #define mmMC_VM_L2_PERFCOUNTER1_CFG … #define mmMC_CITF_PERFCOUNTER_RSLT_CNTL … #define mmMC_HUB_PERFCOUNTER_RSLT_CNTL … #define mmMC_RPB_PERFCOUNTER_RSLT_CNTL … #define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL … #define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL … #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmMC_ARB_PERFCOUNTER_RSLT_CNTL … #define mmATC_PERFCOUNTER_RSLT_CNTL … #define mmCHUB_ATC_PERFCOUNTER_LO … #define mmCHUB_ATC_PERFCOUNTER_HI … #define mmCHUB_ATC_PERFCOUNTER0_CFG … #define mmCHUB_ATC_PERFCOUNTER1_CFG … #define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL … #define mmMC_GRUB_PERFCOUNTER_LO … #define mmMC_GRUB_PERFCOUNTER_HI … #define mmMC_GRUB_PERFCOUNTER0_CFG … #define mmMC_GRUB_PERFCOUNTER1_CFG … #define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL … #define mmATC_VM_APERTURE0_LOW_ADDR … #define mmATC_VM_APERTURE1_LOW_ADDR … #define mmATC_VM_APERTURE0_HIGH_ADDR … #define mmATC_VM_APERTURE1_HIGH_ADDR … #define mmATC_VM_APERTURE0_CNTL … #define mmATC_VM_APERTURE1_CNTL … #define mmATC_VM_APERTURE0_CNTL2 … #define mmATC_VM_APERTURE1_CNTL2 … #define mmATC_ATS_CNTL … #define mmATC_ATS_DEBUG … #define mmATC_ATS_FAULT_DEBUG … #define mmATC_ATS_STATUS … #define mmATC_ATS_FAULT_CNTL … #define mmATC_ATS_FAULT_STATUS_INFO … #define mmATC_ATS_FAULT_STATUS_ADDR … #define mmATC_ATS_DEFAULT_PAGE_LOW … #define mmATC_ATS_DEFAULT_PAGE_CNTL … #define mmATC_ATS_FAULT_STATUS_INFO2 … #define mmATC_MISC_CG … #define mmATC_L2_CNTL … #define mmATC_L2_CNTL2 … #define mmATC_L2_DEBUG … #define mmATC_L2_DEBUG2 … #define mmATC_L2_CACHE_DATA0 … #define mmATC_L2_CACHE_DATA1 … #define mmATC_L2_CACHE_DATA2 … #define mmATC_L1_CNTL … #define mmATC_L1_ADDRESS_OFFSET … #define mmATC_L1RD_DEBUG_TLB … #define mmATC_L1WR_DEBUG_TLB … #define mmATC_L1RD_STATUS … #define mmATC_L1WR_STATUS … #define mmATC_L1RD_DEBUG2_TLB … #define mmATC_L1WR_DEBUG2_TLB … #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS … #define mmATC_VMID0_PASID_MAPPING … #define mmATC_VMID1_PASID_MAPPING … #define mmATC_VMID2_PASID_MAPPING … #define mmATC_VMID3_PASID_MAPPING … #define mmATC_VMID4_PASID_MAPPING … #define mmATC_VMID5_PASID_MAPPING … #define mmATC_VMID6_PASID_MAPPING … #define mmATC_VMID7_PASID_MAPPING … #define mmATC_VMID8_PASID_MAPPING … #define mmATC_VMID9_PASID_MAPPING … #define mmATC_VMID10_PASID_MAPPING … #define mmATC_VMID11_PASID_MAPPING … #define mmATC_VMID12_PASID_MAPPING … #define mmATC_VMID13_PASID_MAPPING … #define mmATC_VMID14_PASID_MAPPING … #define mmATC_VMID15_PASID_MAPPING … #define mmATC_ATS_VMID_STATUS … #define mmATC_ATS_SMU_STATUS … #define mmATC_L2_CNTL3 … #define mmATC_L2_STATUS … #define mmATC_L2_STATUS2 … #define mmGMCON_RENG_RAM_INDEX … #define mmGMCON_RENG_RAM_DATA … #define mmGMCON_RENG_EXECUTE … #define mmGMCON_MISC … #define mmGMCON_MISC2 … #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 … #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 … #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 … #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmGMCON_PERF_MON_CNTL0 … #define mmGMCON_PERF_MON_CNTL1 … #define mmGMCON_PERF_MON_RSLT0 … #define mmGMCON_PERF_MON_RSLT1 … #define mmGMCON_PGFSM_CONFIG … #define mmGMCON_PGFSM_WRITE … #define mmGMCON_PGFSM_READ … #define mmGMCON_MISC3 … #define mmGMCON_MASK … #define mmGMCON_LPT_TARGET … #define mmGMCON_DEBUG … #define mmVM_L2_CNTL … #define mmVM_L2_CNTL2 … #define mmVM_L2_CNTL3 … #define mmVM_L2_STATUS … #define mmVM_CONTEXT0_CNTL … #define mmVM_CONTEXT1_CNTL … #define mmVM_DUMMY_PAGE_FAULT_CNTL … #define mmVM_DUMMY_PAGE_FAULT_ADDR … #define mmVM_CONTEXT0_CNTL2 … #define mmVM_CONTEXT1_CNTL2 … #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR … #define mmVM_INVALIDATE_REQUEST … #define mmVM_INVALIDATE_RESPONSE … #define mmVM_PRT_APERTURE0_LOW_ADDR … #define mmVM_PRT_APERTURE1_LOW_ADDR … #define mmVM_PRT_APERTURE2_LOW_ADDR … #define mmVM_PRT_APERTURE3_LOW_ADDR … #define mmVM_PRT_APERTURE0_HIGH_ADDR … #define mmVM_PRT_APERTURE1_HIGH_ADDR … #define mmVM_PRT_APERTURE2_HIGH_ADDR … #define mmVM_PRT_APERTURE3_HIGH_ADDR … #define mmVM_PRT_CNTL … #define mmVM_CONTEXTS_DISABLE … #define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS … #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS … #define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT … #define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT … #define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR … #define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR … #define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR … #define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR … #define mmVM_FAULT_CLIENT_ID … #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR … #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR … #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR … #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR … #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR … #define mmVM_DEBUG … #define mmVM_L2_CG … #define mmVM_L2_BANK_SELECT_MASKA … #define mmVM_L2_BANK_SELECT_MASKB … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR … #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET … #define mmVM_L2_CNTL4 … #define mmVM_L2_BANK_SELECT_RESERVED_CID … #define mmMC_VM_FB_SIZE_OFFSET_VF0 … #define mmMC_VM_FB_SIZE_OFFSET_VF1 … #define mmMC_VM_FB_SIZE_OFFSET_VF2 … #define mmMC_VM_FB_SIZE_OFFSET_VF3 … #define mmMC_VM_FB_SIZE_OFFSET_VF4 … #define mmMC_VM_FB_SIZE_OFFSET_VF5 … #define mmMC_VM_FB_SIZE_OFFSET_VF6 … #define mmMC_VM_FB_SIZE_OFFSET_VF7 … #define mmMC_VM_FB_SIZE_OFFSET_VF8 … #define mmMC_VM_FB_SIZE_OFFSET_VF9 … #define mmMC_VM_FB_SIZE_OFFSET_VF10 … #define mmMC_VM_FB_SIZE_OFFSET_VF11 … #define mmMC_VM_FB_SIZE_OFFSET_VF12 … #define mmMC_VM_FB_SIZE_OFFSET_VF13 … #define mmMC_VM_FB_SIZE_OFFSET_VF14 … #define mmMC_VM_FB_SIZE_OFFSET_VF15 … #define mmMC_VM_NB_MMIOBASE … #define mmMC_VM_NB_MMIOLIMIT … #define mmMC_VM_NB_PCI_CTRL … #define mmMC_VM_NB_PCI_ARB … #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmMC_VM_NB_TOP_OF_DRAM3 … #define mmMC_VM_MARC_BASE_LO_0 … #define mmMC_VM_MARC_BASE_LO_1 … #define mmMC_VM_MARC_BASE_LO_2 … #define mmMC_VM_MARC_BASE_LO_3 … #define mmMC_VM_MARC_BASE_HI_0 … #define mmMC_VM_MARC_BASE_HI_1 … #define mmMC_VM_MARC_BASE_HI_2 … #define mmMC_VM_MARC_BASE_HI_3 … #define mmMC_VM_MARC_RELOC_LO_0 … #define mmMC_VM_MARC_RELOC_LO_1 … #define mmMC_VM_MARC_RELOC_LO_2 … #define mmMC_VM_MARC_RELOC_LO_3 … #define mmMC_VM_MARC_RELOC_HI_0 … #define mmMC_VM_MARC_RELOC_HI_1 … #define mmMC_VM_MARC_RELOC_HI_2 … #define mmMC_VM_MARC_RELOC_HI_3 … #define mmMC_VM_MARC_LEN_LO_0 … #define mmMC_VM_MARC_LEN_LO_1 … #define mmMC_VM_MARC_LEN_LO_2 … #define mmMC_VM_MARC_LEN_LO_3 … #define mmMC_VM_MARC_LEN_HI_0 … #define mmMC_VM_MARC_LEN_HI_1 … #define mmMC_VM_MARC_LEN_HI_2 … #define mmMC_VM_MARC_LEN_HI_3 … #define mmMC_VM_MARC_CNTL … #define mmMC_ARB_HARSH_EN_RD … #define mmMC_ARB_HARSH_EN_WR … #define mmMC_ARB_HARSH_TX_HI0_RD … #define mmMC_ARB_HARSH_TX_HI0_WR … #define mmMC_ARB_HARSH_TX_HI1_RD … #define mmMC_ARB_HARSH_TX_HI1_WR … #define mmMC_ARB_HARSH_TX_LO0_RD … #define mmMC_ARB_HARSH_TX_LO0_WR … #define mmMC_ARB_HARSH_TX_LO1_RD … #define mmMC_ARB_HARSH_TX_LO1_WR … #define mmMC_ARB_HARSH_BWPERIOD0_RD … #define mmMC_ARB_HARSH_BWPERIOD0_WR … #define mmMC_ARB_HARSH_BWPERIOD1_RD … #define mmMC_ARB_HARSH_BWPERIOD1_WR … #define mmMC_ARB_HARSH_BWCNT0_RD … #define mmMC_ARB_HARSH_BWCNT0_WR … #define mmMC_ARB_HARSH_BWCNT1_RD … #define mmMC_ARB_HARSH_BWCNT1_WR … #define mmMC_ARB_HARSH_SAT0_RD … #define mmMC_ARB_HARSH_SAT0_WR … #define mmMC_ARB_HARSH_SAT1_RD … #define mmMC_ARB_HARSH_SAT1_WR … #define mmMC_ARB_HARSH_CTL_RD … #define mmMC_ARB_HARSH_CTL_WR … #define mmMC_ARB_GRUB_PRIORITY1_RD … #define mmMC_ARB_GRUB_PRIORITY1_WR … #define mmMC_ARB_GRUB_PRIORITY2_RD … #define mmMC_ARB_GRUB_PRIORITY2_WR … #define mmMC_FUS_DRAM0_CS0_BASE … #define mmMC_FUS_DRAM1_CS0_BASE … #define mmMC_FUS_DRAM0_CS1_BASE … #define mmMC_FUS_DRAM1_CS1_BASE … #define mmMC_FUS_DRAM0_CS2_BASE … #define mmMC_FUS_DRAM1_CS2_BASE … #define mmMC_FUS_DRAM0_CS3_BASE … #define mmMC_FUS_DRAM1_CS3_BASE … #define mmMC_FUS_DRAM0_CS01_MASK … #define mmMC_FUS_DRAM1_CS01_MASK … #define mmMC_FUS_DRAM0_CS23_MASK … #define mmMC_FUS_DRAM1_CS23_MASK … #define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING … #define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING … #define mmMC_FUS_DRAM0_CTL_BASE … #define mmMC_FUS_DRAM1_CTL_BASE … #define mmMC_FUS_DRAM0_CTL_LIMIT … #define mmMC_FUS_DRAM1_CTL_LIMIT … #define mmMC_FUS_DRAM_CTL_HIGH_01 … #define mmMC_FUS_DRAM_CTL_HIGH_23 … #define mmMC_FUS_DRAM_MODE … #define mmMC_FUS_DRAM_APER_BASE … #define mmMC_FUS_DRAM_APER_TOP … #define mmMC_FUS_DRAM_APER_DEF … #define mmMC_FUS_ARB_GARLIC_ISOC_PRI … #define mmMC_FUS_ARB_GARLIC_CNTL … #define mmMC_FUS_ARB_GARLIC_WR_PRI … #define mmMC_FUS_ARB_GARLIC_WR_PRI2 … #define mmMC_CG_DATAPORT … #define mmMC_GRUB_PROBE_MAP … #define mmMC_GRUB_POST_PROBE_DELAY … #define mmMC_GRUB_PROBE_CREDITS … #define mmMC_GRUB_FEATURES … #define mmMC_GRUB_TX_CREDITS … #define mmMC_GRUB_TCB_INDEX … #define mmMC_GRUB_TCB_DATA_LO … #define mmMC_GRUB_TCB_DATA_HI … #define mmMCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB_BUF_PITCH … #define mmMCIF_WB0_MCIF_WB_BUF_PITCH … #define mmMCIF_WB1_MCIF_WB_BUF_PITCH … #define mmMCIF_WB2_MCIF_WB_BUF_PITCH … #define mmMCIF_WB_BUF_1_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB_BUF_2_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB_BUF_3_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB_BUF_4_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB_URGENCY_WATERMARK … #define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK … #define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK … #define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK … #define mmMCIF_WB_TEST_DEBUG_INDEX … #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX … #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX … #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX … #define mmMCIF_WB_TEST_DEBUG_DATA … #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA … #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA … #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA … #define mmMCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB_HVVMID_CONTROL … #define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL … #define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL … #define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL … #endif /* GMC_8_2_D_H */
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