/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/module.h> #include <linux/pci.h> #include <drm/drm_cache.h> #include "amdgpu.h" #include "gmc_v8_0.h" #include "amdgpu_ucode.h" #include "amdgpu_amdkfd.h" #include "amdgpu_gem.h" #include "gmc/gmc_8_1_d.h" #include "gmc/gmc_8_1_sh_mask.h" #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "vid.h" #include "vi.h" #include "amdgpu_atombios.h" #include "ivsrcid/ivsrcid_vislands30.h" static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); static int gmc_v8_0_wait_for_idle(void *handle); MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; static const u32 golden_settings_tonga_a11[] = …; static const u32 tonga_mgcg_cgcg_init[] = …; static const u32 golden_settings_fiji_a10[] = …; static const u32 fiji_mgcg_cgcg_init[] = …; static const u32 golden_settings_polaris11_a11[] = …; static const u32 golden_settings_polaris10_a11[] = …; static const u32 cz_mgcg_cgcg_init[] = …; static const u32 stoney_mgcg_cgcg_init[] = …; static const u32 golden_settings_stoney_common[] = …; static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) { … } static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) { … } static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) { … } /** * gmc_v8_0_init_microcode - load ucode images from disk * * @adev: amdgpu_device pointer * * Use the firmware interface to load the ucode images into * the driver (not loaded into hw). * Returns 0 on success, error on failure. */ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) { … } /** * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw * * @adev: amdgpu_device pointer * * Load the GDDR MC ucode into the hw (VI). * Returns 0 on success, error on failure. */ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) { … } static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) { … } static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) { … } /** * gmc_v8_0_mc_program - program the GPU memory controller * * @adev: amdgpu_device pointer * * Set the location of vram, gart, and AGP in the GPU's * physical address space (VI). */ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) { … } /** * gmc_v8_0_mc_init - initialize the memory controller driver params * * @adev: amdgpu_device pointer * * Look up the amount of vram, vram width, and decide how to place * vram and gart within the GPU's physical address space (VI). * Returns 0 for success. */ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) { … } /** * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid * * @adev: amdgpu_device pointer * @pasid: pasid to be flush * @flush_type: type of flush * @all_hub: flush all hubs * @inst: is used to select which instance of KIQ to use for the invalidation * * Flush the TLB for the requested pasid. */ static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) { … } /* * GART * VMID 0 is the physical GPU addresses as used by the kernel. * VMIDs 1-15 are used for userspace clients and are handled * by the amdgpu vm/hsa code. */ /** * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback * * @adev: amdgpu_device pointer * @vmid: vm instance to flush * @vmhub: which hub to flush * @flush_type: type of flush * * Flush the TLB for the requested page table (VI). */ static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, uint32_t vmhub, uint32_t flush_type) { … } static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) { … } static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) { … } /* * PTE format on VI: * 63:40 reserved * 39:12 4k physical page base address * 11:7 fragment * 6 write * 5 read * 4 exe * 3 reserved * 2 snooped * 1 system * 0 valid * * PDE format on VI: * 63:59 block fragment size * 58:40 reserved * 39:1 physical base address of PTE * bits 5:1 must be 0. * 0 valid */ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { … } static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping, uint64_t *flags) { … } /** * gmc_v8_0_set_fault_enable_default - update VM fault handling * * @adev: amdgpu_device pointer * @value: true redirects VM faults to the default page */ static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) { … } /** * gmc_v8_0_set_prt() - set PRT VM fault * * @adev: amdgpu_device pointer * @enable: enable/disable VM fault handling for PRT */ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) { … } /** * gmc_v8_0_gart_enable - gart enable * * @adev: amdgpu_device pointer * * This sets up the TLBs, programs the page tables for VMID0, * sets up the hw for VMIDs 1-15 which are allocated on * demand, and sets up the global locations for the LDS, GDS, * and GPUVM for FSA64 clients (VI). * Returns 0 for success, errors for failure. */ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) { … } static int gmc_v8_0_gart_init(struct amdgpu_device *adev) { … } /** * gmc_v8_0_gart_disable - gart disable * * @adev: amdgpu_device pointer * * This disables all VM page table (VI). */ static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) { … } /** * gmc_v8_0_vm_decode_fault - print human readable fault info * * @adev: amdgpu_device pointer * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value * @pasid: debug logging only - no functional use * * Print human readable fault information (VI). */ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client, unsigned int pasid) { … } static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) { … } static int gmc_v8_0_early_init(void *handle) { … } static int gmc_v8_0_late_init(void *handle) { … } static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) { … } #define mmMC_SEQ_MISC0_FIJI … static int gmc_v8_0_sw_init(void *handle) { … } static int gmc_v8_0_sw_fini(void *handle) { … } static int gmc_v8_0_hw_init(void *handle) { … } static int gmc_v8_0_hw_fini(void *handle) { … } static int gmc_v8_0_suspend(void *handle) { … } static int gmc_v8_0_resume(void *handle) { … } static bool gmc_v8_0_is_idle(void *handle) { … } static int gmc_v8_0_wait_for_idle(void *handle) { … } static bool gmc_v8_0_check_soft_reset(void *handle) { … } static int gmc_v8_0_pre_soft_reset(void *handle) { … } static int gmc_v8_0_soft_reset(void *handle) { … } static int gmc_v8_0_post_soft_reset(void *handle) { … } static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) { … } static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, bool enable) { … } static int gmc_v8_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int gmc_v8_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags) { … } static const struct amd_ip_funcs gmc_v8_0_ip_funcs = …; static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = …; static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = …; static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) { … } static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version gmc_v8_0_ip_block = …; const struct amdgpu_ip_block_version gmc_v8_1_ip_block = …; const struct amdgpu_ip_block_version gmc_v8_5_ip_block = …;
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