linux/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h

/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef _nbio_7_0_SMN_HEADER
#define _nbio_7_0_SMN_HEADER


#define smnCPM_CONTROL …
#define smnPCIE_CNTL2 …

#define smnPCIE_PERF_COUNT_CNTL …
#define smnPCIE_PERF_CNTL_TXCLK …
#define smnPCIE_PERF_COUNT0_TXCLK …
#define smnPCIE_PERF_COUNT1_TXCLK …
#define smnPCIE_PERF_CNTL_MST_R_CLK …
#define smnPCIE_PERF_COUNT0_MST_R_CLK …
#define smnPCIE_PERF_COUNT1_MST_R_CLK …
#define smnPCIE_PERF_CNTL_MST_C_CLK …
#define smnPCIE_PERF_COUNT0_MST_C_CLK …
#define smnPCIE_PERF_COUNT1_MST_C_CLK …
#define smnPCIE_PERF_CNTL_SLV_R_CLK …
#define smnPCIE_PERF_COUNT0_SLV_R_CLK …
#define smnPCIE_PERF_COUNT1_SLV_R_CLK …
#define smnPCIE_PERF_CNTL_SLV_S_C_CLK …
#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK …
#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK …
#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK …
#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK …
#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK …
#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL …
#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL …
#define smnPCIE_PERF_CNTL_TXCLK2 …
#define smnPCIE_PERF_COUNT0_TXCLK2 …
#define smnPCIE_PERF_COUNT1_TXCLK2 …
#define smnPCIE_PERF_CNTL_TXCLK3 …
#define smnPCIE_PERF_COUNT0_TXCLK3 …
#define smnPCIE_PERF_COUNT1_TXCLK3 …
#define smnPCIE_PERF_CNTL_TXCLK4 …
#define smnPCIE_PERF_COUNT0_TXCLK4 …
#define smnPCIE_PERF_COUNT1_TXCLK4 …

#define smnPCIE_RX_NUM_NAK …
#define smnPCIE_RX_NUM_NAK_GENERATED …

#endif	// _nbio_7_0_SMN_HEADER