linux/drivers/gpu/drm/amd/amdgpu/soc15.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <drm/amdgpu_drm.h>

#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "amdgpu_ih.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_ucode.h"
#include "amdgpu_psp.h"
#include "atom.h"
#include "amd_pcie.h"

#include "uvd/uvd_7_0_offset.h"
#include "gc/gc_9_0_offset.h"
#include "gc/gc_9_0_sh_mask.h"
#include "sdma0/sdma0_4_0_offset.h"
#include "sdma1/sdma1_4_0_offset.h"
#include "nbio/nbio_7_0_default.h"
#include "nbio/nbio_7_0_offset.h"
#include "nbio/nbio_7_0_sh_mask.h"
#include "nbio/nbio_7_0_smn.h"
#include "mp/mp_9_0_offset.h"

#include "soc15.h"
#include "soc15_common.h"
#include "gfx_v9_0.h"
#include "gmc_v9_0.h"
#include "gfxhub_v1_0.h"
#include "mmhub_v1_0.h"
#include "df_v1_7.h"
#include "df_v3_6.h"
#include "nbio_v6_1.h"
#include "nbio_v7_0.h"
#include "nbio_v7_4.h"
#include "hdp_v4_0.h"
#include "vega10_ih.h"
#include "vega20_ih.h"
#include "navi10_ih.h"
#include "sdma_v4_0.h"
#include "uvd_v7_0.h"
#include "vce_v4_0.h"
#include "vcn_v1_0.h"
#include "vcn_v2_0.h"
#include "jpeg_v2_0.h"
#include "vcn_v2_5.h"
#include "jpeg_v2_5.h"
#include "smuio_v9_0.h"
#include "smuio_v11_0.h"
#include "smuio_v13_0.h"
#include "amdgpu_vkms.h"
#include "mxgpu_ai.h"
#include "amdgpu_ras.h"
#include "amdgpu_xgmi.h"
#include <uapi/linux/kfd_ioctl.h>

#define mmMP0_MISC_CGTT_CTRL0 …
#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX …
#define mmMP0_MISC_LIGHT_SLEEP_CTRL …
#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX …

static const struct amd_ip_funcs soc15_common_ip_funcs;

/* Vega, Raven, Arcturus */
static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = …;

static const struct amdgpu_video_codecs vega_video_codecs_encode = …;

/* Vega */
static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs vega_video_codecs_decode = …;

/* Raven */
static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs rv_video_codecs_decode = …;

/* Renoir, Arcturus */
static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs rn_video_codecs_decode = …;

static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = …;

static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = …;

static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
				    const struct amdgpu_video_codecs **codecs)
{ … }

static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
{ … }

static u32 soc15_get_xclk(struct amdgpu_device *adev)
{ … }


void soc15_grbm_select(struct amdgpu_device *adev,
		     u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
{ … }

static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
{ … }

static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = …;

static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
					 u32 sh_num, u32 reg_offset)
{ … }

static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
					 bool indexed, u32 se_num,
					 u32 sh_num, u32 reg_offset)
{ … }

static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
			    u32 sh_num, u32 reg_offset, u32 *value)
{ … }


/**
 * soc15_program_register_sequence - program an array of registers.
 *
 * @adev: amdgpu_device pointer
 * @regs: pointer to the register array
 * @array_size: size of the register array
 *
 * Programs an array or registers with and and or masks.
 * This is a helper for setting golden registers.
 */

void soc15_program_register_sequence(struct amdgpu_device *adev,
					     const struct soc15_reg_golden *regs,
					     const u32 array_size)
{ … }

static int soc15_asic_baco_reset(struct amdgpu_device *adev)
{ … }

static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device *adev)
{ … }

static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
{ … }

static int soc15_asic_reset(struct amdgpu_device *adev)
{ … }

static int soc15_supports_baco(struct amdgpu_device *adev)
{ … }

/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
			u32 cntl_reg, u32 status_reg)
{
	return 0;
}*/

static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{ … }

static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
{ … }

static void soc15_program_aspm(struct amdgpu_device *adev)
{ … }

const struct amdgpu_ip_block_version vega10_common_ip_block = …;

static void soc15_reg_base_init(struct amdgpu_device *adev)
{ … }

void soc15_set_virt_ops(struct amdgpu_device *adev)
{ … }

static bool soc15_need_full_reset(struct amdgpu_device *adev)
{ … }

static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
				 uint64_t *count1)
{ … }

static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
				 uint64_t *count1)
{ … }

static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
{ … }

static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
{ … }

static void soc15_pre_asic_init(struct amdgpu_device *adev)
{ … }

static const struct amdgpu_asic_funcs soc15_asic_funcs = …;

static const struct amdgpu_asic_funcs vega20_asic_funcs = …;

static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = …;

static int soc15_common_early_init(void *handle)
{ … }

static int soc15_common_late_init(void *handle)
{ … }

static int soc15_common_sw_init(void *handle)
{ … }

static int soc15_common_sw_fini(void *handle)
{ … }

static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
{ … }

static int soc15_common_hw_init(void *handle)
{ … }

static int soc15_common_hw_fini(void *handle)
{ … }

static int soc15_common_suspend(void *handle)
{ … }

static int soc15_common_resume(void *handle)
{ … }

static bool soc15_common_is_idle(void *handle)
{ … }

static int soc15_common_wait_for_idle(void *handle)
{ … }

static int soc15_common_soft_reset(void *handle)
{ … }

static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
{ … }

static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
{ … }

static int soc15_common_set_clockgating_state(void *handle,
					    enum amd_clockgating_state state)
{ … }

static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
{ … }

static int soc15_common_set_powergating_state(void *handle,
					    enum amd_powergating_state state)
{ … }

static const struct amd_ip_funcs soc15_common_ip_funcs = …;