/* SPDX-License-Identifier: GPL-2.0 */ /* * Low-Level PCI Access for i386 machines. * * (c) 1999 Martin Mares <[email protected]> */ #include <linux/errno.h> #include <linux/init.h> #include <linux/ioport.h> #include <linux/spinlock.h> #undef DEBUG #ifdef DEBUG #define DBG … #else #define DBG(fmt, ...) … #endif #define PCI_PROBE_BIOS … #define PCI_PROBE_CONF1 … #define PCI_PROBE_CONF2 … #define PCI_PROBE_MMCONF … #define PCI_PROBE_MASK … #define PCI_PROBE_NOEARLY … #define PCI_NO_CHECKS … #define PCI_USE_PIRQ_MASK … #define PCI_ASSIGN_ROMS … #define PCI_BIOS_IRQ_SCAN … #define PCI_ASSIGN_ALL_BUSSES … #define PCI_CAN_SKIP_ISA_ALIGN … #define PCI_USE__CRS … #define PCI_CHECK_ENABLE_AMD_MMCONF … #define PCI_HAS_IO_ECS … #define PCI_NOASSIGN_ROMS … #define PCI_ROOT_NO_CRS … #define PCI_NOASSIGN_BARS … #define PCI_BIG_ROOT_WINDOW … #define PCI_USE_E820 … #define PCI_NO_E820 … extern unsigned int pci_probe; extern unsigned long pirq_table_addr; enum pci_bf_sort_state { … }; /* pci-i386.c */ void pcibios_resource_survey(void); void pcibios_set_cache_line_size(void); /* pci-pc.c */ extern int pcibios_last_bus; extern struct pci_ops pci_root_ops; void pcibios_scan_specific_bus(int busn); /* pci-irq.c */ struct pci_dev; struct irq_info { … } __attribute__((packed)); struct irq_routing_table { … } __attribute__((packed)); struct irt_routing_table { … } __attribute__((packed)); extern unsigned int pcibios_irq_mask; extern raw_spinlock_t pci_config_lock; extern int (*pcibios_enable_irq)(struct pci_dev *dev); extern void (*pcibios_disable_irq)(struct pci_dev *dev); extern bool mp_should_keep_irq(struct device *dev); struct pci_raw_ops { … }; extern const struct pci_raw_ops *raw_pci_ops; extern const struct pci_raw_ops *raw_pci_ext_ops; extern const struct pci_raw_ops pci_mmcfg; extern const struct pci_raw_ops pci_direct_conf1; extern bool port_cf9_safe; /* arch_initcall level */ #ifdef CONFIG_PCI_DIRECT extern int pci_direct_probe(void); extern void pci_direct_init(int type); #else static inline int pci_direct_probe(void) { return -1; } static inline void pci_direct_init(int type) { } #endif #ifdef CONFIG_PCI_BIOS extern void pci_pcbios_init(void); #else static inline void pci_pcbios_init(void) { … } #endif extern void __init dmi_check_pciprobe(void); extern void __init dmi_check_skip_isa_align(void); /* some common used subsys_initcalls */ #ifdef CONFIG_PCI extern int __init pci_acpi_init(void); #else static inline int __init pci_acpi_init(void) { return -EINVAL; } #endif extern void __init pcibios_irq_init(void); extern int __init pcibios_init(void); extern int pci_legacy_init(void); extern void pcibios_fixup_irqs(void); /* pci-mmconfig.c */ /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ #define PCI_MMCFG_RESOURCE_NAME_LEN … struct pci_mmcfg_region { … }; extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, phys_addr_t addr); extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, int end, u64 addr); extern struct list_head pci_mmcfg_list; #define PCI_MMCFG_BUS_OFFSET(bus) … /* * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use * %eax. No other source or target registers may be used. The following * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1, * "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) { … } static inline unsigned short mmio_config_readw(void __iomem *pos) { … } static inline unsigned int mmio_config_readl(void __iomem *pos) { … } static inline void mmio_config_writeb(void __iomem *pos, u8 val) { … } static inline void mmio_config_writew(void __iomem *pos, u16 val) { … } static inline void mmio_config_writel(void __iomem *pos, u32 val) { … } #ifdef CONFIG_PCI # ifdef CONFIG_ACPI #define x86_default_pci_init … # else #define x86_default_pci_init … # endif #define x86_default_pci_init_irq … #define x86_default_pci_fixup_irqs … #else #define x86_default_pci_init … #define x86_default_pci_init_irq … #define x86_default_pci_fixup_irqs … #endif #if defined(CONFIG_PCI) && defined(CONFIG_ACPI) extern bool pci_use_e820; #else #define pci_use_e820 … #endif
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