linux/arch/x86/include/asm/amd_nb.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_AMD_NB_H
#define _ASM_X86_AMD_NB_H

#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/refcount.h>

struct amd_nb_bus_dev_range { … };

extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];

extern bool early_is_amd_nb(u32 value);
extern struct resource *amd_get_mmconfig_range(struct resource *res);
extern void amd_flush_garts(void);
extern int amd_numa_init(void);
extern int amd_get_subcaches(int);
extern int amd_set_subcaches(int, unsigned long);

int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
int __must_check amd_smn_write(u16 node, u32 address, u32 value);

struct amd_l3_cache { … };

struct threshold_block { … };

struct threshold_bank { … };

struct amd_northbridge { … };

struct amd_northbridge_info { … };

#define AMD_NB_GART …
#define AMD_NB_L3_INDEX_DISABLE …
#define AMD_NB_L3_PARTITIONING …

#ifdef CONFIG_AMD_NB

u16 amd_nb_num(void);
bool amd_nb_has_feature(unsigned int feature);
struct amd_northbridge *node_to_amd_nb(int node);

static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
{ … }

static inline bool amd_gart_present(void)
{ … }

#else

#define amd_nb_num …
#define amd_nb_has_feature …
#define node_to_amd_nb …
#define amd_gart_present …

#endif


#endif /* _ASM_X86_AMD_NB_H */