/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _mmhub_1_0_OFFSET_HEADER #define _mmhub_1_0_OFFSET_HEADER // addressBlock: mmhub_dagbdec // base address: 0x68000 #define mmDAGB0_RDCLI0 … #define mmDAGB0_RDCLI0_BASE_IDX … #define mmDAGB0_RDCLI1 … #define mmDAGB0_RDCLI1_BASE_IDX … #define mmDAGB0_RDCLI2 … #define mmDAGB0_RDCLI2_BASE_IDX … #define mmDAGB0_RDCLI3 … #define mmDAGB0_RDCLI3_BASE_IDX … #define mmDAGB0_RDCLI4 … #define mmDAGB0_RDCLI4_BASE_IDX … #define mmDAGB0_RDCLI5 … #define mmDAGB0_RDCLI5_BASE_IDX … #define mmDAGB0_RDCLI6 … #define mmDAGB0_RDCLI6_BASE_IDX … #define mmDAGB0_RDCLI7 … #define mmDAGB0_RDCLI7_BASE_IDX … #define mmDAGB0_RDCLI8 … #define mmDAGB0_RDCLI8_BASE_IDX … #define mmDAGB0_RDCLI9 … #define mmDAGB0_RDCLI9_BASE_IDX … #define mmDAGB0_RDCLI10 … #define mmDAGB0_RDCLI10_BASE_IDX … #define mmDAGB0_RDCLI11 … #define mmDAGB0_RDCLI11_BASE_IDX … #define mmDAGB0_RDCLI12 … #define mmDAGB0_RDCLI12_BASE_IDX … #define mmDAGB0_RDCLI13 … #define mmDAGB0_RDCLI13_BASE_IDX … #define mmDAGB0_RDCLI14 … #define mmDAGB0_RDCLI14_BASE_IDX … #define mmDAGB0_RDCLI15 … #define mmDAGB0_RDCLI15_BASE_IDX … #define mmDAGB0_RD_CNTL … #define mmDAGB0_RD_CNTL_BASE_IDX … #define mmDAGB0_RD_GMI_CNTL … #define mmDAGB0_RD_GMI_CNTL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB … #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_RD_CGTT_CLK_CTRL … #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_RD_VC0_CNTL … #define mmDAGB0_RD_VC0_CNTL_BASE_IDX … #define mmDAGB0_RD_VC1_CNTL … #define mmDAGB0_RD_VC1_CNTL_BASE_IDX … #define mmDAGB0_RD_VC2_CNTL … #define mmDAGB0_RD_VC2_CNTL_BASE_IDX … #define mmDAGB0_RD_VC3_CNTL … #define mmDAGB0_RD_VC3_CNTL_BASE_IDX … #define mmDAGB0_RD_VC4_CNTL … #define mmDAGB0_RD_VC4_CNTL_BASE_IDX … #define mmDAGB0_RD_VC5_CNTL … #define mmDAGB0_RD_VC5_CNTL_BASE_IDX … #define mmDAGB0_RD_VC6_CNTL … #define mmDAGB0_RD_VC6_CNTL_BASE_IDX … #define mmDAGB0_RD_VC7_CNTL … #define mmDAGB0_RD_VC7_CNTL_BASE_IDX … #define mmDAGB0_RD_CNTL_MISC … #define mmDAGB0_RD_CNTL_MISC_BASE_IDX … #define mmDAGB0_RD_TLB_CREDIT … #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB0_RDCLI_ASK_PENDING … #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GO_PENDING … #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GBLSEND_PENDING … #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_TLB_PENDING … #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OARB_PENDING … #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OSD_PENDING … #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI0 … #define mmDAGB0_WRCLI0_BASE_IDX … #define mmDAGB0_WRCLI1 … #define mmDAGB0_WRCLI1_BASE_IDX … #define mmDAGB0_WRCLI2 … #define mmDAGB0_WRCLI2_BASE_IDX … #define mmDAGB0_WRCLI3 … #define mmDAGB0_WRCLI3_BASE_IDX … #define mmDAGB0_WRCLI4 … #define mmDAGB0_WRCLI4_BASE_IDX … #define mmDAGB0_WRCLI5 … #define mmDAGB0_WRCLI5_BASE_IDX … #define mmDAGB0_WRCLI6 … #define mmDAGB0_WRCLI6_BASE_IDX … #define mmDAGB0_WRCLI7 … #define mmDAGB0_WRCLI7_BASE_IDX … #define mmDAGB0_WRCLI8 … #define mmDAGB0_WRCLI8_BASE_IDX … #define mmDAGB0_WRCLI9 … #define mmDAGB0_WRCLI9_BASE_IDX … #define mmDAGB0_WRCLI10 … #define mmDAGB0_WRCLI10_BASE_IDX … #define mmDAGB0_WRCLI11 … #define mmDAGB0_WRCLI11_BASE_IDX … #define mmDAGB0_WRCLI12 … #define mmDAGB0_WRCLI12_BASE_IDX … #define mmDAGB0_WRCLI13 … #define mmDAGB0_WRCLI13_BASE_IDX … #define mmDAGB0_WRCLI14 … #define mmDAGB0_WRCLI14_BASE_IDX … #define mmDAGB0_WRCLI15 … #define mmDAGB0_WRCLI15_BASE_IDX … #define mmDAGB0_WR_CNTL … #define mmDAGB0_WR_CNTL_BASE_IDX … #define mmDAGB0_WR_GMI_CNTL … #define mmDAGB0_WR_GMI_CNTL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB … #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_WR_CGTT_CLK_CTRL … #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB … #define mmDAGB0_WR_DATA_DAGB_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_VC0_CNTL … #define mmDAGB0_WR_VC0_CNTL_BASE_IDX … #define mmDAGB0_WR_VC1_CNTL … #define mmDAGB0_WR_VC1_CNTL_BASE_IDX … #define mmDAGB0_WR_VC2_CNTL … #define mmDAGB0_WR_VC2_CNTL_BASE_IDX … #define mmDAGB0_WR_VC3_CNTL … #define mmDAGB0_WR_VC3_CNTL_BASE_IDX … #define mmDAGB0_WR_VC4_CNTL … #define mmDAGB0_WR_VC4_CNTL_BASE_IDX … #define mmDAGB0_WR_VC5_CNTL … #define mmDAGB0_WR_VC5_CNTL_BASE_IDX … #define mmDAGB0_WR_VC6_CNTL … #define mmDAGB0_WR_VC6_CNTL_BASE_IDX … #define mmDAGB0_WR_VC7_CNTL … #define mmDAGB0_WR_VC7_CNTL_BASE_IDX … #define mmDAGB0_WR_CNTL_MISC … #define mmDAGB0_WR_CNTL_MISC_BASE_IDX … #define mmDAGB0_WR_TLB_CREDIT … #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB0_WR_DATA_CREDIT … #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB0_WR_MISC_CREDIT … #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB0_WRCLI_ASK_PENDING … #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GO_PENDING … #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GBLSEND_PENDING … #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_TLB_PENDING … #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OARB_PENDING … #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OSD_PENDING … #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_GO_PENDING … #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB0_DAGB_DLY … #define mmDAGB0_DAGB_DLY_BASE_IDX … #define mmDAGB0_CNTL_MISC … #define mmDAGB0_CNTL_MISC_BASE_IDX … #define mmDAGB0_CNTL_MISC2 … #define mmDAGB0_CNTL_MISC2_BASE_IDX … #define mmDAGB0_FIFO_EMPTY … #define mmDAGB0_FIFO_EMPTY_BASE_IDX … #define mmDAGB0_FIFO_FULL … #define mmDAGB0_FIFO_FULL_BASE_IDX … #define mmDAGB0_WR_CREDITS_FULL … #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB0_RD_CREDITS_FULL … #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB0_PERFCOUNTER_LO … #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB0_PERFCOUNTER_HI … #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB0_PERFCOUNTER0_CFG … #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER1_CFG … #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER2_CFG … #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB0_RESERVE0 … #define mmDAGB0_RESERVE0_BASE_IDX … #define mmDAGB0_RESERVE1 … #define mmDAGB0_RESERVE1_BASE_IDX … #define mmDAGB0_RESERVE2 … #define mmDAGB0_RESERVE2_BASE_IDX … #define mmDAGB0_RESERVE3 … #define mmDAGB0_RESERVE3_BASE_IDX … #define mmDAGB0_RESERVE4 … #define mmDAGB0_RESERVE4_BASE_IDX … #define mmDAGB0_RESERVE5 … #define mmDAGB0_RESERVE5_BASE_IDX … #define mmDAGB0_RESERVE6 … #define mmDAGB0_RESERVE6_BASE_IDX … #define mmDAGB0_RESERVE7 … #define mmDAGB0_RESERVE7_BASE_IDX … #define mmDAGB0_RESERVE8 … #define mmDAGB0_RESERVE8_BASE_IDX … #define mmDAGB0_RESERVE9 … #define mmDAGB0_RESERVE9_BASE_IDX … #define mmDAGB0_RESERVE10 … #define mmDAGB0_RESERVE10_BASE_IDX … #define mmDAGB0_RESERVE11 … #define mmDAGB0_RESERVE11_BASE_IDX … #define mmDAGB0_RESERVE12 … #define mmDAGB0_RESERVE12_BASE_IDX … #define mmDAGB0_RESERVE13 … #define mmDAGB0_RESERVE13_BASE_IDX … #define mmDAGB0_RESERVE14 … #define mmDAGB0_RESERVE14_BASE_IDX … #define mmDAGB0_RESERVE15 … #define mmDAGB0_RESERVE15_BASE_IDX … #define mmDAGB0_RESERVE16 … #define mmDAGB0_RESERVE16_BASE_IDX … #define mmDAGB0_RESERVE17 … #define mmDAGB0_RESERVE17_BASE_IDX … #define mmDAGB1_RDCLI0 … #define mmDAGB1_RDCLI0_BASE_IDX … #define mmDAGB1_RDCLI1 … #define mmDAGB1_RDCLI1_BASE_IDX … #define mmDAGB1_RDCLI2 … #define mmDAGB1_RDCLI2_BASE_IDX … #define mmDAGB1_RDCLI3 … #define mmDAGB1_RDCLI3_BASE_IDX … #define mmDAGB1_RDCLI4 … #define mmDAGB1_RDCLI4_BASE_IDX … #define mmDAGB1_RDCLI5 … #define mmDAGB1_RDCLI5_BASE_IDX … #define mmDAGB1_RDCLI6 … #define mmDAGB1_RDCLI6_BASE_IDX … #define mmDAGB1_RDCLI7 … #define mmDAGB1_RDCLI7_BASE_IDX … #define mmDAGB1_RDCLI8 … #define mmDAGB1_RDCLI8_BASE_IDX … #define mmDAGB1_RDCLI9 … #define mmDAGB1_RDCLI9_BASE_IDX … #define mmDAGB1_RDCLI10 … #define mmDAGB1_RDCLI10_BASE_IDX … #define mmDAGB1_RDCLI11 … #define mmDAGB1_RDCLI11_BASE_IDX … #define mmDAGB1_RDCLI12 … #define mmDAGB1_RDCLI12_BASE_IDX … #define mmDAGB1_RDCLI13 … #define mmDAGB1_RDCLI13_BASE_IDX … #define mmDAGB1_RDCLI14 … #define mmDAGB1_RDCLI14_BASE_IDX … #define mmDAGB1_RDCLI15 … #define mmDAGB1_RDCLI15_BASE_IDX … #define mmDAGB1_RD_CNTL … #define mmDAGB1_RD_CNTL_BASE_IDX … #define mmDAGB1_RD_GMI_CNTL … #define mmDAGB1_RD_GMI_CNTL_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB … #define mmDAGB1_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB1_RD_CGTT_CLK_CTRL … #define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_RD_VC0_CNTL … #define mmDAGB1_RD_VC0_CNTL_BASE_IDX … #define mmDAGB1_RD_VC1_CNTL … #define mmDAGB1_RD_VC1_CNTL_BASE_IDX … #define mmDAGB1_RD_VC2_CNTL … #define mmDAGB1_RD_VC2_CNTL_BASE_IDX … #define mmDAGB1_RD_VC3_CNTL … #define mmDAGB1_RD_VC3_CNTL_BASE_IDX … #define mmDAGB1_RD_VC4_CNTL … #define mmDAGB1_RD_VC4_CNTL_BASE_IDX … #define mmDAGB1_RD_VC5_CNTL … #define mmDAGB1_RD_VC5_CNTL_BASE_IDX … #define mmDAGB1_RD_VC6_CNTL … #define mmDAGB1_RD_VC6_CNTL_BASE_IDX … #define mmDAGB1_RD_VC7_CNTL … #define mmDAGB1_RD_VC7_CNTL_BASE_IDX … #define mmDAGB1_RD_CNTL_MISC … #define mmDAGB1_RD_CNTL_MISC_BASE_IDX … #define mmDAGB1_RD_TLB_CREDIT … #define mmDAGB1_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB1_RDCLI_ASK_PENDING … #define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_GO_PENDING … #define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_GBLSEND_PENDING … #define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_TLB_PENDING … #define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_OARB_PENDING … #define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_OSD_PENDING … #define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB1_WRCLI0 … #define mmDAGB1_WRCLI0_BASE_IDX … #define mmDAGB1_WRCLI1 … #define mmDAGB1_WRCLI1_BASE_IDX … #define mmDAGB1_WRCLI2 … #define mmDAGB1_WRCLI2_BASE_IDX … #define mmDAGB1_WRCLI3 … #define mmDAGB1_WRCLI3_BASE_IDX … #define mmDAGB1_WRCLI4 … #define mmDAGB1_WRCLI4_BASE_IDX … #define mmDAGB1_WRCLI5 … #define mmDAGB1_WRCLI5_BASE_IDX … #define mmDAGB1_WRCLI6 … #define mmDAGB1_WRCLI6_BASE_IDX … #define mmDAGB1_WRCLI7 … #define mmDAGB1_WRCLI7_BASE_IDX … #define mmDAGB1_WRCLI8 … #define mmDAGB1_WRCLI8_BASE_IDX … #define mmDAGB1_WRCLI9 … #define mmDAGB1_WRCLI9_BASE_IDX … #define mmDAGB1_WRCLI10 … #define mmDAGB1_WRCLI10_BASE_IDX … #define mmDAGB1_WRCLI11 … #define mmDAGB1_WRCLI11_BASE_IDX … #define mmDAGB1_WRCLI12 … #define mmDAGB1_WRCLI12_BASE_IDX … #define mmDAGB1_WRCLI13 … #define mmDAGB1_WRCLI13_BASE_IDX … #define mmDAGB1_WRCLI14 … #define mmDAGB1_WRCLI14_BASE_IDX … #define mmDAGB1_WRCLI15 … #define mmDAGB1_WRCLI15_BASE_IDX … #define mmDAGB1_WR_CNTL … #define mmDAGB1_WR_CNTL_BASE_IDX … #define mmDAGB1_WR_GMI_CNTL … #define mmDAGB1_WR_GMI_CNTL_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB … #define mmDAGB1_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB1_WR_CGTT_CLK_CTRL … #define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB … #define mmDAGB1_WR_DATA_DAGB_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_WR_VC0_CNTL … #define mmDAGB1_WR_VC0_CNTL_BASE_IDX … #define mmDAGB1_WR_VC1_CNTL … #define mmDAGB1_WR_VC1_CNTL_BASE_IDX … #define mmDAGB1_WR_VC2_CNTL … #define mmDAGB1_WR_VC2_CNTL_BASE_IDX … #define mmDAGB1_WR_VC3_CNTL … #define mmDAGB1_WR_VC3_CNTL_BASE_IDX … #define mmDAGB1_WR_VC4_CNTL … #define mmDAGB1_WR_VC4_CNTL_BASE_IDX … #define mmDAGB1_WR_VC5_CNTL … #define mmDAGB1_WR_VC5_CNTL_BASE_IDX … #define mmDAGB1_WR_VC6_CNTL … #define mmDAGB1_WR_VC6_CNTL_BASE_IDX … #define mmDAGB1_WR_VC7_CNTL … #define mmDAGB1_WR_VC7_CNTL_BASE_IDX … #define mmDAGB1_WR_CNTL_MISC … #define mmDAGB1_WR_CNTL_MISC_BASE_IDX … #define mmDAGB1_WR_TLB_CREDIT … #define mmDAGB1_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB1_WR_DATA_CREDIT … #define mmDAGB1_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB1_WR_MISC_CREDIT … #define mmDAGB1_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB1_WRCLI_ASK_PENDING … #define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_GO_PENDING … #define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_GBLSEND_PENDING … #define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_TLB_PENDING … #define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_OARB_PENDING … #define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_OSD_PENDING … #define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_DBUS_ASK_PENDING … #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_DBUS_GO_PENDING … #define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB1_DAGB_DLY … #define mmDAGB1_DAGB_DLY_BASE_IDX … #define mmDAGB1_CNTL_MISC … #define mmDAGB1_CNTL_MISC_BASE_IDX … #define mmDAGB1_CNTL_MISC2 … #define mmDAGB1_CNTL_MISC2_BASE_IDX … #define mmDAGB1_FIFO_EMPTY … #define mmDAGB1_FIFO_EMPTY_BASE_IDX … #define mmDAGB1_FIFO_FULL … #define mmDAGB1_FIFO_FULL_BASE_IDX … #define mmDAGB1_WR_CREDITS_FULL … #define mmDAGB1_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB1_RD_CREDITS_FULL … #define mmDAGB1_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB1_PERFCOUNTER_LO … #define mmDAGB1_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB1_PERFCOUNTER_HI … #define mmDAGB1_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB1_PERFCOUNTER0_CFG … #define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER1_CFG … #define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER2_CFG … #define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER_RSLT_CNTL … #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB1_RESERVE0 … #define mmDAGB1_RESERVE0_BASE_IDX … #define mmDAGB1_RESERVE1 … #define mmDAGB1_RESERVE1_BASE_IDX … #define mmDAGB1_RESERVE2 … #define mmDAGB1_RESERVE2_BASE_IDX … #define mmDAGB1_RESERVE3 … #define mmDAGB1_RESERVE3_BASE_IDX … #define mmDAGB1_RESERVE4 … #define mmDAGB1_RESERVE4_BASE_IDX … #define mmDAGB1_RESERVE5 … #define mmDAGB1_RESERVE5_BASE_IDX … #define mmDAGB1_RESERVE6 … #define mmDAGB1_RESERVE6_BASE_IDX … #define mmDAGB1_RESERVE7 … #define mmDAGB1_RESERVE7_BASE_IDX … #define mmDAGB1_RESERVE8 … #define mmDAGB1_RESERVE8_BASE_IDX … #define mmDAGB1_RESERVE9 … #define mmDAGB1_RESERVE9_BASE_IDX … #define mmDAGB1_RESERVE10 … #define mmDAGB1_RESERVE10_BASE_IDX … #define mmDAGB1_RESERVE11 … #define mmDAGB1_RESERVE11_BASE_IDX … #define mmDAGB1_RESERVE12 … #define mmDAGB1_RESERVE12_BASE_IDX … #define mmDAGB1_RESERVE13 … #define mmDAGB1_RESERVE13_BASE_IDX … #define mmDAGB1_RESERVE14 … #define mmDAGB1_RESERVE14_BASE_IDX … #define mmDAGB1_RESERVE15 … #define mmDAGB1_RESERVE15_BASE_IDX … #define mmDAGB1_RESERVE16 … #define mmDAGB1_RESERVE16_BASE_IDX … #define mmDAGB1_RESERVE17 … #define mmDAGB1_RESERVE17_BASE_IDX … // addressBlock: mmhub_ea_mmeadec // base address: 0x68400 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_RD_GRP2VC_MAP … #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_WR_GRP2VC_MAP … #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_RD_LAZY … #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA0_DRAM_WR_LAZY … #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA0_DRAM_RD_CAM_CNTL … #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_WR_CAM_CNTL … #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_PAGE_BURST … #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_AGE … #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_AGE … #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUEUING … #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUEUING … #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_FIXED … #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_FIXED … #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_URGENCY … #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_URGENCY … #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR0 … #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR1 … #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_HOLE_CNTL … #define mmMMEA0_ADDRNORM_HOLE_CNTL_BASE_IDX … #define mmMMEA0_ADDRDEC_BANK_CFG … #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA0_ADDRDEC_MISC_CFG … #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP0 … #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP1 … #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP0 … #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP1 … #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_RD_COMBINE_FLUSH … #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_WR_COMBINE_FLUSH … #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_GROUP_BURST … #define mmMMEA0_IO_GROUP_BURST_BASE_IDX … #define mmMMEA0_IO_RD_PRI_AGE … #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_WR_PRI_AGE … #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUEUING … #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUEUING … #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_RD_PRI_FIXED … #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_WR_PRI_FIXED … #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY … #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY … #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY_MASK … #define mmMMEA0_IO_RD_PRI_URGENCY_MASK_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY_MASK … #define mmMMEA0_IO_WR_PRI_URGENCY_MASK_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_SDP_ARB_DRAM … #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA0_SDP_ARB_FINAL … #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA0_SDP_DRAM_PRIORITY … #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_IO_PRIORITY … #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_CREDITS … #define mmMMEA0_SDP_CREDITS_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE0 … #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE1 … #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE0 … #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE1 … #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE0 … #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE1 … #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_REQ_CNTL … #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA0_MISC … #define mmMMEA0_MISC_BASE_IDX … #define mmMMEA0_LATENCY_SAMPLING … #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA0_PERFCOUNTER_LO … #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA0_PERFCOUNTER_HI … #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA0_PERFCOUNTER0_CFG … #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER1_CFG … #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA0_EDC_CNT … #define mmMMEA0_EDC_CNT_BASE_IDX … #define mmMMEA0_EDC_CNT2 … #define mmMMEA0_EDC_CNT2_BASE_IDX … #define mmMMEA0_DSM_CNTL … #define mmMMEA0_DSM_CNTL_BASE_IDX … #define mmMMEA0_DSM_CNTLA … #define mmMMEA0_DSM_CNTLA_BASE_IDX … #define mmMMEA0_DSM_CNTLB … #define mmMMEA0_DSM_CNTLB_BASE_IDX … #define mmMMEA0_DSM_CNTL2 … #define mmMMEA0_DSM_CNTL2_BASE_IDX … #define mmMMEA0_DSM_CNTL2A … #define mmMMEA0_DSM_CNTL2A_BASE_IDX … #define mmMMEA0_DSM_CNTL2B … #define mmMMEA0_DSM_CNTL2B_BASE_IDX … #define mmMMEA0_CGTT_CLK_CTRL … #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA0_EDC_MODE … #define mmMMEA0_EDC_MODE_BASE_IDX … #define mmMMEA0_ERR_STATUS … #define mmMMEA0_ERR_STATUS_BASE_IDX … #define mmMMEA0_MISC2 … #define mmMMEA0_MISC2_BASE_IDX … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_DRAM_RD_GRP2VC_MAP … #define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_DRAM_WR_GRP2VC_MAP … #define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_DRAM_RD_LAZY … #define mmMMEA1_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA1_DRAM_WR_LAZY … #define mmMMEA1_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA1_DRAM_RD_CAM_CNTL … #define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA1_DRAM_WR_CAM_CNTL … #define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA1_DRAM_PAGE_BURST … #define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_AGE … #define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_AGE … #define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUEUING … #define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUEUING … #define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_FIXED … #define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_FIXED … #define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_URGENCY … #define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_URGENCY … #define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR0 … #define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR1 … #define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_HOLE_CNTL … #define mmMMEA1_ADDRNORM_HOLE_CNTL_BASE_IDX … #define mmMMEA1_ADDRDEC_BANK_CFG … #define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA1_ADDRDEC_MISC_CFG … #define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA1_IO_RD_CLI2GRP_MAP0 … #define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_IO_RD_CLI2GRP_MAP1 … #define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_IO_WR_CLI2GRP_MAP0 … #define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_IO_WR_CLI2GRP_MAP1 … #define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_IO_RD_COMBINE_FLUSH … #define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA1_IO_WR_COMBINE_FLUSH … #define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA1_IO_GROUP_BURST … #define mmMMEA1_IO_GROUP_BURST_BASE_IDX … #define mmMMEA1_IO_RD_PRI_AGE … #define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA1_IO_WR_PRI_AGE … #define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUEUING … #define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUEUING … #define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA1_IO_RD_PRI_FIXED … #define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA1_IO_WR_PRI_FIXED … #define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA1_IO_RD_PRI_URGENCY … #define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA1_IO_WR_PRI_URGENCY … #define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA1_IO_RD_PRI_URGENCY_MASK … #define mmMMEA1_IO_RD_PRI_URGENCY_MASK_BASE_IDX … #define mmMMEA1_IO_WR_PRI_URGENCY_MASK … #define mmMMEA1_IO_WR_PRI_URGENCY_MASK_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_SDP_ARB_DRAM … #define mmMMEA1_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA1_SDP_ARB_FINAL … #define mmMMEA1_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA1_SDP_DRAM_PRIORITY … #define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA1_SDP_IO_PRIORITY … #define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA1_SDP_CREDITS … #define mmMMEA1_SDP_CREDITS_BASE_IDX … #define mmMMEA1_SDP_TAG_RESERVE0 … #define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_TAG_RESERVE1 … #define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_VCC_RESERVE0 … #define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_VCC_RESERVE1 … #define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_VCD_RESERVE0 … #define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_VCD_RESERVE1 … #define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_REQ_CNTL … #define mmMMEA1_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA1_MISC … #define mmMMEA1_MISC_BASE_IDX … #define mmMMEA1_LATENCY_SAMPLING … #define mmMMEA1_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA1_PERFCOUNTER_LO … #define mmMMEA1_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA1_PERFCOUNTER_HI … #define mmMMEA1_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA1_PERFCOUNTER0_CFG … #define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA1_PERFCOUNTER1_CFG … #define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA1_PERFCOUNTER_RSLT_CNTL … #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA1_EDC_CNT … #define mmMMEA1_EDC_CNT_BASE_IDX … #define mmMMEA1_EDC_CNT2 … #define mmMMEA1_EDC_CNT2_BASE_IDX … #define mmMMEA1_DSM_CNTL … #define mmMMEA1_DSM_CNTL_BASE_IDX … #define mmMMEA1_DSM_CNTLA … #define mmMMEA1_DSM_CNTLA_BASE_IDX … #define mmMMEA1_DSM_CNTLB … #define mmMMEA1_DSM_CNTLB_BASE_IDX … #define mmMMEA1_DSM_CNTL2 … #define mmMMEA1_DSM_CNTL2_BASE_IDX … #define mmMMEA1_DSM_CNTL2A … #define mmMMEA1_DSM_CNTL2A_BASE_IDX … #define mmMMEA1_DSM_CNTL2B … #define mmMMEA1_DSM_CNTL2B_BASE_IDX … #define mmMMEA1_CGTT_CLK_CTRL … #define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA1_EDC_MODE … #define mmMMEA1_EDC_MODE_BASE_IDX … #define mmMMEA1_ERR_STATUS … #define mmMMEA1_ERR_STATUS_BASE_IDX … #define mmMMEA1_MISC2 … #define mmMMEA1_MISC2_BASE_IDX … // addressBlock: mmhub_pctldec // base address: 0x68e00 #define mmPCTL_MISC … #define mmPCTL_MISC_BASE_IDX … #define mmPCTL_MMHUB_DEEPSLEEP … #define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define mmPCTL_PG_IGNORE_DEEPSLEEP … #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define mmPCTL_PG_DAGB … #define mmPCTL_PG_DAGB_BASE_IDX … #define mmPCTL0_RENG_RAM_INDEX … #define mmPCTL0_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_RENG_RAM_DATA … #define mmPCTL0_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_RENG_EXECUTE … #define mmPCTL0_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_MISC … #define mmPCTL0_MISC_BASE_IDX … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET … #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX … #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_RENG_RAM_INDEX … #define mmPCTL1_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_RENG_RAM_DATA … #define mmPCTL1_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_RENG_EXECUTE … #define mmPCTL1_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_MISC … #define mmPCTL1_MISC_BASE_IDX … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET … #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX … #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL2_RENG_RAM_INDEX … #define mmPCTL2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL2_RENG_RAM_DATA … #define mmPCTL2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL2_RENG_EXECUTE … #define mmPCTL2_RENG_EXECUTE_BASE_IDX … #define mmPCTL2_MISC … #define mmPCTL2_MISC_BASE_IDX … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET … #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX … #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1dec // base address: 0x69600 #define mmMC_VM_MX_L1_TLB0_STATUS … #define mmMC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB1_STATUS … #define mmMC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB2_STATUS … #define mmMC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB3_STATUS … #define mmMC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB4_STATUS … #define mmMC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB5_STATUS … #define mmMC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB6_STATUS … #define mmMC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define mmMC_VM_MX_L1_TLB7_STATUS … #define mmMC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1pldec // base address: 0x69650 #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG … #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG … #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG … #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG … #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1prdec // base address: 0x69670 #define mmMC_VM_MX_L1_PERFCOUNTER_LO … #define mmMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define mmMC_VM_MX_L1_PERFCOUNTER_HI … #define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2dec // base address: 0x69900 #define mmATC_L2_CNTL … #define mmATC_L2_CNTL_BASE_IDX … #define mmATC_L2_CNTL2 … #define mmATC_L2_CNTL2_BASE_IDX … #define mmATC_L2_CACHE_DATA0 … #define mmATC_L2_CACHE_DATA0_BASE_IDX … #define mmATC_L2_CACHE_DATA1 … #define mmATC_L2_CACHE_DATA1_BASE_IDX … #define mmATC_L2_CACHE_DATA2 … #define mmATC_L2_CACHE_DATA2_BASE_IDX … #define mmATC_L2_CNTL3 … #define mmATC_L2_CNTL3_BASE_IDX … #define mmATC_L2_STATUS … #define mmATC_L2_STATUS_BASE_IDX … #define mmATC_L2_STATUS2 … #define mmATC_L2_STATUS2_BASE_IDX … #define mmATC_L2_MISC_CG … #define mmATC_L2_MISC_CG_BASE_IDX … #define mmATC_L2_MEM_POWER_LS … #define mmATC_L2_MEM_POWER_LS_BASE_IDX … #define mmATC_L2_CGTT_CLK_CTRL … #define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pfdec // base address: 0x69a00 #define mmVM_L2_CNTL … #define mmVM_L2_CNTL_BASE_IDX … #define mmVM_L2_CNTL2 … #define mmVM_L2_CNTL2_BASE_IDX … #define mmVM_L2_CNTL3 … #define mmVM_L2_CNTL3_BASE_IDX … #define mmVM_L2_STATUS … #define mmVM_L2_STATUS_BASE_IDX … #define mmVM_DUMMY_PAGE_FAULT_CNTL … #define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_CNTL … #define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_CNTL2 … #define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_STATUS … #define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define mmVM_L2_CNTL4 … #define mmVM_L2_CNTL4_BASE_IDX … #define mmVM_L2_MM_GROUP_RT_CLASSES … #define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmVM_L2_BANK_SELECT_RESERVED_CID … #define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define mmVM_L2_BANK_SELECT_RESERVED_CID2 … #define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define mmVM_L2_CACHE_PARITY_CNTL … #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define mmVM_L2_CGTT_CLK_CTRL … #define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2vcdec // base address: 0x69b00 #define mmVM_CONTEXT0_CNTL … #define mmVM_CONTEXT0_CNTL_BASE_IDX … #define mmVM_CONTEXT1_CNTL … #define mmVM_CONTEXT1_CNTL_BASE_IDX … #define mmVM_CONTEXT2_CNTL … #define mmVM_CONTEXT2_CNTL_BASE_IDX … #define mmVM_CONTEXT3_CNTL … #define mmVM_CONTEXT3_CNTL_BASE_IDX … #define mmVM_CONTEXT4_CNTL … #define mmVM_CONTEXT4_CNTL_BASE_IDX … #define mmVM_CONTEXT5_CNTL … #define mmVM_CONTEXT5_CNTL_BASE_IDX … #define mmVM_CONTEXT6_CNTL … #define mmVM_CONTEXT6_CNTL_BASE_IDX … #define mmVM_CONTEXT7_CNTL … #define mmVM_CONTEXT7_CNTL_BASE_IDX … #define mmVM_CONTEXT8_CNTL … #define mmVM_CONTEXT8_CNTL_BASE_IDX … #define mmVM_CONTEXT9_CNTL … #define mmVM_CONTEXT9_CNTL_BASE_IDX … #define mmVM_CONTEXT10_CNTL … #define mmVM_CONTEXT10_CNTL_BASE_IDX … #define mmVM_CONTEXT11_CNTL … #define mmVM_CONTEXT11_CNTL_BASE_IDX … #define mmVM_CONTEXT12_CNTL … #define mmVM_CONTEXT12_CNTL_BASE_IDX … #define mmVM_CONTEXT13_CNTL … #define mmVM_CONTEXT13_CNTL_BASE_IDX … #define mmVM_CONTEXT14_CNTL … #define mmVM_CONTEXT14_CNTL_BASE_IDX … #define mmVM_CONTEXT15_CNTL … #define mmVM_CONTEXT15_CNTL_BASE_IDX … #define mmVM_CONTEXTS_DISABLE … #define mmVM_CONTEXTS_DISABLE_BASE_IDX … #define mmVM_INVALIDATE_ENG0_SEM … #define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG1_SEM … #define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG2_SEM … #define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG3_SEM … #define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG4_SEM … #define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG5_SEM … #define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG6_SEM … #define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG7_SEM … #define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG8_SEM … #define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG9_SEM … #define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG10_SEM … #define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG11_SEM … #define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG12_SEM … #define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG13_SEM … #define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG14_SEM … #define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG15_SEM … #define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG16_SEM … #define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG17_SEM … #define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define mmVM_INVALIDATE_ENG0_REQ … #define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG1_REQ … #define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG2_REQ … #define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG3_REQ … #define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG4_REQ … #define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG5_REQ … #define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG6_REQ … #define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG7_REQ … #define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG8_REQ … #define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG9_REQ … #define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG10_REQ … #define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG11_REQ … #define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG12_REQ … #define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG13_REQ … #define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG14_REQ … #define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG15_REQ … #define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG16_REQ … #define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG17_REQ … #define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define mmVM_INVALIDATE_ENG0_ACK … #define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG1_ACK … #define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG2_ACK … #define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG3_ACK … #define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG4_ACK … #define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG5_ACK … #define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG6_ACK … #define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG7_ACK … #define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG8_ACK … #define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG9_ACK … #define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG10_ACK … #define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG11_ACK … #define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG12_ACK … #define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG13_ACK … #define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG14_ACK … #define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG15_ACK … #define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG16_ACK … #define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG17_ACK … #define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pldec // base address: 0x69e90 #define mmMC_VM_L2_PERFCOUNTER0_CFG … #define mmMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER1_CFG … #define mmMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER2_CFG … #define mmMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER3_CFG … #define mmMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER4_CFG … #define mmMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER5_CFG … #define mmMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER6_CFG … #define mmMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER7_CFG … #define mmMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2prdec // base address: 0x69ee0 #define mmMC_VM_L2_PERFCOUNTER_LO … #define mmMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define mmMC_VM_L2_PERFCOUNTER_HI … #define mmMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedhvdec // base address: 0x69f30 #define mmMC_VM_FB_SIZE_OFFSET_VF0 … #define mmMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF1 … #define mmMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF2 … #define mmMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF3 … #define mmMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF4 … #define mmMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF5 … #define mmMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF6 … #define mmMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF7 … #define mmMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF8 … #define mmMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF9 … #define mmMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF10 … #define mmMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF11 … #define mmMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF12 … #define mmMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF13 … #define mmMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF14 … #define mmMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define mmMC_VM_FB_SIZE_OFFSET_VF15 … #define mmMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define mmVM_IOMMU_MMIO_CNTRL_1 … #define mmVM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define mmMC_VM_MARC_BASE_LO_0 … #define mmMC_VM_MARC_BASE_LO_0_BASE_IDX … #define mmMC_VM_MARC_BASE_LO_1 … #define mmMC_VM_MARC_BASE_LO_1_BASE_IDX … #define mmMC_VM_MARC_BASE_LO_2 … #define mmMC_VM_MARC_BASE_LO_2_BASE_IDX … #define mmMC_VM_MARC_BASE_LO_3 … #define mmMC_VM_MARC_BASE_LO_3_BASE_IDX … #define mmMC_VM_MARC_BASE_HI_0 … #define mmMC_VM_MARC_BASE_HI_0_BASE_IDX … #define mmMC_VM_MARC_BASE_HI_1 … #define mmMC_VM_MARC_BASE_HI_1_BASE_IDX … #define mmMC_VM_MARC_BASE_HI_2 … #define mmMC_VM_MARC_BASE_HI_2_BASE_IDX … #define mmMC_VM_MARC_BASE_HI_3 … #define mmMC_VM_MARC_BASE_HI_3_BASE_IDX … #define mmMC_VM_MARC_RELOC_LO_0 … #define mmMC_VM_MARC_RELOC_LO_0_BASE_IDX … #define mmMC_VM_MARC_RELOC_LO_1 … #define mmMC_VM_MARC_RELOC_LO_1_BASE_IDX … #define mmMC_VM_MARC_RELOC_LO_2 … #define mmMC_VM_MARC_RELOC_LO_2_BASE_IDX … #define mmMC_VM_MARC_RELOC_LO_3 … #define mmMC_VM_MARC_RELOC_LO_3_BASE_IDX … #define mmMC_VM_MARC_RELOC_HI_0 … #define mmMC_VM_MARC_RELOC_HI_0_BASE_IDX … #define mmMC_VM_MARC_RELOC_HI_1 … #define mmMC_VM_MARC_RELOC_HI_1_BASE_IDX … #define mmMC_VM_MARC_RELOC_HI_2 … #define mmMC_VM_MARC_RELOC_HI_2_BASE_IDX … #define mmMC_VM_MARC_RELOC_HI_3 … #define mmMC_VM_MARC_RELOC_HI_3_BASE_IDX … #define mmMC_VM_MARC_LEN_LO_0 … #define mmMC_VM_MARC_LEN_LO_0_BASE_IDX … #define mmMC_VM_MARC_LEN_LO_1 … #define mmMC_VM_MARC_LEN_LO_1_BASE_IDX … #define mmMC_VM_MARC_LEN_LO_2 … #define mmMC_VM_MARC_LEN_LO_2_BASE_IDX … #define mmMC_VM_MARC_LEN_LO_3 … #define mmMC_VM_MARC_LEN_LO_3_BASE_IDX … #define mmMC_VM_MARC_LEN_HI_0 … #define mmMC_VM_MARC_LEN_HI_0_BASE_IDX … #define mmMC_VM_MARC_LEN_HI_1 … #define mmMC_VM_MARC_LEN_HI_1_BASE_IDX … #define mmMC_VM_MARC_LEN_HI_2 … #define mmMC_VM_MARC_LEN_HI_2_BASE_IDX … #define mmMC_VM_MARC_LEN_HI_3 … #define mmMC_VM_MARC_LEN_HI_3_BASE_IDX … #define mmVM_IOMMU_CONTROL_REGISTER … #define mmVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define mmVM_PCIE_ATS_CNTL … #define mmVM_PCIE_ATS_CNTL_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_0 … #define mmVM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_1 … #define mmVM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_2 … #define mmVM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_3 … #define mmVM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_4 … #define mmVM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_5 … #define mmVM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_6 … #define mmVM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_7 … #define mmVM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_8 … #define mmVM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_9 … #define mmVM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_10 … #define mmVM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_11 … #define mmVM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_12 … #define mmVM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_13 … #define mmVM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_14 … #define mmVM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define mmVM_PCIE_ATS_CNTL_VF_15 … #define mmVM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define mmUTCL2_CGTT_CLK_CTRL … #define mmUTCL2_CGTT_CLK_CTRL_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6a040 #define mmMC_VM_NB_MMIOBASE … #define mmMC_VM_NB_MMIOBASE_BASE_IDX … #define mmMC_VM_NB_MMIOLIMIT … #define mmMC_VM_NB_MMIOLIMIT_BASE_IDX … #define mmMC_VM_NB_PCI_CTRL … #define mmMC_VM_NB_PCI_CTRL_BASE_IDX … #define mmMC_VM_NB_PCI_ARB … #define mmMC_VM_NB_PCI_ARB_BASE_IDX … #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define mmMC_VM_FB_OFFSET … #define mmMC_VM_FB_OFFSET_BASE_IDX … #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmMC_VM_STEERING … #define mmMC_VM_STEERING_BASE_IDX … #define mmMC_SHARED_VIRT_RESET_REQ … #define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define mmMC_MEM_POWER_LS … #define mmMC_MEM_POWER_LS_BASE_IDX … #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define mmMC_VM_APT_CNTL … #define mmMC_VM_APT_CNTL_BASE_IDX … #define mmMC_VM_LOCAL_HBM_ADDRESS_START … #define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define mmMC_VM_LOCAL_HBM_ADDRESS_END … #define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedvcdec // base address: 0x6a0b0 #define mmMC_VM_FB_LOCATION_BASE … #define mmMC_VM_FB_LOCATION_BASE_BASE_IDX … #define mmMC_VM_FB_LOCATION_TOP … #define mmMC_VM_FB_LOCATION_TOP_BASE_IDX … #define mmMC_VM_AGP_TOP … #define mmMC_VM_AGP_TOP_BASE_IDX … #define mmMC_VM_AGP_BOT … #define mmMC_VM_AGP_BOT_BASE_IDX … #define mmMC_VM_AGP_BASE … #define mmMC_VM_AGP_BASE_BASE_IDX … #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define mmMC_VM_MX_L1_TLB_CNTL … #define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntrdec // base address: 0x6a100 #define mmATC_L2_PERFCOUNTER_LO … #define mmATC_L2_PERFCOUNTER_LO_BASE_IDX … #define mmATC_L2_PERFCOUNTER_HI … #define mmATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntldec // base address: 0x6a120 #define mmATC_L2_PERFCOUNTER0_CFG … #define mmATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmATC_L2_PERFCOUNTER1_CFG … #define mmATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmATC_L2_PERFCOUNTER_RSLT_CNTL … #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … /* MMEA */ #define mmMMEA0_EDC_CNT_VG20 … #define mmMMEA0_EDC_CNT_VG20_BASE_IDX … #define mmMMEA0_EDC_CNT2_VG20 … #define mmMMEA0_EDC_CNT2_VG20_BASE_IDX … #define mmMMEA1_EDC_CNT_VG20 … #define mmMMEA1_EDC_CNT_VG20_BASE_IDX … #define mmMMEA1_EDC_CNT2_VG20 … #define mmMMEA1_EDC_CNT2_VG20_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6a040 #define mmMC_VM_XGMI_LFB_CNTL … #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX … #define mmMC_VM_XGMI_LFB_SIZE … #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX … #endif
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