/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _dce_12_0_OFFSET_HEADER #define _dce_12_0_OFFSET_HEADER // addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR // base address: 0x48 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR … #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … // addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR // base address: 0x4c #define mmdispdec_VGA_MEM_READ_PAGE_ADDR … #define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX … // addressBlock: dce_dc_dc_perfmon0_dispdec // base address: 0x0 #define mmDC_PERFMON0_PERFCOUNTER_CNTL … #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON0_PERFCOUNTER_STATE … #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CNTL … #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CNTL2 … #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CVALUE_LOW … #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON0_PERFMON_HI … #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON0_PERFMON_LOW … #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dc_perfmon13_dispdec // base address: 0x30 #define mmDC_PERFMON13_PERFCOUNTER_CNTL … #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON13_PERFCOUNTER_STATE … #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CNTL … #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CNTL2 … #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CVALUE_LOW … #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON13_PERFMON_HI … #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON13_PERFMON_LOW … #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dc_displaypllregs_dispdec // base address: 0x0 #define mmPPLL_VREG_CFG … #define mmPPLL_VREG_CFG_BASE_IDX … #define mmPPLL_MODE_CNTL … #define mmPPLL_MODE_CNTL_BASE_IDX … #define mmPPLL_FREQ_CTRL0 … #define mmPPLL_FREQ_CTRL0_BASE_IDX … #define mmPPLL_FREQ_CTRL1 … #define mmPPLL_FREQ_CTRL1_BASE_IDX … #define mmPPLL_FREQ_CTRL2 … #define mmPPLL_FREQ_CTRL2_BASE_IDX … #define mmPPLL_FREQ_CTRL3 … #define mmPPLL_FREQ_CTRL3_BASE_IDX … #define mmPPLL_BW_CTRL_COARSE … #define mmPPLL_BW_CTRL_COARSE_BASE_IDX … #define mmPPLL_BW_CTRL_FINE … #define mmPPLL_BW_CTRL_FINE_BASE_IDX … #define mmPPLL_CAL_CTRL … #define mmPPLL_CAL_CTRL_BASE_IDX … #define mmPPLL_LOOP_CTRL … #define mmPPLL_LOOP_CTRL_BASE_IDX … #define mmPPLL_REFCLK_CNTL … #define mmPPLL_REFCLK_CNTL_BASE_IDX … #define mmPPLL_CLKOUT_CNTL … #define mmPPLL_CLKOUT_CNTL_BASE_IDX … #define mmPPLL_DFT_CNTL … #define mmPPLL_DFT_CNTL_BASE_IDX … #define mmPPLL_ANALOG_CNTL … #define mmPPLL_ANALOG_CNTL_BASE_IDX … #define mmPPLL_POSTDIV … #define mmPPLL_POSTDIV_BASE_IDX … #define mmPPLL_OBSERVE0 … #define mmPPLL_OBSERVE0_BASE_IDX … #define mmPPLL_OBSERVE1 … #define mmPPLL_OBSERVE1_BASE_IDX … #define mmPPLL_UPDATE_CNTL … #define mmPPLL_UPDATE_CNTL_BASE_IDX … #define mmPPLL_OBSERVE0_OUT … #define mmPPLL_OBSERVE0_OUT_BASE_IDX … // addressBlock: dce_dc_dccg_pll0_dispdec // base address: 0x0 #define mmPLL_MACRO_CNTL_RESERVED0 … #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED1 … #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED2 … #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED3 … #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED4 … #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED5 … #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED6 … #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED7 … #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED8 … #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED9 … #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED10 … #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED11 … #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED12 … #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED13 … #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED14 … #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED15 … #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED16 … #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED17 … #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED18 … #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED19 … #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED20 … #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED21 … #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED22 … #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED23 … #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED24 … #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED25 … #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED26 … #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED27 … #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED28 … #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED29 … #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED30 … #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED31 … #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED32 … #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED33 … #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED34 … #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED35 … #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED36 … #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED37 … #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED38 … #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED39 … #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED40 … #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED41 … #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX … // addressBlock: dce_dc_dc_perfmon1_dispdec // base address: 0x598 #define mmDC_PERFMON1_PERFCOUNTER_CNTL … #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON1_PERFCOUNTER_STATE … #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CNTL … #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CNTL2 … #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CVALUE_LOW … #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON1_PERFMON_HI … #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON1_PERFMON_LOW … #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_mcif_wb0_dispdec // base address: 0x0 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_PITCH … #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE … #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_WATERMARK … #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL … #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL … #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL … #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL … #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE … #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE … #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … // addressBlock: dce_dc_mcif_wb1_dispdec // base address: 0x100 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_PITCH … #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE … #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_WATERMARK … #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL … #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL … #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL … #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL … #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE … #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE … #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … // addressBlock: dce_dc_mcif_wb2_dispdec // base address: 0x200 #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_PITCH … #define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE … #define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL … #define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_WATERMARK … #define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL … #define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL … #define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL … #define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL … #define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE … #define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE … #define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … // addressBlock: dce_dc_cwb0_dispdec // base address: 0x0 #define mmCWB0_CWB_CTRL … #define mmCWB0_CWB_CTRL_BASE_IDX … #define mmCWB0_CWB_FENCE_PAR0 … #define mmCWB0_CWB_FENCE_PAR0_BASE_IDX … #define mmCWB0_CWB_FENCE_PAR1 … #define mmCWB0_CWB_FENCE_PAR1_BASE_IDX … #define mmCWB0_CWB_CRC_CTRL … #define mmCWB0_CWB_CRC_CTRL_BASE_IDX … #define mmCWB0_CWB_CRC_RED_GREEN_MASK … #define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX … #define mmCWB0_CWB_CRC_BLUE_MASK … #define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX … #define mmCWB0_CWB_CRC_RED_GREEN_RESULT … #define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX … #define mmCWB0_CWB_CRC_BLUE_RESULT … #define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX … // addressBlock: dce_dc_cwb1_dispdec // base address: 0x60 #define mmCWB1_CWB_CTRL … #define mmCWB1_CWB_CTRL_BASE_IDX … #define mmCWB1_CWB_FENCE_PAR0 … #define mmCWB1_CWB_FENCE_PAR0_BASE_IDX … #define mmCWB1_CWB_FENCE_PAR1 … #define mmCWB1_CWB_FENCE_PAR1_BASE_IDX … #define mmCWB1_CWB_CRC_CTRL … #define mmCWB1_CWB_CRC_CTRL_BASE_IDX … #define mmCWB1_CWB_CRC_RED_GREEN_MASK … #define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX … #define mmCWB1_CWB_CRC_BLUE_MASK … #define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX … #define mmCWB1_CWB_CRC_RED_GREEN_RESULT … #define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX … #define mmCWB1_CWB_CRC_BLUE_RESULT … #define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX … // addressBlock: dce_dc_dc_perfmon9_dispdec // base address: 0xd08 #define mmDC_PERFMON9_PERFCOUNTER_CNTL … #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON9_PERFCOUNTER_STATE … #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CNTL … #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CNTL2 … #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CVALUE_LOW … #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON9_PERFMON_HI … #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON9_PERFMON_LOW … #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dispdec // base address: 0x0 #define mmVGA_MEM_WRITE_PAGE_ADDR … #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … #define mmVGA_MEM_READ_PAGE_ADDR … #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX … #define mmVGA_RENDER_CONTROL … #define mmVGA_RENDER_CONTROL_BASE_IDX … #define mmVGA_SEQUENCER_RESET_CONTROL … #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … #define mmVGA_MODE_CONTROL … #define mmVGA_MODE_CONTROL_BASE_IDX … #define mmVGA_SURFACE_PITCH_SELECT … #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX … #define mmVGA_MEMORY_BASE_ADDRESS … #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX … #define mmVGA_DISPBUF1_SURFACE_ADDR … #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … #define mmVGA_DISPBUF2_SURFACE_ADDR … #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX … #define mmVGA_MEMORY_BASE_ADDRESS_HIGH … #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX … #define mmVGA_HDP_CONTROL … #define mmVGA_HDP_CONTROL_BASE_IDX … #define mmVGA_CACHE_CONTROL … #define mmVGA_CACHE_CONTROL_BASE_IDX … #define mmD1VGA_CONTROL … #define mmD1VGA_CONTROL_BASE_IDX … #define mmD2VGA_CONTROL … #define mmD2VGA_CONTROL_BASE_IDX … #define mmVGA_STATUS … #define mmVGA_STATUS_BASE_IDX … #define mmVGA_INTERRUPT_CONTROL … #define mmVGA_INTERRUPT_CONTROL_BASE_IDX … #define mmVGA_STATUS_CLEAR … #define mmVGA_STATUS_CLEAR_BASE_IDX … #define mmVGA_INTERRUPT_STATUS … #define mmVGA_INTERRUPT_STATUS_BASE_IDX … #define mmVGA_MAIN_CONTROL … #define mmVGA_MAIN_CONTROL_BASE_IDX … #define mmVGA_TEST_CONTROL … #define mmVGA_TEST_CONTROL_BASE_IDX … #define mmVGA_QOS_CTRL … #define mmVGA_QOS_CTRL_BASE_IDX … #define mmCRTC8_IDX … #define mmCRTC8_IDX_BASE_IDX … #define mmCRTC8_DATA … #define mmCRTC8_DATA_BASE_IDX … #define mmGENFC_WT … #define mmGENFC_WT_BASE_IDX … #define mmGENS1 … #define mmGENS1_BASE_IDX … #define mmATTRDW … #define mmATTRDW_BASE_IDX … #define mmATTRX … #define mmATTRX_BASE_IDX … #define mmATTRDR … #define mmATTRDR_BASE_IDX … #define mmGENMO_WT … #define mmGENMO_WT_BASE_IDX … #define mmGENS0 … #define mmGENS0_BASE_IDX … #define mmGENENB … #define mmGENENB_BASE_IDX … #define mmSEQ8_IDX … #define mmSEQ8_IDX_BASE_IDX … #define mmSEQ8_DATA … #define mmSEQ8_DATA_BASE_IDX … #define mmDAC_MASK … #define mmDAC_MASK_BASE_IDX … #define mmDAC_R_INDEX … #define mmDAC_R_INDEX_BASE_IDX … #define mmDAC_W_INDEX … #define mmDAC_W_INDEX_BASE_IDX … #define mmDAC_DATA … #define mmDAC_DATA_BASE_IDX … #define mmGENFC_RD … #define mmGENFC_RD_BASE_IDX … #define mmGENMO_RD … #define mmGENMO_RD_BASE_IDX … #define mmGRPH8_IDX … #define mmGRPH8_IDX_BASE_IDX … #define mmGRPH8_DATA … #define mmGRPH8_DATA_BASE_IDX … #define mmCRTC8_IDX_1 … #define mmCRTC8_IDX_1_BASE_IDX … #define mmCRTC8_DATA_1 … #define mmCRTC8_DATA_1_BASE_IDX … #define mmGENFC_WT_1 … #define mmGENFC_WT_1_BASE_IDX … #define mmGENS1_1 … #define mmGENS1_1_BASE_IDX … #define mmD3VGA_CONTROL … #define mmD3VGA_CONTROL_BASE_IDX … #define mmD4VGA_CONTROL … #define mmD4VGA_CONTROL_BASE_IDX … #define mmD5VGA_CONTROL … #define mmD5VGA_CONTROL_BASE_IDX … #define mmD6VGA_CONTROL … #define mmD6VGA_CONTROL_BASE_IDX … #define mmVGA_SOURCE_SELECT … #define mmVGA_SOURCE_SELECT_BASE_IDX … #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLC_PIXCLK_RESYNC_CNTL … #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLD_PIXCLK_RESYNC_CNTL … #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL … #define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX … #define mmDCFEV1_CRTC_PIXEL_RATE_CNTL … #define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX … #define mmSYMCLKLPA_CLOCK_ENABLE … #define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKLPB_CLOCK_ENABLE … #define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX … #define mmDPREFCLK_CGTT_BLK_CTRL_REG … #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmREFCLK_CNTL … #define mmREFCLK_CNTL_BASE_IDX … #define mmMIPI_CLK_CNTL … #define mmMIPI_CLK_CNTL_BASE_IDX … #define mmREFCLK_CGTT_BLK_CTRL_REG … #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmPHYPLLE_PIXCLK_RESYNC_CNTL … #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_PERFMON_CNTL2 … #define mmDCCG_PERFMON_CNTL2_BASE_IDX … #define mmDSICLK_CGTT_BLK_CTRL_REG … #define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_CBUS_WRCMD_DELAY … #define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX … #define mmDCCG_DS_DTO_INCR … #define mmDCCG_DS_DTO_INCR_BASE_IDX … #define mmDCCG_DS_DTO_MODULO … #define mmDCCG_DS_DTO_MODULO_BASE_IDX … #define mmDCCG_DS_CNTL … #define mmDCCG_DS_CNTL_BASE_IDX … #define mmDCCG_DS_HW_CAL_INTERVAL … #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … #define mmSYMCLKG_CLOCK_ENABLE … #define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX … #define mmDPREFCLK_CNTL … #define mmDPREFCLK_CNTL_BASE_IDX … #define mmAOMCLK0_CNTL … #define mmAOMCLK0_CNTL_BASE_IDX … #define mmAOMCLK1_CNTL … #define mmAOMCLK1_CNTL_BASE_IDX … #define mmAOMCLK2_CNTL … #define mmAOMCLK2_CNTL_BASE_IDX … #define mmDCCG_AUDIO_DTO2_PHASE … #define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO2_MODULO … #define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX … #define mmDCE_VERSION … #define mmDCE_VERSION_BASE_IDX … #define mmPHYPLLG_PIXCLK_RESYNC_CNTL … #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_GTC_CNTL … #define mmDCCG_GTC_CNTL_BASE_IDX … #define mmDCCG_GTC_DTO_INCR … #define mmDCCG_GTC_DTO_INCR_BASE_IDX … #define mmDCCG_GTC_DTO_MODULO … #define mmDCCG_GTC_DTO_MODULO_BASE_IDX … #define mmDCCG_GTC_CURRENT … #define mmDCCG_GTC_CURRENT_BASE_IDX … #define mmDENTIST_DISPCLK_CNTL … #define mmDENTIST_DISPCLK_CNTL_BASE_IDX … #define mmMIPI_DTO_CNTL … #define mmMIPI_DTO_CNTL_BASE_IDX … #define mmMIPI_DTO_PHASE … #define mmMIPI_DTO_PHASE_BASE_IDX … #define mmMIPI_DTO_MODULO … #define mmMIPI_DTO_MODULO_BASE_IDX … #define mmDAC_CLK_ENABLE … #define mmDAC_CLK_ENABLE_BASE_IDX … #define mmDVO_CLK_ENABLE … #define mmDVO_CLK_ENABLE_BASE_IDX … #define mmAVSYNC_COUNTER_WRITE … #define mmAVSYNC_COUNTER_WRITE_BASE_IDX … #define mmAVSYNC_COUNTER_CONTROL … #define mmAVSYNC_COUNTER_CONTROL_BASE_IDX … #define mmDMCU_SMU_INTERRUPT_CNTL … #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX … #define mmSMU_CONTROL … #define mmSMU_CONTROL_BASE_IDX … #define mmSMU_INTERRUPT_CONTROL … #define mmSMU_INTERRUPT_CONTROL_BASE_IDX … #define mmAVSYNC_COUNTER_READ … #define mmAVSYNC_COUNTER_READ_BASE_IDX … #define mmMILLISECOND_TIME_BASE_DIV … #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX … #define mmDISPCLK_FREQ_CHANGE_CNTL … #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX … #define mmDCCG_PERFMON_CNTL … #define mmDCCG_PERFMON_CNTL_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL … #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX … #define mmDISPCLK_CGTT_BLK_CTRL_REG … #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmSCLK_CGTT_BLK_CTRL_REG … #define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_CAC_STATUS … #define mmDCCG_CAC_STATUS_BASE_IDX … #define mmPIXCLK1_RESYNC_CNTL … #define mmPIXCLK1_RESYNC_CNTL_BASE_IDX … #define mmPIXCLK2_RESYNC_CNTL … #define mmPIXCLK2_RESYNC_CNTL_BASE_IDX … #define mmPIXCLK0_RESYNC_CNTL … #define mmPIXCLK0_RESYNC_CNTL_BASE_IDX … #define mmMICROSECOND_TIME_BASE_DIV … #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL2 … #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX … #define mmSYMCLK_CGTT_BLK_CTRL_REG … #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmPHYPLLF_PIXCLK_RESYNC_CNTL … #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_DISP_CNTL_REG … #define mmDCCG_DISP_CNTL_REG_BASE_IDX … #define mmCRTC0_PIXEL_RATE_CNTL … #define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO0_PHASE … #define mmDP_DTO0_PHASE_BASE_IDX … #define mmDP_DTO0_MODULO … #define mmDP_DTO0_MODULO_BASE_IDX … #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmCRTC1_PIXEL_RATE_CNTL … #define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO1_PHASE … #define mmDP_DTO1_PHASE_BASE_IDX … #define mmDP_DTO1_MODULO … #define mmDP_DTO1_MODULO_BASE_IDX … #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmCRTC2_PIXEL_RATE_CNTL … #define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO2_PHASE … #define mmDP_DTO2_PHASE_BASE_IDX … #define mmDP_DTO2_MODULO … #define mmDP_DTO2_MODULO_BASE_IDX … #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmCRTC3_PIXEL_RATE_CNTL … #define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO3_PHASE … #define mmDP_DTO3_PHASE_BASE_IDX … #define mmDP_DTO3_MODULO … #define mmDP_DTO3_MODULO_BASE_IDX … #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmCRTC4_PIXEL_RATE_CNTL … #define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO4_PHASE … #define mmDP_DTO4_PHASE_BASE_IDX … #define mmDP_DTO4_MODULO … #define mmDP_DTO4_MODULO_BASE_IDX … #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmCRTC5_PIXEL_RATE_CNTL … #define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO5_PHASE … #define mmDP_DTO5_PHASE_BASE_IDX … #define mmDP_DTO5_MODULO … #define mmDP_DTO5_MODULO_BASE_IDX … #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL … #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmDCCG_SOFT_RESET … #define mmDCCG_SOFT_RESET_BASE_IDX … #define mmSYMCLKA_CLOCK_ENABLE … #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKB_CLOCK_ENABLE … #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKC_CLOCK_ENABLE … #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKD_CLOCK_ENABLE … #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKE_CLOCK_ENABLE … #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKF_CLOCK_ENABLE … #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX … #define mmDVOACLKD_CNTL … #define mmDVOACLKD_CNTL_BASE_IDX … #define mmDVOACLKC_MVP_CNTL … #define mmDVOACLKC_MVP_CNTL_BASE_IDX … #define mmDVOACLKC_CNTL … #define mmDVOACLKC_CNTL_BASE_IDX … #define mmDCCG_AUDIO_DTO_SOURCE … #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_PHASE … #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_MODULE … #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_PHASE … #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_MODULE … #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX … #define mmDCCG_TEST_CLK_SEL … #define mmDCCG_TEST_CLK_SEL_BASE_IDX … #define mmFBC_CNTL … #define mmFBC_CNTL_BASE_IDX … #define mmFBC_IDLE_FORCE_CLEAR_MASK … #define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX … #define mmFBC_START_STOP_DELAY … #define mmFBC_START_STOP_DELAY_BASE_IDX … #define mmFBC_COMP_CNTL … #define mmFBC_COMP_CNTL_BASE_IDX … #define mmFBC_COMP_MODE … #define mmFBC_COMP_MODE_BASE_IDX … #define mmFBC_IND_LUT0 … #define mmFBC_IND_LUT0_BASE_IDX … #define mmFBC_IND_LUT1 … #define mmFBC_IND_LUT1_BASE_IDX … #define mmFBC_IND_LUT2 … #define mmFBC_IND_LUT2_BASE_IDX … #define mmFBC_IND_LUT3 … #define mmFBC_IND_LUT3_BASE_IDX … #define mmFBC_IND_LUT4 … #define mmFBC_IND_LUT4_BASE_IDX … #define mmFBC_IND_LUT5 … #define mmFBC_IND_LUT5_BASE_IDX … #define mmFBC_IND_LUT6 … #define mmFBC_IND_LUT6_BASE_IDX … #define mmFBC_IND_LUT7 … #define mmFBC_IND_LUT7_BASE_IDX … #define mmFBC_IND_LUT8 … #define mmFBC_IND_LUT8_BASE_IDX … #define mmFBC_IND_LUT9 … #define mmFBC_IND_LUT9_BASE_IDX … #define mmFBC_IND_LUT10 … #define mmFBC_IND_LUT10_BASE_IDX … #define mmFBC_IND_LUT11 … #define mmFBC_IND_LUT11_BASE_IDX … #define mmFBC_IND_LUT12 … #define mmFBC_IND_LUT12_BASE_IDX … #define mmFBC_IND_LUT13 … #define mmFBC_IND_LUT13_BASE_IDX … #define mmFBC_IND_LUT14 … #define mmFBC_IND_LUT14_BASE_IDX … #define mmFBC_IND_LUT15 … #define mmFBC_IND_LUT15_BASE_IDX … #define mmFBC_CSM_REGION_OFFSET_01 … #define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX … #define mmFBC_CSM_REGION_OFFSET_23 … #define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX … #define mmFBC_CLIENT_REGION_MASK … #define mmFBC_CLIENT_REGION_MASK_BASE_IDX … #define mmFBC_DEBUG_COMP … #define mmFBC_DEBUG_COMP_BASE_IDX … #define mmFBC_MISC … #define mmFBC_MISC_BASE_IDX … #define mmFBC_STATUS … #define mmFBC_STATUS_BASE_IDX … #define mmFBC_ALPHA_CNTL … #define mmFBC_ALPHA_CNTL_BASE_IDX … #define mmFBC_ALPHA_RGB_OVERRIDE … #define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX … #define mmPIPE0_PG_CONFIG … #define mmPIPE0_PG_CONFIG_BASE_IDX … #define mmPIPE0_PG_ENABLE … #define mmPIPE0_PG_ENABLE_BASE_IDX … #define mmPIPE0_PG_STATUS … #define mmPIPE0_PG_STATUS_BASE_IDX … #define mmPIPE1_PG_CONFIG … #define mmPIPE1_PG_CONFIG_BASE_IDX … #define mmPIPE1_PG_ENABLE … #define mmPIPE1_PG_ENABLE_BASE_IDX … #define mmPIPE1_PG_STATUS … #define mmPIPE1_PG_STATUS_BASE_IDX … #define mmPIPE2_PG_CONFIG … #define mmPIPE2_PG_CONFIG_BASE_IDX … #define mmPIPE2_PG_ENABLE … #define mmPIPE2_PG_ENABLE_BASE_IDX … #define mmPIPE2_PG_STATUS … #define mmPIPE2_PG_STATUS_BASE_IDX … #define mmPIPE3_PG_CONFIG … #define mmPIPE3_PG_CONFIG_BASE_IDX … #define mmPIPE3_PG_ENABLE … #define mmPIPE3_PG_ENABLE_BASE_IDX … #define mmPIPE3_PG_STATUS … #define mmPIPE3_PG_STATUS_BASE_IDX … #define mmPIPE4_PG_CONFIG … #define mmPIPE4_PG_CONFIG_BASE_IDX … #define mmPIPE4_PG_ENABLE … #define mmPIPE4_PG_ENABLE_BASE_IDX … #define mmPIPE4_PG_STATUS … #define mmPIPE4_PG_STATUS_BASE_IDX … #define mmPIPE5_PG_CONFIG … #define mmPIPE5_PG_CONFIG_BASE_IDX … #define mmPIPE5_PG_ENABLE … #define mmPIPE5_PG_ENABLE_BASE_IDX … #define mmPIPE5_PG_STATUS … #define mmPIPE5_PG_STATUS_BASE_IDX … #define mmDSI_PG_CONFIG … #define mmDSI_PG_CONFIG_BASE_IDX … #define mmDSI_PG_ENABLE … #define mmDSI_PG_ENABLE_BASE_IDX … #define mmDSI_PG_STATUS … #define mmDSI_PG_STATUS_BASE_IDX … #define mmDCFEV0_PG_CONFIG … #define mmDCFEV0_PG_CONFIG_BASE_IDX … #define mmDCFEV0_PG_ENABLE … #define mmDCFEV0_PG_ENABLE_BASE_IDX … #define mmDCFEV0_PG_STATUS … #define mmDCFEV0_PG_STATUS_BASE_IDX … #define mmDCPG_INTERRUPT_STATUS … #define mmDCPG_INTERRUPT_STATUS_BASE_IDX … #define mmDCPG_INTERRUPT_CONTROL … #define mmDCPG_INTERRUPT_CONTROL_BASE_IDX … #define mmDCPG_INTERRUPT_CONTROL2 … #define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX … #define mmDCFEV1_PG_CONFIG … #define mmDCFEV1_PG_CONFIG_BASE_IDX … #define mmDCFEV1_PG_ENABLE … #define mmDCFEV1_PG_ENABLE_BASE_IDX … #define mmDCFEV1_PG_STATUS … #define mmDCFEV1_PG_STATUS_BASE_IDX … #define mmDC_IP_REQUEST_CNTL … #define mmDC_IP_REQUEST_CNTL_BASE_IDX … #define mmDC_PGCNTL_STATUS_REG … #define mmDC_PGCNTL_STATUS_REG_BASE_IDX … #define mmDMIFV_STATUS … #define mmDMIFV_STATUS_BASE_IDX … #define mmDMIF_CONTROL … #define mmDMIF_CONTROL_BASE_IDX … #define mmDMIF_STATUS … #define mmDMIF_STATUS_BASE_IDX … #define mmDMIF_ARBITRATION_CONTROL … #define mmDMIF_ARBITRATION_CONTROL_BASE_IDX … #define mmPIPE0_ARBITRATION_CONTROL3 … #define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE1_ARBITRATION_CONTROL3 … #define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE2_ARBITRATION_CONTROL3 … #define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE3_ARBITRATION_CONTROL3 … #define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE4_ARBITRATION_CONTROL3 … #define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE5_ARBITRATION_CONTROL3 … #define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX … #define mmDMIF_P_VMID … #define mmDMIF_P_VMID_BASE_IDX … #define mmDMIF_ADDR_CALC … #define mmDMIF_ADDR_CALC_BASE_IDX … #define mmDMIF_STATUS2 … #define mmDMIF_STATUS2_BASE_IDX … #define mmPIPE0_MAX_REQUESTS … #define mmPIPE0_MAX_REQUESTS_BASE_IDX … #define mmPIPE1_MAX_REQUESTS … #define mmPIPE1_MAX_REQUESTS_BASE_IDX … #define mmPIPE2_MAX_REQUESTS … #define mmPIPE2_MAX_REQUESTS_BASE_IDX … #define mmPIPE3_MAX_REQUESTS … #define mmPIPE3_MAX_REQUESTS_BASE_IDX … #define mmPIPE4_MAX_REQUESTS … #define mmPIPE4_MAX_REQUESTS_BASE_IDX … #define mmPIPE5_MAX_REQUESTS … #define mmPIPE5_MAX_REQUESTS_BASE_IDX … #define mmLOW_POWER_TILING_CONTROL … #define mmLOW_POWER_TILING_CONTROL_BASE_IDX … #define mmMCIF_CONTROL … #define mmMCIF_CONTROL_BASE_IDX … #define mmMCIF_WRITE_COMBINE_CONTROL … #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX … #define mmMCIF_PHASE0_OUTSTANDING_COUNTER … #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define mmCC_DC_PIPE_DIS … #define mmCC_DC_PIPE_DIS_BASE_IDX … #define mmSMU_WM_CONTROL … #define mmSMU_WM_CONTROL_BASE_IDX … #define mmRBBMIF_TIMEOUT … #define mmRBBMIF_TIMEOUT_BASE_IDX … #define mmRBBMIF_STATUS … #define mmRBBMIF_STATUS_BASE_IDX … #define mmRBBMIF_TIMEOUT_DIS … #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX … #define mmDCI_MEM_PWR_STATUS … #define mmDCI_MEM_PWR_STATUS_BASE_IDX … #define mmDCI_MEM_PWR_STATUS2 … #define mmDCI_MEM_PWR_STATUS2_BASE_IDX … #define mmDCI_CLK_CNTL … #define mmDCI_CLK_CNTL_BASE_IDX … #define mmDCI_CLK_CNTL2 … #define mmDCI_CLK_CNTL2_BASE_IDX … #define mmDCI_MEM_PWR_CNTL … #define mmDCI_MEM_PWR_CNTL_BASE_IDX … #define mmDCI_MEM_PWR_CNTL2 … #define mmDCI_MEM_PWR_CNTL2_BASE_IDX … #define mmDCI_MEM_PWR_CNTL3 … #define mmDCI_MEM_PWR_CNTL3_BASE_IDX … #define mmPIPE0_DMIF_BUFFER_CONTROL … #define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmPIPE1_DMIF_BUFFER_CONTROL … #define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmPIPE2_DMIF_BUFFER_CONTROL … #define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmPIPE3_DMIF_BUFFER_CONTROL … #define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmPIPE4_DMIF_BUFFER_CONTROL … #define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmPIPE5_DMIF_BUFFER_CONTROL … #define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX … #define mmRBBMIF_STATUS_FLAG … #define mmRBBMIF_STATUS_FLAG_BASE_IDX … #define mmDCI_SOFT_RESET … #define mmDCI_SOFT_RESET_BASE_IDX … #define mmDMIF_URG_OVERRIDE … #define mmDMIF_URG_OVERRIDE_BASE_IDX … #define mmPIPE6_ARBITRATION_CONTROL3 … #define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE7_ARBITRATION_CONTROL3 … #define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX … #define mmPIPE6_MAX_REQUESTS … #define mmPIPE6_MAX_REQUESTS_BASE_IDX … #define mmPIPE7_MAX_REQUESTS … #define mmPIPE7_MAX_REQUESTS_BASE_IDX … #define mmDVMM_REG_RD_STATUS … #define mmDVMM_REG_RD_STATUS_BASE_IDX … #define mmDVMM_REG_RD_DATA … #define mmDVMM_REG_RD_DATA_BASE_IDX … #define mmDVMM_PTE_REQ … #define mmDVMM_PTE_REQ_BASE_IDX … #define mmDVMM_CNTL … #define mmDVMM_CNTL_BASE_IDX … #define mmDVMM_FAULT_STATUS … #define mmDVMM_FAULT_STATUS_BASE_IDX … #define mmDVMM_FAULT_ADDR … #define mmDVMM_FAULT_ADDR_BASE_IDX … #define mmFMON_CTRL … #define mmFMON_CTRL_BASE_IDX … #define mmDVMM_PTE_PGMEM_CONTROL … #define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX … #define mmDVMM_PTE_PGMEM_STATE … #define mmDVMM_PTE_PGMEM_STATE_BASE_IDX … #define mmMCIF_PHASE1_OUTSTANDING_COUNTER … #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define mmMCIF_PHASE2_OUTSTANDING_COUNTER … #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX … #define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER … #define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER … #define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define mmDCI_MEM_PWR_CNTL4 … #define mmDCI_MEM_PWR_CNTL4_BASE_IDX … #define mmMCIF_WB_MISC_CTRL … #define mmMCIF_WB_MISC_CTRL_BASE_IDX … #define mmDCI_MEM_PWR_STATUS3 … #define mmDCI_MEM_PWR_STATUS3_BASE_IDX … #define mmDMIF_CURSOR_CONTROL … #define mmDMIF_CURSOR_CONTROL_BASE_IDX … #define mmDMIF_CURSOR_MEM_CONTROL … #define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX … #define mmDCHUB_FB_LOCATION … #define mmDCHUB_FB_LOCATION_BASE_IDX … #define mmDCHUB_FB_OFFSET … #define mmDCHUB_FB_OFFSET_BASE_IDX … #define mmDCHUB_AGP_BASE … #define mmDCHUB_AGP_BASE_BASE_IDX … #define mmDCHUB_AGP_BOT … #define mmDCHUB_AGP_BOT_BASE_IDX … #define mmDCHUB_AGP_TOP … #define mmDCHUB_AGP_TOP_BASE_IDX … #define mmDCHUB_DRAM_APER_BASE … #define mmDCHUB_DRAM_APER_BASE_BASE_IDX … #define mmDCHUB_DRAM_APER_DEF … #define mmDCHUB_DRAM_APER_DEF_BASE_IDX … #define mmDCHUB_DRAM_APER_TOP … #define mmDCHUB_DRAM_APER_TOP_BASE_IDX … #define mmDCHUB_CONTROL_STATUS … #define mmDCHUB_CONTROL_STATUS_BASE_IDX … #define mmWB_ENABLE … #define mmWB_ENABLE_BASE_IDX … #define mmWB_EC_CONFIG … #define mmWB_EC_CONFIG_BASE_IDX … #define mmCNV_MODE … #define mmCNV_MODE_BASE_IDX … #define mmCNV_WINDOW_START … #define mmCNV_WINDOW_START_BASE_IDX … #define mmCNV_WINDOW_SIZE … #define mmCNV_WINDOW_SIZE_BASE_IDX … #define mmCNV_UPDATE … #define mmCNV_UPDATE_BASE_IDX … #define mmCNV_SOURCE_SIZE … #define mmCNV_SOURCE_SIZE_BASE_IDX … #define mmCNV_CSC_CONTROL … #define mmCNV_CSC_CONTROL_BASE_IDX … #define mmCNV_CSC_C11_C12 … #define mmCNV_CSC_C11_C12_BASE_IDX … #define mmCNV_CSC_C13_C14 … #define mmCNV_CSC_C13_C14_BASE_IDX … #define mmCNV_CSC_C21_C22 … #define mmCNV_CSC_C21_C22_BASE_IDX … #define mmCNV_CSC_C23_C24 … #define mmCNV_CSC_C23_C24_BASE_IDX … #define mmCNV_CSC_C31_C32 … #define mmCNV_CSC_C31_C32_BASE_IDX … #define mmCNV_CSC_C33_C34 … #define mmCNV_CSC_C33_C34_BASE_IDX … #define mmCNV_CSC_ROUND_OFFSET_R … #define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX … #define mmCNV_CSC_ROUND_OFFSET_G … #define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX … #define mmCNV_CSC_ROUND_OFFSET_B … #define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX … #define mmCNV_CSC_CLAMP_R … #define mmCNV_CSC_CLAMP_R_BASE_IDX … #define mmCNV_CSC_CLAMP_G … #define mmCNV_CSC_CLAMP_G_BASE_IDX … #define mmCNV_CSC_CLAMP_B … #define mmCNV_CSC_CLAMP_B_BASE_IDX … #define mmCNV_TEST_CNTL … #define mmCNV_TEST_CNTL_BASE_IDX … #define mmCNV_TEST_CRC_RED … #define mmCNV_TEST_CRC_RED_BASE_IDX … #define mmCNV_TEST_CRC_GREEN … #define mmCNV_TEST_CRC_GREEN_BASE_IDX … #define mmCNV_TEST_CRC_BLUE … #define mmCNV_TEST_CRC_BLUE_BASE_IDX … #define mmCNV_INPUT_SELECT … #define mmCNV_INPUT_SELECT_BASE_IDX … #define mmWB_SOFT_RESET … #define mmWB_SOFT_RESET_BASE_IDX … #define mmWB_WARM_UP_MODE_CTL1 … #define mmWB_WARM_UP_MODE_CTL1_BASE_IDX … #define mmWB_WARM_UP_MODE_CTL2 … #define mmWB_WARM_UP_MODE_CTL2_BASE_IDX … #define mmWBSCL_COEF_RAM_SELECT … #define mmWBSCL_COEF_RAM_SELECT_BASE_IDX … #define mmWBSCL_COEF_RAM_TAP_DATA … #define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmWBSCL_MODE … #define mmWBSCL_MODE_BASE_IDX … #define mmWBSCL_TAP_CONTROL … #define mmWBSCL_TAP_CONTROL_BASE_IDX … #define mmWBSCL_DEST_SIZE … #define mmWBSCL_DEST_SIZE_BASE_IDX … #define mmWBSCL_HORZ_FILTER_SCALE_RATIO … #define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB … #define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL_HORZ_FILTER_INIT_CBCR … #define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL_VERT_FILTER_SCALE_RATIO … #define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL_VERT_FILTER_INIT_Y_RGB … #define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL_VERT_FILTER_INIT_CBCR … #define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL_ROUND_OFFSET … #define mmWBSCL_ROUND_OFFSET_BASE_IDX … #define mmWBSCL_CLAMP … #define mmWBSCL_CLAMP_BASE_IDX … #define mmWBSCL_OVERFLOW_STATUS … #define mmWBSCL_OVERFLOW_STATUS_BASE_IDX … #define mmWBSCL_COEF_RAM_CONFLICT_STATUS … #define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmWBSCL_OUTSIDE_PIX_STRATEGY … #define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX … #define mmWBSCL_TEST_CNTL … #define mmWBSCL_TEST_CNTL_BASE_IDX … #define mmWBSCL_TEST_CRC_RED … #define mmWBSCL_TEST_CRC_RED_BASE_IDX … #define mmWBSCL_TEST_CRC_GREEN … #define mmWBSCL_TEST_CRC_GREEN_BASE_IDX … #define mmWBSCL_TEST_CRC_BLUE … #define mmWBSCL_TEST_CRC_BLUE_BASE_IDX … #define mmWBSCL_BACKPRESSURE_CNT_EN … #define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX … #define mmWB_MCIF_BACKPRESSURE_CNT … #define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX … #define mmWBSCL_RAM_SHUTDOWN … #define mmWBSCL_RAM_SHUTDOWN_BASE_IDX … #define mmDMCU_CTRL … #define mmDMCU_CTRL_BASE_IDX … #define mmDMCU_STATUS … #define mmDMCU_STATUS_BASE_IDX … #define mmDMCU_PC_START_ADDR … #define mmDMCU_PC_START_ADDR_BASE_IDX … #define mmDMCU_FW_START_ADDR … #define mmDMCU_FW_START_ADDR_BASE_IDX … #define mmDMCU_FW_END_ADDR … #define mmDMCU_FW_END_ADDR_BASE_IDX … #define mmDMCU_FW_ISR_START_ADDR … #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX … #define mmDMCU_FW_CS_HI … #define mmDMCU_FW_CS_HI_BASE_IDX … #define mmDMCU_FW_CS_LO … #define mmDMCU_FW_CS_LO_BASE_IDX … #define mmDMCU_RAM_ACCESS_CTRL … #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX … #define mmDMCU_ERAM_WR_CTRL … #define mmDMCU_ERAM_WR_CTRL_BASE_IDX … #define mmDMCU_ERAM_WR_DATA … #define mmDMCU_ERAM_WR_DATA_BASE_IDX … #define mmDMCU_ERAM_RD_CTRL … #define mmDMCU_ERAM_RD_CTRL_BASE_IDX … #define mmDMCU_ERAM_RD_DATA … #define mmDMCU_ERAM_RD_DATA_BASE_IDX … #define mmDMCU_IRAM_WR_CTRL … #define mmDMCU_IRAM_WR_CTRL_BASE_IDX … #define mmDMCU_IRAM_WR_DATA … #define mmDMCU_IRAM_WR_DATA_BASE_IDX … #define mmDMCU_IRAM_RD_CTRL … #define mmDMCU_IRAM_RD_CTRL_BASE_IDX … #define mmDMCU_IRAM_RD_DATA … #define mmDMCU_IRAM_RD_DATA_BASE_IDX … #define mmDMCU_EVENT_TRIGGER … #define mmDMCU_EVENT_TRIGGER_BASE_IDX … #define mmDMCU_UC_INTERNAL_INT_STATUS … #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX … #define mmDMCU_SS_INTERRUPT_CNTL_STATUS … #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … #define mmDMCU_INTERRUPT_STATUS … #define mmDMCU_INTERRUPT_STATUS_BASE_IDX … #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK … #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX … #define mmDC_DMCU_SCRATCH … #define mmDC_DMCU_SCRATCH_BASE_IDX … #define mmDMCU_INT_CNT … #define mmDMCU_INT_CNT_BASE_IDX … #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS … #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX … #define mmDMCU_UC_CLK_GATING_CNTL … #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX … #define mmMASTER_COMM_DATA_REG1 … #define mmMASTER_COMM_DATA_REG1_BASE_IDX … #define mmMASTER_COMM_DATA_REG2 … #define mmMASTER_COMM_DATA_REG2_BASE_IDX … #define mmMASTER_COMM_DATA_REG3 … #define mmMASTER_COMM_DATA_REG3_BASE_IDX … #define mmMASTER_COMM_CMD_REG … #define mmMASTER_COMM_CMD_REG_BASE_IDX … #define mmMASTER_COMM_CNTL_REG … #define mmMASTER_COMM_CNTL_REG_BASE_IDX … #define mmSLAVE_COMM_DATA_REG1 … #define mmSLAVE_COMM_DATA_REG1_BASE_IDX … #define mmSLAVE_COMM_DATA_REG2 … #define mmSLAVE_COMM_DATA_REG2_BASE_IDX … #define mmSLAVE_COMM_DATA_REG3 … #define mmSLAVE_COMM_DATA_REG3_BASE_IDX … #define mmSLAVE_COMM_CMD_REG … #define mmSLAVE_COMM_CMD_REG_BASE_IDX … #define mmSLAVE_COMM_CNTL_REG … #define mmSLAVE_COMM_CNTL_REG_BASE_IDX … #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL … #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define mmBL1_PWM_USER_LEVEL … #define mmBL1_PWM_USER_LEVEL_BASE_IDX … #define mmBL1_PWM_TARGET_ABM_LEVEL … #define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define mmBL1_PWM_CURRENT_ABM_LEVEL … #define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define mmBL1_PWM_FINAL_DUTY_CYCLE … #define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define mmBL1_PWM_MINIMUM_DUTY_CYCLE … #define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define mmBL1_PWM_ABM_CNTL … #define mmBL1_PWM_ABM_CNTL_BASE_IDX … #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE … #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define mmBL1_PWM_GRP2_REG_LOCK … #define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX … #define mmDMCU_INTERRUPT_STATUS_1 … #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_STATUS1 … #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX … #define mmDC_ABM1_CNTL … #define mmDC_ABM1_CNTL_BASE_IDX … #define mmDC_ABM1_IPCSC_COEFF_SEL … #define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX … #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX … #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX … #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX … #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 … #define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX … #define mmDC_ABM1_ACE_THRES_12 … #define mmDC_ABM1_ACE_THRES_12_BASE_IDX … #define mmDC_ABM1_ACE_THRES_34 … #define mmDC_ABM1_ACE_THRES_34_BASE_IDX … #define mmDC_ABM1_ACE_CNTL_MISC … #define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS5 … #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS1 … #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS2 … #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS3 … #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS4 … #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX … #define mmDC_ABM1_HGLS_REG_READ_PROGRESS … #define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define mmDC_ABM1_HG_MISC_CTRL … #define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX … #define mmDC_ABM1_LS_SUM_OF_LUMA … #define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define mmDC_ABM1_LS_MIN_MAX_LUMA … #define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define mmDC_ABM1_LS_PIXEL_COUNT … #define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define mmDC_ABM1_LS_OVR_SCAN_BIN … #define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX … #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define mmDC_ABM1_HG_SAMPLE_RATE … #define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define mmDC_ABM1_LS_SAMPLE_RATE … #define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define mmDC_ABM1_HG_RESULT_1 … #define mmDC_ABM1_HG_RESULT_1_BASE_IDX … #define mmDC_ABM1_HG_RESULT_2 … #define mmDC_ABM1_HG_RESULT_2_BASE_IDX … #define mmDC_ABM1_HG_RESULT_3 … #define mmDC_ABM1_HG_RESULT_3_BASE_IDX … #define mmDC_ABM1_HG_RESULT_4 … #define mmDC_ABM1_HG_RESULT_4_BASE_IDX … #define mmDC_ABM1_HG_RESULT_5 … #define mmDC_ABM1_HG_RESULT_5_BASE_IDX … #define mmDC_ABM1_HG_RESULT_6 … #define mmDC_ABM1_HG_RESULT_6_BASE_IDX … #define mmDC_ABM1_HG_RESULT_7 … #define mmDC_ABM1_HG_RESULT_7_BASE_IDX … #define mmDC_ABM1_HG_RESULT_8 … #define mmDC_ABM1_HG_RESULT_8_BASE_IDX … #define mmDC_ABM1_HG_RESULT_9 … #define mmDC_ABM1_HG_RESULT_9_BASE_IDX … #define mmDC_ABM1_HG_RESULT_10 … #define mmDC_ABM1_HG_RESULT_10_BASE_IDX … #define mmDC_ABM1_HG_RESULT_11 … #define mmDC_ABM1_HG_RESULT_11_BASE_IDX … #define mmDC_ABM1_HG_RESULT_12 … #define mmDC_ABM1_HG_RESULT_12_BASE_IDX … #define mmDC_ABM1_HG_RESULT_13 … #define mmDC_ABM1_HG_RESULT_13_BASE_IDX … #define mmDC_ABM1_HG_RESULT_14 … #define mmDC_ABM1_HG_RESULT_14_BASE_IDX … #define mmDC_ABM1_HG_RESULT_15 … #define mmDC_ABM1_HG_RESULT_15_BASE_IDX … #define mmDC_ABM1_HG_RESULT_16 … #define mmDC_ABM1_HG_RESULT_16_BASE_IDX … #define mmDC_ABM1_HG_RESULT_17 … #define mmDC_ABM1_HG_RESULT_17_BASE_IDX … #define mmDC_ABM1_HG_RESULT_18 … #define mmDC_ABM1_HG_RESULT_18_BASE_IDX … #define mmDC_ABM1_HG_RESULT_19 … #define mmDC_ABM1_HG_RESULT_19_BASE_IDX … #define mmDC_ABM1_HG_RESULT_20 … #define mmDC_ABM1_HG_RESULT_20_BASE_IDX … #define mmDC_ABM1_HG_RESULT_21 … #define mmDC_ABM1_HG_RESULT_21_BASE_IDX … #define mmDC_ABM1_HG_RESULT_22 … #define mmDC_ABM1_HG_RESULT_22_BASE_IDX … #define mmDC_ABM1_HG_RESULT_23 … #define mmDC_ABM1_HG_RESULT_23_BASE_IDX … #define mmDC_ABM1_HG_RESULT_24 … #define mmDC_ABM1_HG_RESULT_24_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX … #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE … #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX … #define mmDC_ABM1_BL_MASTER_LOCK … #define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX … #define mmAZALIA_CONTROLLER_CLOCK_GATING … #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX … #define mmAZALIA_AUDIO_DTO … #define mmAZALIA_AUDIO_DTO_BASE_IDX … #define mmAZALIA_AUDIO_DTO_CONTROL … #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX … #define mmAZALIA_SOCCLK_CONTROL … #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX … #define mmAZALIA_DATA_DMA_CONTROL … #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX … #define mmAZALIA_BDL_DMA_CONTROL … #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX … #define mmAZALIA_RIRB_AND_DP_CONTROL … #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX … #define mmAZALIA_CORB_DMA_CONTROL … #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX … #define mmAZALIA_CYCLIC_BUFFER_SYNC … #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX … #define mmAZALIA_GLOBAL_CAPABILITIES … #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL0 … #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL1 … #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL2 … #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL3 … #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC0_RESULT … #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL0 … #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL1 … #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL2 … #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL3 … #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC1_RESULT … #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX … #define mmAZALIA_CRC0_CONTROL0 … #define mmAZALIA_CRC0_CONTROL0_BASE_IDX … #define mmAZALIA_CRC0_CONTROL1 … #define mmAZALIA_CRC0_CONTROL1_BASE_IDX … #define mmAZALIA_CRC0_CONTROL2 … #define mmAZALIA_CRC0_CONTROL2_BASE_IDX … #define mmAZALIA_CRC0_CONTROL3 … #define mmAZALIA_CRC0_CONTROL3_BASE_IDX … #define mmAZALIA_CRC0_RESULT … #define mmAZALIA_CRC0_RESULT_BASE_IDX … #define mmAZALIA_CRC1_CONTROL0 … #define mmAZALIA_CRC1_CONTROL0_BASE_IDX … #define mmAZALIA_CRC1_CONTROL1 … #define mmAZALIA_CRC1_CONTROL1_BASE_IDX … #define mmAZALIA_CRC1_CONTROL2 … #define mmAZALIA_CRC1_CONTROL2_BASE_IDX … #define mmAZALIA_CRC1_CONTROL3 … #define mmAZALIA_CRC1_CONTROL3_BASE_IDX … #define mmAZALIA_CRC1_RESULT … #define mmAZALIA_CRC1_RESULT_BASE_IDX … #define mmAZALIA_MEM_PWR_CTRL … #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX … #define mmAZALIA_MEM_PWR_STATUS … #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX … #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY … #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET0 … #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET1 … #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET2 … #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET3 … #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET4 … #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET5 … #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET6 … #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … #define mmDAC_ENABLE … #define mmDAC_ENABLE_BASE_IDX … #define mmDAC_SOURCE_SELECT … #define mmDAC_SOURCE_SELECT_BASE_IDX … #define mmDAC_CRC_EN … #define mmDAC_CRC_EN_BASE_IDX … #define mmDAC_CRC_CONTROL … #define mmDAC_CRC_CONTROL_BASE_IDX … #define mmDAC_CRC_SIG_RGB_MASK … #define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX … #define mmDAC_CRC_SIG_CONTROL_MASK … #define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX … #define mmDAC_CRC_SIG_RGB … #define mmDAC_CRC_SIG_RGB_BASE_IDX … #define mmDAC_CRC_SIG_CONTROL … #define mmDAC_CRC_SIG_CONTROL_BASE_IDX … #define mmDAC_SYNC_TRISTATE_CONTROL … #define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX … #define mmDAC_STEREOSYNC_SELECT … #define mmDAC_STEREOSYNC_SELECT_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL … #define mmDAC_AUTODETECT_CONTROL_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL2 … #define mmDAC_AUTODETECT_CONTROL2_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL3 … #define mmDAC_AUTODETECT_CONTROL3_BASE_IDX … #define mmDAC_AUTODETECT_STATUS … #define mmDAC_AUTODETECT_STATUS_BASE_IDX … #define mmDAC_AUTODETECT_INT_CONTROL … #define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX … #define mmDAC_FORCE_OUTPUT_CNTL … #define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX … #define mmDAC_FORCE_DATA … #define mmDAC_FORCE_DATA_BASE_IDX … #define mmDAC_POWERDOWN … #define mmDAC_POWERDOWN_BASE_IDX … #define mmDAC_CONTROL … #define mmDAC_CONTROL_BASE_IDX … #define mmDAC_COMPARATOR_ENABLE … #define mmDAC_COMPARATOR_ENABLE_BASE_IDX … #define mmDAC_COMPARATOR_OUTPUT … #define mmDAC_COMPARATOR_OUTPUT_BASE_IDX … #define mmDAC_PWR_CNTL … #define mmDAC_PWR_CNTL_BASE_IDX … #define mmDAC_DFT_CONFIG … #define mmDAC_DFT_CONFIG_BASE_IDX … #define mmDAC_FIFO_STATUS … #define mmDAC_FIFO_STATUS_BASE_IDX … #define mmDC_I2C_CONTROL … #define mmDC_I2C_CONTROL_BASE_IDX … #define mmDC_I2C_ARBITRATION … #define mmDC_I2C_ARBITRATION_BASE_IDX … #define mmDC_I2C_INTERRUPT_CONTROL … #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define mmDC_I2C_SW_STATUS … #define mmDC_I2C_SW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_HW_STATUS … #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC2_HW_STATUS … #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC3_HW_STATUS … #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC4_HW_STATUS … #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC5_HW_STATUS … #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC6_HW_STATUS … #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_SPEED … #define mmDC_I2C_DDC1_SPEED_BASE_IDX … #define mmDC_I2C_DDC1_SETUP … #define mmDC_I2C_DDC1_SETUP_BASE_IDX … #define mmDC_I2C_DDC2_SPEED … #define mmDC_I2C_DDC2_SPEED_BASE_IDX … #define mmDC_I2C_DDC2_SETUP … #define mmDC_I2C_DDC2_SETUP_BASE_IDX … #define mmDC_I2C_DDC3_SPEED … #define mmDC_I2C_DDC3_SPEED_BASE_IDX … #define mmDC_I2C_DDC3_SETUP … #define mmDC_I2C_DDC3_SETUP_BASE_IDX … #define mmDC_I2C_DDC4_SPEED … #define mmDC_I2C_DDC4_SPEED_BASE_IDX … #define mmDC_I2C_DDC4_SETUP … #define mmDC_I2C_DDC4_SETUP_BASE_IDX … #define mmDC_I2C_DDC5_SPEED … #define mmDC_I2C_DDC5_SPEED_BASE_IDX … #define mmDC_I2C_DDC5_SETUP … #define mmDC_I2C_DDC5_SETUP_BASE_IDX … #define mmDC_I2C_DDC6_SPEED … #define mmDC_I2C_DDC6_SPEED_BASE_IDX … #define mmDC_I2C_DDC6_SETUP … #define mmDC_I2C_DDC6_SETUP_BASE_IDX … #define mmDC_I2C_TRANSACTION0 … #define mmDC_I2C_TRANSACTION0_BASE_IDX … #define mmDC_I2C_TRANSACTION1 … #define mmDC_I2C_TRANSACTION1_BASE_IDX … #define mmDC_I2C_TRANSACTION2 … #define mmDC_I2C_TRANSACTION2_BASE_IDX … #define mmDC_I2C_TRANSACTION3 … #define mmDC_I2C_TRANSACTION3_BASE_IDX … #define mmDC_I2C_DATA … #define mmDC_I2C_DATA_BASE_IDX … #define mmDC_I2C_DDCVGA_HW_STATUS … #define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDCVGA_SPEED … #define mmDC_I2C_DDCVGA_SPEED_BASE_IDX … #define mmDC_I2C_DDCVGA_SETUP … #define mmDC_I2C_DDCVGA_SETUP_BASE_IDX … #define mmDC_I2C_EDID_DETECT_CTRL … #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX … #define mmDC_I2C_READ_REQUEST_INTERRUPT … #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX … #define mmGENERIC_I2C_CONTROL … #define mmGENERIC_I2C_CONTROL_BASE_IDX … #define mmGENERIC_I2C_INTERRUPT_CONTROL … #define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define mmGENERIC_I2C_STATUS … #define mmGENERIC_I2C_STATUS_BASE_IDX … #define mmGENERIC_I2C_SPEED … #define mmGENERIC_I2C_SPEED_BASE_IDX … #define mmGENERIC_I2C_SETUP … #define mmGENERIC_I2C_SETUP_BASE_IDX … #define mmGENERIC_I2C_TRANSACTION … #define mmGENERIC_I2C_TRANSACTION_BASE_IDX … #define mmGENERIC_I2C_DATA … #define mmGENERIC_I2C_DATA_BASE_IDX … #define mmGENERIC_I2C_PIN_SELECTION … #define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX … #define mmDCO_SCRATCH0 … #define mmDCO_SCRATCH0_BASE_IDX … #define mmDCO_SCRATCH1 … #define mmDCO_SCRATCH1_BASE_IDX … #define mmDCO_SCRATCH2 … #define mmDCO_SCRATCH2_BASE_IDX … #define mmDCO_SCRATCH3 … #define mmDCO_SCRATCH3_BASE_IDX … #define mmDCO_SCRATCH4 … #define mmDCO_SCRATCH4_BASE_IDX … #define mmDCO_SCRATCH5 … #define mmDCO_SCRATCH5_BASE_IDX … #define mmDCO_SCRATCH6 … #define mmDCO_SCRATCH6_BASE_IDX … #define mmDCO_SCRATCH7 … #define mmDCO_SCRATCH7_BASE_IDX … #define mmDCE_VCE_CONTROL … #define mmDCE_VCE_CONTROL_BASE_IDX … #define mmDISP_INTERRUPT_STATUS … #define mmDISP_INTERRUPT_STATUS_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE … #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE2 … #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE3 … #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE4 … #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE5 … #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE6 … #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE7 … #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE8 … #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE9 … #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX … #define mmDCO_MEM_PWR_STATUS … #define mmDCO_MEM_PWR_STATUS_BASE_IDX … #define mmDCO_MEM_PWR_CTRL … #define mmDCO_MEM_PWR_CTRL_BASE_IDX … #define mmDCO_MEM_PWR_CTRL2 … #define mmDCO_MEM_PWR_CTRL2_BASE_IDX … #define mmDCO_CLK_CNTL … #define mmDCO_CLK_CNTL_BASE_IDX … #define mmDCO_POWER_MANAGEMENT_CNTL … #define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX … #define mmDIG_SOFT_RESET_2 … #define mmDIG_SOFT_RESET_2_BASE_IDX … #define mmDCO_STEREOSYNC_SEL … #define mmDCO_STEREOSYNC_SEL_BASE_IDX … #define mmDCO_SOFT_RESET … #define mmDCO_SOFT_RESET_BASE_IDX … #define mmDIG_SOFT_RESET … #define mmDIG_SOFT_RESET_BASE_IDX … #define mmDCO_MEM_PWR_STATUS1 … #define mmDCO_MEM_PWR_STATUS1_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE10 … #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX … #define mmDCO_CLK_CNTL2 … #define mmDCO_CLK_CNTL2_BASE_IDX … #define mmDCO_CLK_CNTL3 … #define mmDCO_CLK_CNTL3_BASE_IDX … #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL … #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX … #define mmDCO_PSP_INTERRUPT_STATUS … #define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX … #define mmDCO_PSP_INTERRUPT_CLEAR … #define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX … #define mmDCO_GENERIC_INTERRUPT_MESSAGE … #define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX … #define mmDCO_GENERIC_INTERRUPT_CLEAR … #define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX … #define mmFMT_MEMORY0_CONTROL … #define mmFMT_MEMORY0_CONTROL_BASE_IDX … #define mmFMT_MEMORY1_CONTROL … #define mmFMT_MEMORY1_CONTROL_BASE_IDX … #define mmFMT_MEMORY2_CONTROL … #define mmFMT_MEMORY2_CONTROL_BASE_IDX … #define mmFMT_MEMORY3_CONTROL … #define mmFMT_MEMORY3_CONTROL_BASE_IDX … #define mmFMT_MEMORY4_CONTROL … #define mmFMT_MEMORY4_CONTROL_BASE_IDX … #define mmFMT_MEMORY5_CONTROL … #define mmFMT_MEMORY5_CONTROL_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE11 … #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX … #define mmDC_GENERICA … #define mmDC_GENERICA_BASE_IDX … #define mmDC_GENERICB … #define mmDC_GENERICB_BASE_IDX … #define mmDC_PAD_EXTERN_SIG … #define mmDC_PAD_EXTERN_SIG_BASE_IDX … #define mmDC_REF_CLK_CNTL … #define mmDC_REF_CLK_CNTL_BASE_IDX … #define mmDC_GPIO_DEBUG … #define mmDC_GPIO_DEBUG_BASE_IDX … #define mmUNIPHYA_LINK_CNTL … #define mmUNIPHYA_LINK_CNTL_BASE_IDX … #define mmUNIPHYA_CHANNEL_XBAR_CNTL … #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYB_LINK_CNTL … #define mmUNIPHYB_LINK_CNTL_BASE_IDX … #define mmUNIPHYB_CHANNEL_XBAR_CNTL … #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYC_LINK_CNTL … #define mmUNIPHYC_LINK_CNTL_BASE_IDX … #define mmUNIPHYC_CHANNEL_XBAR_CNTL … #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYD_LINK_CNTL … #define mmUNIPHYD_LINK_CNTL_BASE_IDX … #define mmUNIPHYD_CHANNEL_XBAR_CNTL … #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYE_LINK_CNTL … #define mmUNIPHYE_LINK_CNTL_BASE_IDX … #define mmUNIPHYE_CHANNEL_XBAR_CNTL … #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYF_LINK_CNTL … #define mmUNIPHYF_LINK_CNTL_BASE_IDX … #define mmUNIPHYF_CHANNEL_XBAR_CNTL … #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYG_LINK_CNTL … #define mmUNIPHYG_LINK_CNTL_BASE_IDX … #define mmUNIPHYG_CHANNEL_XBAR_CNTL … #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmDCIO_WRCMD_DELAY … #define mmDCIO_WRCMD_DELAY_BASE_IDX … #define mmDC_PINSTRAPS … #define mmDC_PINSTRAPS_BASE_IDX … #define mmCC_DC_MISC_STRAPS … #define mmCC_DC_MISC_STRAPS_BASE_IDX … #define mmDC_DVODATA_CONFIG … #define mmDC_DVODATA_CONFIG_BASE_IDX … #define mmLVTMA_PWRSEQ_CNTL … #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … #define mmLVTMA_PWRSEQ_STATE … #define mmLVTMA_PWRSEQ_STATE_BASE_IDX … #define mmLVTMA_PWRSEQ_REF_DIV … #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX … #define mmLVTMA_PWRSEQ_DELAY1 … #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX … #define mmLVTMA_PWRSEQ_DELAY2 … #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX … #define mmBL_PWM_CNTL … #define mmBL_PWM_CNTL_BASE_IDX … #define mmBL_PWM_CNTL2 … #define mmBL_PWM_CNTL2_BASE_IDX … #define mmBL_PWM_PERIOD_CNTL … #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … #define mmBL_PWM_GRP1_REG_LOCK … #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … #define mmDCIO_GSL_GENLK_PAD_CNTL … #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX … #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL … #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX … #define mmDCIO_GSL0_CNTL … #define mmDCIO_GSL0_CNTL_BASE_IDX … #define mmDCIO_GSL1_CNTL … #define mmDCIO_GSL1_CNTL_BASE_IDX … #define mmDCIO_GSL2_CNTL … #define mmDCIO_GSL2_CNTL_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_P_FLIP … #define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX … #define mmDC_GPU_TIMER_READ … #define mmDC_GPU_TIMER_READ_BASE_IDX … #define mmDC_GPU_TIMER_READ_CNTL … #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX … #define mmDCIO_CLOCK_CNTL … #define mmDCIO_CLOCK_CNTL_BASE_IDX … #define mmDCO_DCFE_EXT_VSYNC_CNTL … #define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX … #define mmDCIO_SOFT_RESET … #define mmDCIO_SOFT_RESET_BASE_IDX … #define mmDCIO_DPHY_SEL … #define mmDCIO_DPHY_SEL_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKA … #define mmUNIPHY_IMPCAL_LINKA_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKB … #define mmUNIPHY_IMPCAL_LINKB_BASE_IDX … #define mmUNIPHY_IMPCAL_PERIOD … #define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX … #define mmAUXP_IMPCAL … #define mmAUXP_IMPCAL_BASE_IDX … #define mmAUXN_IMPCAL … #define mmAUXN_IMPCAL_BASE_IDX … #define mmDCIO_IMPCAL_CNTL … #define mmDCIO_IMPCAL_CNTL_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_AB … #define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKC … #define mmUNIPHY_IMPCAL_LINKC_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKD … #define mmUNIPHY_IMPCAL_LINKD_BASE_IDX … #define mmDCIO_IMPCAL_CNTL_CD … #define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_CD … #define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKE … #define mmUNIPHY_IMPCAL_LINKE_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKF … #define mmUNIPHY_IMPCAL_LINKF_BASE_IDX … #define mmDCIO_IMPCAL_CNTL_EF … #define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_EF … #define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX … #define mmUNIPHYLPA_LINK_CNTL … #define mmUNIPHYLPA_LINK_CNTL_BASE_IDX … #define mmUNIPHYLPB_LINK_CNTL … #define mmUNIPHYLPB_LINK_CNTL_BASE_IDX … #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL … #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL … #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmDCIO_DPCS_TX_INTERRUPT … #define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX … #define mmDCIO_DPCS_RX_INTERRUPT … #define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX … #define mmDCIO_SEMAPHORE0 … #define mmDCIO_SEMAPHORE0_BASE_IDX … #define mmDCIO_SEMAPHORE1 … #define mmDCIO_SEMAPHORE1_BASE_IDX … #define mmDCIO_SEMAPHORE2 … #define mmDCIO_SEMAPHORE2_BASE_IDX … #define mmDCIO_SEMAPHORE3 … #define mmDCIO_SEMAPHORE3_BASE_IDX … #define mmDCIO_SEMAPHORE4 … #define mmDCIO_SEMAPHORE4_BASE_IDX … #define mmDCIO_SEMAPHORE5 … #define mmDCIO_SEMAPHORE5_BASE_IDX … #define mmDCIO_SEMAPHORE6 … #define mmDCIO_SEMAPHORE6_BASE_IDX … #define mmDCIO_SEMAPHORE7 … #define mmDCIO_SEMAPHORE7_BASE_IDX … #define mmDC_GPIO_GENERIC_MASK … #define mmDC_GPIO_GENERIC_MASK_BASE_IDX … #define mmDC_GPIO_GENERIC_A … #define mmDC_GPIO_GENERIC_A_BASE_IDX … #define mmDC_GPIO_GENERIC_EN … #define mmDC_GPIO_GENERIC_EN_BASE_IDX … #define mmDC_GPIO_GENERIC_Y … #define mmDC_GPIO_GENERIC_Y_BASE_IDX … #define mmDC_GPIO_DVODATA_MASK … #define mmDC_GPIO_DVODATA_MASK_BASE_IDX … #define mmDC_GPIO_DVODATA_A … #define mmDC_GPIO_DVODATA_A_BASE_IDX … #define mmDC_GPIO_DVODATA_EN … #define mmDC_GPIO_DVODATA_EN_BASE_IDX … #define mmDC_GPIO_DVODATA_Y … #define mmDC_GPIO_DVODATA_Y_BASE_IDX … #define mmDC_GPIO_DDC1_MASK … #define mmDC_GPIO_DDC1_MASK_BASE_IDX … #define mmDC_GPIO_DDC1_A … #define mmDC_GPIO_DDC1_A_BASE_IDX … #define mmDC_GPIO_DDC1_EN … #define mmDC_GPIO_DDC1_EN_BASE_IDX … #define mmDC_GPIO_DDC1_Y … #define mmDC_GPIO_DDC1_Y_BASE_IDX … #define mmDC_GPIO_DDC2_MASK … #define mmDC_GPIO_DDC2_MASK_BASE_IDX … #define mmDC_GPIO_DDC2_A … #define mmDC_GPIO_DDC2_A_BASE_IDX … #define mmDC_GPIO_DDC2_EN … #define mmDC_GPIO_DDC2_EN_BASE_IDX … #define mmDC_GPIO_DDC2_Y … #define mmDC_GPIO_DDC2_Y_BASE_IDX … #define mmDC_GPIO_DDC3_MASK … #define mmDC_GPIO_DDC3_MASK_BASE_IDX … #define mmDC_GPIO_DDC3_A … #define mmDC_GPIO_DDC3_A_BASE_IDX … #define mmDC_GPIO_DDC3_EN … #define mmDC_GPIO_DDC3_EN_BASE_IDX … #define mmDC_GPIO_DDC3_Y … #define mmDC_GPIO_DDC3_Y_BASE_IDX … #define mmDC_GPIO_DDC4_MASK … #define mmDC_GPIO_DDC4_MASK_BASE_IDX … #define mmDC_GPIO_DDC4_A … #define mmDC_GPIO_DDC4_A_BASE_IDX … #define mmDC_GPIO_DDC4_EN … #define mmDC_GPIO_DDC4_EN_BASE_IDX … #define mmDC_GPIO_DDC4_Y … #define mmDC_GPIO_DDC4_Y_BASE_IDX … #define mmDC_GPIO_DDC5_MASK … #define mmDC_GPIO_DDC5_MASK_BASE_IDX … #define mmDC_GPIO_DDC5_A … #define mmDC_GPIO_DDC5_A_BASE_IDX … #define mmDC_GPIO_DDC5_EN … #define mmDC_GPIO_DDC5_EN_BASE_IDX … #define mmDC_GPIO_DDC5_Y … #define mmDC_GPIO_DDC5_Y_BASE_IDX … #define mmDC_GPIO_DDC6_MASK … #define mmDC_GPIO_DDC6_MASK_BASE_IDX … #define mmDC_GPIO_DDC6_A … #define mmDC_GPIO_DDC6_A_BASE_IDX … #define mmDC_GPIO_DDC6_EN … #define mmDC_GPIO_DDC6_EN_BASE_IDX … #define mmDC_GPIO_DDC6_Y … #define mmDC_GPIO_DDC6_Y_BASE_IDX … #define mmDC_GPIO_DDCVGA_MASK … #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX … #define mmDC_GPIO_DDCVGA_A … #define mmDC_GPIO_DDCVGA_A_BASE_IDX … #define mmDC_GPIO_DDCVGA_EN … #define mmDC_GPIO_DDCVGA_EN_BASE_IDX … #define mmDC_GPIO_DDCVGA_Y … #define mmDC_GPIO_DDCVGA_Y_BASE_IDX … #define mmDC_GPIO_SYNCA_MASK … #define mmDC_GPIO_SYNCA_MASK_BASE_IDX … #define mmDC_GPIO_SYNCA_A … #define mmDC_GPIO_SYNCA_A_BASE_IDX … #define mmDC_GPIO_SYNCA_EN … #define mmDC_GPIO_SYNCA_EN_BASE_IDX … #define mmDC_GPIO_SYNCA_Y … #define mmDC_GPIO_SYNCA_Y_BASE_IDX … #define mmDC_GPIO_GENLK_MASK … #define mmDC_GPIO_GENLK_MASK_BASE_IDX … #define mmDC_GPIO_GENLK_A … #define mmDC_GPIO_GENLK_A_BASE_IDX … #define mmDC_GPIO_GENLK_EN … #define mmDC_GPIO_GENLK_EN_BASE_IDX … #define mmDC_GPIO_GENLK_Y … #define mmDC_GPIO_GENLK_Y_BASE_IDX … #define mmDC_GPIO_HPD_MASK … #define mmDC_GPIO_HPD_MASK_BASE_IDX … #define mmDC_GPIO_HPD_A … #define mmDC_GPIO_HPD_A_BASE_IDX … #define mmDC_GPIO_HPD_EN … #define mmDC_GPIO_HPD_EN_BASE_IDX … #define mmDC_GPIO_HPD_Y … #define mmDC_GPIO_HPD_Y_BASE_IDX … #define mmDC_GPIO_PWRSEQ_MASK … #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX … #define mmDC_GPIO_PWRSEQ_A … #define mmDC_GPIO_PWRSEQ_A_BASE_IDX … #define mmDC_GPIO_PWRSEQ_EN … #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX … #define mmDC_GPIO_PWRSEQ_Y … #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX … #define mmDC_GPIO_PAD_STRENGTH_1 … #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX … #define mmDC_GPIO_PAD_STRENGTH_2 … #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX … #define mmPHY_AUX_CNTL … #define mmPHY_AUX_CNTL_BASE_IDX … #define mmDC_GPIO_I2CPAD_MASK … #define mmDC_GPIO_I2CPAD_MASK_BASE_IDX … #define mmDC_GPIO_I2CPAD_A … #define mmDC_GPIO_I2CPAD_A_BASE_IDX … #define mmDC_GPIO_I2CPAD_EN … #define mmDC_GPIO_I2CPAD_EN_BASE_IDX … #define mmDC_GPIO_I2CPAD_Y … #define mmDC_GPIO_I2CPAD_Y_BASE_IDX … #define mmDC_GPIO_I2CPAD_STRENGTH … #define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX … #define mmDVO_STRENGTH_CONTROL … #define mmDVO_STRENGTH_CONTROL_BASE_IDX … #define mmDVO_VREF_CONTROL … #define mmDVO_VREF_CONTROL_BASE_IDX … #define mmDVO_SKEW_ADJUST … #define mmDVO_SKEW_ADJUST_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_MASK … #define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_A … #define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_EN … #define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_Y … #define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_STRENGTH … #define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX … #define mmDC_GPIO_TX12_EN … #define mmDC_GPIO_TX12_EN_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_0 … #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_1 … #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_2 … #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX … #define mmDC_GPIO_RXEN … #define mmDC_GPIO_RXEN_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_3 … #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_4 … #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_5 … #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX … #define mmAUXI2C_PAD_ALL_PWR_OK … #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX … #define mmDC_GPIO_PULLUPEN … #define mmDC_GPIO_PULLUPEN_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_6 … #define mmDC_GPIO_AUX_CTRL_6_BASE_IDX … #define mmBPHYC_DAC_MACRO_CNTL … #define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED0 … #define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmBPHYC_DAC_AUTO_CALIB_CONTROL … #define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED1 … #define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED2 … #define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED3 … #define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDISP_DSI_DUAL_CTRL … #define mmDISP_DSI_DUAL_CTRL_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED0 … #define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED1 … #define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED2 … #define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED3 … #define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED4 … #define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED5 … #define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED6 … #define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED7 … #define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED8 … #define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED9 … #define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED10 … #define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED11 … #define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED12 … #define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED13 … #define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED14 … #define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED15 … #define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED16 … #define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED17 … #define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED18 … #define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED19 … #define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED20 … #define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED21 … #define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED22 … #define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED23 … #define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED24 … #define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED25 … #define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED26 … #define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED27 … #define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED28 … #define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED29 … #define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED30 … #define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED31 … #define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED32 … #define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED33 … #define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED34 … #define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED35 … #define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED36 … #define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED37 … #define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED38 … #define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED39 … #define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED40 … #define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED41 … #define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED42 … #define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED43 … #define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED44 … #define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED45 … #define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED46 … #define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED47 … #define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED48 … #define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED49 … #define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED50 … #define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED51 … #define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED52 … #define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED53 … #define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED54 … #define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED55 … #define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED56 … #define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED57 … #define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED58 … #define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED59 … #define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED60 … #define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED61 … #define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED62 … #define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDPHY_MACRO_CNTL_RESERVED63 … #define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDPRX_AUX_REFERENCE_PULSE_DIV … #define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX … #define mmDPRX_AUX_CONTROL … #define mmDPRX_AUX_CONTROL_BASE_IDX … #define mmDPRX_AUX_HPD_CONTROL1 … #define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX … #define mmDPRX_AUX_HPD_CONTROL2 … #define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX … #define mmDPRX_AUX_RX_STATUS … #define mmDPRX_AUX_RX_STATUS_BASE_IDX … #define mmDPRX_AUX_RX_ERROR_MASK … #define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX … #define mmDPRX_AUX_DPHY_TX_REF_CONTROL … #define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDPRX_AUX_DPHY_TX_CONTROL … #define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDPRX_AUX_DPHY_RX_CONTROL0 … #define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDPRX_AUX_DPHY_RX_CONTROL1 … #define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDPRX_AUX_DPHY_TX_STATUS … #define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDPRX_AUX_DPHY_RX_STATUS … #define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDPRX_AUX_DMCU_HW_INT_STATUS … #define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX … #define mmDPRX_AUX_DMCU_HW_INT_ACK … #define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX … #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 … #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX … #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 … #define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX … #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 … #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX … #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 … #define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX … #define mmDPRX_AUX_AUX_BUF_INDEX … #define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX … #define mmDPRX_AUX_AUX_BUF_DATA … #define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX … #define mmDPRX_AUX_EDID_INDEX … #define mmDPRX_AUX_EDID_INDEX_BASE_IDX … #define mmDPRX_AUX_EDID_DATA … #define mmDPRX_AUX_EDID_DATA_BASE_IDX … #define mmDPRX_AUX_DPCD_INDEX1 … #define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX … #define mmDPRX_AUX_DPCD_DATA1 … #define mmDPRX_AUX_DPCD_DATA1_BASE_IDX … #define mmDPRX_AUX_DPCD_INDEX2 … #define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX … #define mmDPRX_AUX_DPCD_DATA2 … #define mmDPRX_AUX_DPCD_DATA2_BASE_IDX … #define mmDPRX_AUX_MSG_INDEX1 … #define mmDPRX_AUX_MSG_INDEX1_BASE_IDX … #define mmDPRX_AUX_MSG_DATA1 … #define mmDPRX_AUX_MSG_DATA1_BASE_IDX … #define mmDPRX_AUX_MSG_INDEX2 … #define mmDPRX_AUX_MSG_INDEX2_BASE_IDX … #define mmDPRX_AUX_MSG_DATA2 … #define mmDPRX_AUX_MSG_DATA2_BASE_IDX … #define mmDPRX_AUX_KSV_INDEX1 … #define mmDPRX_AUX_KSV_INDEX1_BASE_IDX … #define mmDPRX_AUX_KSV_DATA1 … #define mmDPRX_AUX_KSV_DATA1_BASE_IDX … #define mmDPRX_AUX_KSV_INDEX2 … #define mmDPRX_AUX_KSV_INDEX2_BASE_IDX … #define mmDPRX_AUX_KSV_DATA2 … #define mmDPRX_AUX_KSV_DATA2_BASE_IDX … #define mmDPRX_AUX_MSG_TIMEOUT_CONTROL … #define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX … #define mmDPRX_AUX_MSG_BUF_CONTROL1 … #define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX … #define mmDPRX_AUX_MSG_BUF_CONTROL2 … #define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX … #define mmDPRX_AUX_SCRATCH1 … #define mmDPRX_AUX_SCRATCH1_BASE_IDX … #define mmDPRX_AUX_SCRATCH2 … #define mmDPRX_AUX_SCRATCH2_BASE_IDX … #define mmDPRX_AUX_MSG1_PENDING … #define mmDPRX_AUX_MSG1_PENDING_BASE_IDX … #define mmDPRX_AUX_MSG2_PENDING … #define mmDPRX_AUX_MSG2_PENDING_BASE_IDX … #define mmDPRX_AUX_MSG3_PENDING … #define mmDPRX_AUX_MSG3_PENDING_BASE_IDX … #define mmDPRX_AUX_MSG4_PENDING … #define mmDPRX_AUX_MSG4_PENDING_BASE_IDX … #define mmDPRX_DPHY_DPCD_LANE_COUNT_SET … #define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET … #define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_MSTM_CTRL … #define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS … #define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX … #define mmDPRX_DPHY_READY … #define mmDPRX_DPHY_READY_BASE_IDX … #define mmDPRX_DPHY_COMMA_STATUS … #define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX … #define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED … #define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX … #define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED … #define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 … #define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 … #define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 … #define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 … #define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX … #define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL … #define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX … #define mmDPRX_DPHY_SR_ERROR_COUNT_A … #define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX … #define mmDPRX_DPHY_BS_ERROR_COUNT_A … #define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX … #define mmDPRX_DPHY_BS_ERROR_COUNT_B … #define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX … #define mmDPRX_DPHY_LANESETUP0 … #define mmDPRX_DPHY_LANESETUP0_BASE_IDX … #define mmDPRX_DPHY_LANESETUP1 … #define mmDPRX_DPHY_LANESETUP1_BASE_IDX … #define mmDPRX_DPHY_LFSRADV … #define mmDPRX_DPHY_LFSRADV_BASE_IDX … #define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT … #define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX … #define mmDPRX_DPHY_SET_ENABLE … #define mmDPRX_DPHY_SET_ENABLE_BASE_IDX … #define mmDPRX_DPHY_ECF_LSB … #define mmDPRX_DPHY_ECF_LSB_BASE_IDX … #define mmDPRX_DPHY_ECF_MSB … #define mmDPRX_DPHY_ECF_MSB_BASE_IDX … #define mmDPRX_DPHY_ENHANCED_FRAME_EN … #define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX … #define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE … #define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX … #define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA … #define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX … #define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL … #define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX … #define mmDPRX_DPHY_BYPASS … #define mmDPRX_DPHY_BYPASS_BASE_IDX … #define mmDPRX_DPHY_INT_RESET … #define mmDPRX_DPHY_INT_RESET_BASE_IDX … #define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS … #define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX … #define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS … #define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX … #define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS … #define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX … #define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS … #define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX … #define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS … #define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX … #define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS … #define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX … #define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS … #define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX … #define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS … #define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX … #define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS … #define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX … #define mmDPRX_DPHY_SPARE … #define mmDPRX_DPHY_SPARE_BASE_IDX … #define mmDCRX_GATE_DISABLE_CNTL … #define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX … #define mmDCRX_SOFT_RESET … #define mmDCRX_SOFT_RESET_BASE_IDX … #define mmDCRX_LIGHT_SLEEP_CNTL … #define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX … #define mmDCRX_DISPCLK_GATE_CNTL … #define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX … #define mmDCRX_CLK_CNTL … #define mmDCRX_CLK_CNTL_BASE_IDX … #define mmDCRX_TEST_CLK_CNTL … #define mmDCRX_TEST_CLK_CNTL_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED0 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED1 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED2 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED3 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED4 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED5 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED6 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED7 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED8 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED9 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED10 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED11 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED12 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED13 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED14 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED15 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED16 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED17 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED18 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED19 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED20 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED21 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED22 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED23 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED24 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED25 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED26 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED27 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED28 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED29 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED30 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED31 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED32 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED33 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED34 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED35 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED36 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED37 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED38 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED39 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED40 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED41 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED42 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED43 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED44 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED45 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED46 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED47 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED48 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED49 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED50 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED51 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED52 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED53 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED54 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED55 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED56 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED57 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED58 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED59 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED60 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED61 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED62 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED63 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED64 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED65 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED66 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED67 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED68 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED69 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED70 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED71 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED72 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED73 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED74 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED75 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED76 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED77 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED78 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED79 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED80 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED81 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED82 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED83 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED84 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED85 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED86 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED87 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED88 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED89 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED90 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED91 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED92 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED93 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED94 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED95 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED96 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED97 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED98 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED99 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED100 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED101 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED102 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED103 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED104 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED105 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED106 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED107 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED108 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED109 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED110 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED111 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED112 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED113 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED114 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED115 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED116 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED117 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED118 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED119 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED120 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED121 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED122 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED123 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED124 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED125 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED126 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED127 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED128 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED129 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED130 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED131 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED132 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED133 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED134 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED135 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED136 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED137 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED138 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED139 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED140 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED141 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED142 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED143 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED144 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED145 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED146 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED147 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED148 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED149 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED150 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED151 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED152 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED153 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED154 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED155 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED156 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED157 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED158 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED159 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED160 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED161 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED162 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED163 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED164 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED165 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED166 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED167 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED168 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED169 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED170 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED171 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED172 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED173 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED174 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED175 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED176 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED177 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED178 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED179 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED180 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED181 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED182 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED183 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED184 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED185 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED186 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED187 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED188 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED189 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED190 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED191 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED192 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED193 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED194 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED195 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED196 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED197 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED198 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED199 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED200 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED201 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED202 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED203 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED204 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED205 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED206 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED207 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED208 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED209 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED210 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED211 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED212 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED213 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED214 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED215 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED216 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED217 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED218 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED219 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED220 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED221 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED222 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED223 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED224 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED225 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED226 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED227 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED228 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED229 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED230 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED231 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED232 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED233 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED234 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED235 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED236 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED237 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED238 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED239 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED240 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED241 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED242 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED243 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED244 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED245 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED246 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED247 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED248 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED249 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED250 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED251 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED252 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED253 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED254 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED255 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED256 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED257 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED258 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED259 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED260 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED261 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED262 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED263 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED264 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED265 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED266 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED267 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED268 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED269 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED270 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED271 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED272 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED273 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED274 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED275 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED276 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED277 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED278 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED279 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED280 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED281 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED282 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED283 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED284 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED285 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED286 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED287 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED288 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED289 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED290 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED291 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED292 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED293 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED294 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED295 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED296 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED297 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED298 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED299 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED300 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED301 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED302 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED303 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED304 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED305 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED306 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED307 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED308 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED309 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED310 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED311 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED312 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED313 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED314 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED315 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED316 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED317 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED318 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED319 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED320 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED321 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED322 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED323 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED324 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED325 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED326 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED327 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED328 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED329 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED330 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED331 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED332 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED333 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED334 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED335 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED336 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED337 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED338 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED339 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED340 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED341 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED342 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED343 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED344 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED345 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED346 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED347 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED348 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED349 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED350 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED351 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED352 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED353 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED354 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED355 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED356 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED357 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED358 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED359 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED360 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED361 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED362 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED363 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED364 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED365 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED366 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED367 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED368 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED369 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED370 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED371 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED372 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED373 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED374 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED375 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED376 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED377 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED378 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX … #define mmDCRX_PHY_MACRO_CNTL_RESERVED379 … #define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX … #define mmI2S0_CNTL … #define mmI2S0_CNTL_BASE_IDX … #define mmSPDIF0_CNTL … #define mmSPDIF0_CNTL_BASE_IDX … #define mmI2S1_CNTL … #define mmI2S1_CNTL_BASE_IDX … #define mmSPDIF1_CNTL … #define mmSPDIF1_CNTL_BASE_IDX … #define mmI2S0_STATUS … #define mmI2S0_STATUS_BASE_IDX … #define mmI2S1_STATUS … #define mmI2S1_STATUS_BASE_IDX … #define mmI2S0_CRC_TEST_CNTL … #define mmI2S0_CRC_TEST_CNTL_BASE_IDX … #define mmI2S0_CRC_TEST_DATA_01 … #define mmI2S0_CRC_TEST_DATA_01_BASE_IDX … #define mmI2S0_CRC_TEST_DATA_23 … #define mmI2S0_CRC_TEST_DATA_23_BASE_IDX … #define mmI2S1_CRC_TEST_CNTL … #define mmI2S1_CRC_TEST_CNTL_BASE_IDX … #define mmI2S1_CRC_TEST_DATA_0 … #define mmI2S1_CRC_TEST_DATA_0_BASE_IDX … #define mmSPDIF0_CRC_TEST_CNTL … #define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX … #define mmSPDIF0_CRC_TEST_DATA_0 … #define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX … #define mmSPDIF1_CRC_TEST_CNTL … #define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX … #define mmSPDIF1_CRC_TEST_DATA … #define mmSPDIF1_CRC_TEST_DATA_BASE_IDX … #define mmCRC_I2S_CONT_REPEAT_NUM … #define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX … #define mmCRC_SPDIF_CONT_REPEAT_NUM … #define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED0 … #define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED1 … #define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED2 … #define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED3 … #define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED4 … #define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX … // addressBlock: dce_dc_azf0stream0_dispdec // base address: 0x0 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX … #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM0_AZALIA_STREAM_DATA … #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream1_dispdec // base address: 0x8 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX … #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM1_AZALIA_STREAM_DATA … #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream2_dispdec // base address: 0x10 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX … #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM2_AZALIA_STREAM_DATA … #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream3_dispdec // base address: 0x18 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX … #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM3_AZALIA_STREAM_DATA … #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream4_dispdec // base address: 0x20 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX … #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM4_AZALIA_STREAM_DATA … #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream5_dispdec // base address: 0x28 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX … #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM5_AZALIA_STREAM_DATA … #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream6_dispdec // base address: 0x30 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX … #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM6_AZALIA_STREAM_DATA … #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream7_dispdec // base address: 0x38 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX … #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM7_AZALIA_STREAM_DATA … #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint0_dispdec // base address: 0x0 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint1_dispdec // base address: 0x18 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint2_dispdec // base address: 0x30 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint3_dispdec // base address: 0x48 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint4_dispdec // base address: 0x60 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint5_dispdec // base address: 0x78 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint6_dispdec // base address: 0x90 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0endpoint7_dispdec // base address: 0xa8 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream8_dispdec // base address: 0x320 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX … #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM8_AZALIA_STREAM_DATA … #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream9_dispdec // base address: 0x328 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX … #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM9_AZALIA_STREAM_DATA … #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream10_dispdec // base address: 0x330 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX … #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM10_AZALIA_STREAM_DATA … #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream11_dispdec // base address: 0x338 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX … #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM11_AZALIA_STREAM_DATA … #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream12_dispdec // base address: 0x340 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX … #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM12_AZALIA_STREAM_DATA … #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream13_dispdec // base address: 0x348 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX … #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM13_AZALIA_STREAM_DATA … #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream14_dispdec // base address: 0x350 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX … #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM14_AZALIA_STREAM_DATA … #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0stream15_dispdec // base address: 0x358 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX … #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM15_AZALIA_STREAM_DATA … #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint0_dispdec // base address: 0x0 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint1_dispdec // base address: 0x10 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint2_dispdec // base address: 0x20 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint3_dispdec // base address: 0x30 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint4_dispdec // base address: 0x40 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint5_dispdec // base address: 0x50 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint6_dispdec // base address: 0x60 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_azf0inputendpoint7_dispdec // base address: 0x70 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_dcp0_dispdec // base address: 0x0 #define mmDCP0_GRPH_ENABLE … #define mmDCP0_GRPH_ENABLE_BASE_IDX … #define mmDCP0_GRPH_CONTROL … #define mmDCP0_GRPH_CONTROL_BASE_IDX … #define mmDCP0_GRPH_LUT_10BIT_BYPASS … #define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP0_GRPH_SWAP_CNTL … #define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP0_GRPH_PITCH … #define mmDCP0_GRPH_PITCH_BASE_IDX … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP0_GRPH_SURFACE_OFFSET_X … #define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP0_GRPH_SURFACE_OFFSET_Y … #define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP0_GRPH_X_START … #define mmDCP0_GRPH_X_START_BASE_IDX … #define mmDCP0_GRPH_Y_START … #define mmDCP0_GRPH_Y_START_BASE_IDX … #define mmDCP0_GRPH_X_END … #define mmDCP0_GRPH_X_END_BASE_IDX … #define mmDCP0_GRPH_Y_END … #define mmDCP0_GRPH_Y_END_BASE_IDX … #define mmDCP0_INPUT_GAMMA_CONTROL … #define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP0_GRPH_UPDATE … #define mmDCP0_GRPH_UPDATE_BASE_IDX … #define mmDCP0_GRPH_FLIP_CONTROL … #define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP0_GRPH_DFQ_CONTROL … #define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP0_GRPH_DFQ_STATUS … #define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP0_GRPH_INTERRUPT_STATUS … #define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP0_GRPH_INTERRUPT_CONTROL … #define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP0_GRPH_COMPRESS_PITCH … #define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP0_PRESCALE_GRPH_CONTROL … #define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP0_PRESCALE_VALUES_GRPH_R … #define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP0_PRESCALE_VALUES_GRPH_G … #define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP0_PRESCALE_VALUES_GRPH_B … #define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP0_INPUT_CSC_CONTROL … #define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP0_INPUT_CSC_C11_C12 … #define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP0_INPUT_CSC_C13_C14 … #define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP0_INPUT_CSC_C21_C22 … #define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP0_INPUT_CSC_C23_C24 … #define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP0_INPUT_CSC_C31_C32 … #define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP0_INPUT_CSC_C33_C34 … #define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP0_OUTPUT_CSC_CONTROL … #define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C11_C12 … #define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C13_C14 … #define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C21_C22 … #define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C23_C24 … #define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C31_C32 … #define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP0_OUTPUT_CSC_C33_C34 … #define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP0_DENORM_CONTROL … #define mmDCP0_DENORM_CONTROL_BASE_IDX … #define mmDCP0_OUT_ROUND_CONTROL … #define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP0_OUT_CLAMP_CONTROL_R_CR … #define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP0_OUT_CLAMP_CONTROL_G_Y … #define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP0_OUT_CLAMP_CONTROL_B_CB … #define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP0_KEY_CONTROL … #define mmDCP0_KEY_CONTROL_BASE_IDX … #define mmDCP0_KEY_RANGE_ALPHA … #define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP0_KEY_RANGE_RED … #define mmDCP0_KEY_RANGE_RED_BASE_IDX … #define mmDCP0_KEY_RANGE_GREEN … #define mmDCP0_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP0_KEY_RANGE_BLUE … #define mmDCP0_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP0_DEGAMMA_CONTROL … #define mmDCP0_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP0_GAMUT_REMAP_CONTROL … #define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C11_C12 … #define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C13_C14 … #define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C21_C22 … #define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C23_C24 … #define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C31_C32 … #define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP0_GAMUT_REMAP_C33_C34 … #define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP0_DCP_SPATIAL_DITHER_CNTL … #define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP0_DCP_RANDOM_SEEDS … #define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP0_DCP_FP_CONVERTED_FIELD … #define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP0_CUR_CONTROL … #define mmDCP0_CUR_CONTROL_BASE_IDX … #define mmDCP0_CUR_SURFACE_ADDRESS … #define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP0_CUR_SIZE … #define mmDCP0_CUR_SIZE_BASE_IDX … #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP0_CUR_POSITION … #define mmDCP0_CUR_POSITION_BASE_IDX … #define mmDCP0_CUR_HOT_SPOT … #define mmDCP0_CUR_HOT_SPOT_BASE_IDX … #define mmDCP0_CUR_COLOR1 … #define mmDCP0_CUR_COLOR1_BASE_IDX … #define mmDCP0_CUR_COLOR2 … #define mmDCP0_CUR_COLOR2_BASE_IDX … #define mmDCP0_CUR_UPDATE … #define mmDCP0_CUR_UPDATE_BASE_IDX … #define mmDCP0_CUR_REQUEST_FILTER_CNTL … #define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP0_CUR_STEREO_CONTROL … #define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP0_DC_LUT_RW_MODE … #define mmDCP0_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP0_DC_LUT_RW_INDEX … #define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP0_DC_LUT_SEQ_COLOR … #define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP0_DC_LUT_PWL_DATA … #define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP0_DC_LUT_30_COLOR … #define mmDCP0_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP0_DC_LUT_WRITE_EN_MASK … #define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP0_DC_LUT_AUTOFILL … #define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP0_DC_LUT_CONTROL … #define mmDCP0_DC_LUT_CONTROL_BASE_IDX … #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP0_DC_LUT_BLACK_OFFSET_RED … #define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP0_DC_LUT_WHITE_OFFSET_RED … #define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP0_DCP_CRC_CONTROL … #define mmDCP0_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP0_DCP_CRC_MASK … #define mmDCP0_DCP_CRC_MASK_BASE_IDX … #define mmDCP0_DCP_CRC_CURRENT … #define mmDCP0_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP0_DVMM_PTE_CONTROL … #define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP0_DCP_CRC_LAST … #define mmDCP0_DCP_CRC_LAST_BASE_IDX … #define mmDCP0_DVMM_PTE_ARB_CONTROL … #define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP0_GRPH_FLIP_RATE_CNTL … #define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP0_DCP_GSL_CONTROL … #define mmDCP0_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP0_GRPH_STEREOSYNC_FLIP … #define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP0_HW_ROTATION … #define mmDCP0_HW_ROTATION_BASE_IDX … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP0_REGAMMA_CONTROL … #define mmDCP0_REGAMMA_CONTROL_BASE_IDX … #define mmDCP0_REGAMMA_LUT_INDEX … #define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP0_REGAMMA_LUT_DATA … #define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_START_CNTL … #define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_START_CNTL … #define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP0_ALPHA_CONTROL … #define mmDCP0_ALPHA_CONTROL_BASE_IDX … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb0_dispdec // base address: 0x0 #define mmLB0_LB_DATA_FORMAT … #define mmLB0_LB_DATA_FORMAT_BASE_IDX … #define mmLB0_LB_MEMORY_CTRL … #define mmLB0_LB_MEMORY_CTRL_BASE_IDX … #define mmLB0_LB_MEMORY_SIZE_STATUS … #define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB0_LB_DESKTOP_HEIGHT … #define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB0_LB_VLINE_START_END … #define mmLB0_LB_VLINE_START_END_BASE_IDX … #define mmLB0_LB_VLINE2_START_END … #define mmLB0_LB_VLINE2_START_END_BASE_IDX … #define mmLB0_LB_V_COUNTER … #define mmLB0_LB_V_COUNTER_BASE_IDX … #define mmLB0_LB_SNAPSHOT_V_COUNTER … #define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB0_LB_INTERRUPT_MASK … #define mmLB0_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB0_LB_VLINE_STATUS … #define mmLB0_LB_VLINE_STATUS_BASE_IDX … #define mmLB0_LB_VLINE2_STATUS … #define mmLB0_LB_VLINE2_STATUS_BASE_IDX … #define mmLB0_LB_VBLANK_STATUS … #define mmLB0_LB_VBLANK_STATUS_BASE_IDX … #define mmLB0_LB_SYNC_RESET_SEL … #define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB0_LB_BLACK_KEYER_R_CR … #define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB0_LB_BLACK_KEYER_G_Y … #define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB0_LB_BLACK_KEYER_B_CB … #define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_CTRL … #define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_R_CR … #define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_G_Y … #define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_B_CB … #define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_REP_R_CR … #define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_REP_G_Y … #define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB0_LB_KEYER_COLOR_REP_B_CB … #define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB0_LB_BUFFER_LEVEL_STATUS … #define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB0_LB_BUFFER_URGENCY_CTRL … #define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB0_LB_BUFFER_URGENCY_STATUS … #define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB0_LB_BUFFER_STATUS … #define mmLB0_LB_BUFFER_STATUS_BASE_IDX … #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB0_MVP_AFR_FLIP_MODE … #define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB0_MVP_FLIP_LINE_NUM_INSERT … #define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB0_DC_MVP_LB_CONTROL … #define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe0_dispdec // base address: 0x0 #define mmDCFE0_DCFE_CLOCK_CONTROL … #define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE0_DCFE_SOFT_RESET … #define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE0_DCFE_MEM_PWR_CTRL … #define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE0_DCFE_MEM_PWR_CTRL2 … #define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE0_DCFE_MEM_PWR_STATUS … #define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE0_DCFE_MISC … #define mmDCFE0_DCFE_MISC_BASE_IDX … #define mmDCFE0_DCFE_FLUSH … #define mmDCFE0_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon3_dispdec // base address: 0x1938 #define mmDC_PERFMON3_PERFCOUNTER_CNTL … #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON3_PERFCOUNTER_STATE … #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CNTL … #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CNTL2 … #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CVALUE_LOW … #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON3_PERFMON_HI … #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON3_PERFMON_LOW … #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg0_dispdec // base address: 0x0 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG0_DPG_REPEATER_PROGRAM … #define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG0_DPG_DVMM_STATUS … #define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl0_dispdec // base address: 0x0 #define mmSCL0_SCL_COEF_RAM_SELECT … #define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL0_SCL_COEF_RAM_TAP_DATA … #define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL0_SCL_MODE … #define mmSCL0_SCL_MODE_BASE_IDX … #define mmSCL0_SCL_TAP_CONTROL … #define mmSCL0_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL0_SCL_CONTROL … #define mmSCL0_SCL_CONTROL_BASE_IDX … #define mmSCL0_SCL_BYPASS_CONTROL … #define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL0_SCL_HORZ_FILTER_CONTROL … #define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL0_SCL_HORZ_FILTER_INIT … #define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL0_SCL_VERT_FILTER_CONTROL … #define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL0_SCL_VERT_FILTER_INIT … #define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL0_SCL_VERT_FILTER_INIT_BOT … #define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL0_SCL_ROUND_OFFSET … #define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL0_SCL_UPDATE … #define mmSCL0_SCL_UPDATE_BASE_IDX … #define mmSCL0_SCL_F_SHARP_CONTROL … #define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL0_SCL_ALU_CONTROL … #define mmSCL0_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL0_VIEWPORT_START_SECONDARY … #define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL0_VIEWPORT_START … #define mmSCL0_VIEWPORT_START_BASE_IDX … #define mmSCL0_VIEWPORT_SIZE … #define mmSCL0_VIEWPORT_SIZE_BASE_IDX … #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL0_SCL_MODE_CHANGE_DET1 … #define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL0_SCL_MODE_CHANGE_DET2 … #define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL0_SCL_MODE_CHANGE_DET3 … #define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL0_SCL_MODE_CHANGE_MASK … #define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd0_dispdec // base address: 0x0 #define mmBLND0_BLND_CONTROL … #define mmBLND0_BLND_CONTROL_BASE_IDX … #define mmBLND0_BLND_SM_CONTROL2 … #define mmBLND0_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND0_BLND_CONTROL2 … #define mmBLND0_BLND_CONTROL2_BASE_IDX … #define mmBLND0_BLND_UPDATE … #define mmBLND0_BLND_UPDATE_BASE_IDX … #define mmBLND0_BLND_UNDERFLOW_INTERRUPT … #define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND0_BLND_V_UPDATE_LOCK … #define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND0_BLND_REG_UPDATE_STATUS … #define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc0_dispdec // base address: 0x0 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC0_CRTC_H_TOTAL … #define mmCRTC0_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC0_CRTC_H_BLANK_START_END … #define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC0_CRTC_H_SYNC_A … #define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC0_CRTC_H_SYNC_A_CNTL … #define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC0_CRTC_H_SYNC_B … #define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC0_CRTC_H_SYNC_B_CNTL … #define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC0_CRTC_VBI_END … #define mmCRTC0_CRTC_VBI_END_BASE_IDX … #define mmCRTC0_CRTC_V_TOTAL … #define mmCRTC0_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC0_CRTC_V_TOTAL_MIN … #define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC0_CRTC_V_TOTAL_MAX … #define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC0_CRTC_V_TOTAL_CONTROL … #define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC0_CRTC_V_BLANK_START_END … #define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC0_CRTC_V_SYNC_A … #define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC0_CRTC_V_SYNC_A_CNTL … #define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC0_CRTC_V_SYNC_B … #define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC0_CRTC_V_SYNC_B_CNTL … #define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC0_CRTC_DTMTEST_CNTL … #define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC0_CRTC_TRIGA_CNTL … #define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC0_CRTC_TRIGB_CNTL … #define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC0_CRTC_FLOW_CONTROL … #define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC0_CRTC_AVSYNC_COUNTER … #define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC0_CRTC_CONTROL … #define mmCRTC0_CRTC_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_BLANK_CONTROL … #define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_INTERLACE_CONTROL … #define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_INTERLACE_STATUS … #define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC0_CRTC_STATUS … #define mmCRTC0_CRTC_STATUS_BASE_IDX … #define mmCRTC0_CRTC_STATUS_POSITION … #define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC0_CRTC_NOM_VERT_POSITION … #define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC0_CRTC_STATUS_FRAME_COUNT … #define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC0_CRTC_STATUS_VF_COUNT … #define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC0_CRTC_STATUS_HV_COUNT … #define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC0_CRTC_COUNT_CONTROL … #define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_COUNT_RESET … #define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC0_CRTC_VERT_SYNC_CONTROL … #define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_STEREO_STATUS … #define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC0_CRTC_STEREO_CONTROL … #define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_SNAPSHOT_STATUS … #define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC0_CRTC_SNAPSHOT_CONTROL … #define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_SNAPSHOT_POSITION … #define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC0_CRTC_SNAPSHOT_FRAME … #define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC0_CRTC_START_LINE_CONTROL … #define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_INTERRUPT_CONTROL … #define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_UPDATE_LOCK … #define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC0_CRTC_TEST_PATTERN_COLOR … #define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC0_CRTC_MASTER_UPDATE_MODE … #define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC0_CRTC_MVP_STATUS … #define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC0_CRTC_MASTER_EN … #define mmCRTC0_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC0_CRTC_OVERSCAN_COLOR … #define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC0_CRTC_BLANK_DATA_COLOR … #define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC0_CRTC_BLACK_COLOR … #define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC0_CRTC_BLACK_COLOR_EXT … #define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC_CNTL … #define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC0_DATA_RG … #define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC0_CRTC_CRC0_DATA_B … #define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_CRC1_DATA_RG … #define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC0_CRTC_CRC1_DATA_B … #define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_GSL_VSYNC_GAP … #define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC0_CRTC_GSL_WINDOW … #define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC0_CRTC_GSL_CONTROL … #define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC0_CRTC_DRR_CONTROL … #define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt0_dispdec // base address: 0x0 #define mmFMT0_FMT_CLAMP_COMPONENT_R … #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_G … #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_B … #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT0_FMT_CONTROL … #define mmFMT0_FMT_CONTROL_BASE_IDX … #define mmFMT0_FMT_BIT_DEPTH_CONTROL … #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_R_SEED … #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_G_SEED … #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_B_SEED … #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT0_FMT_CLAMP_CNTL … #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT0_FMT_CRC_CNTL … #define mmFMT0_FMT_CRC_CNTL_BASE_IDX … #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT0_FMT_CRC_SIG_RED_GREEN … #define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT0_FMT_420_HBLANK_EARLY_START … #define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_dcp1_dispdec // base address: 0x800 #define mmDCP1_GRPH_ENABLE … #define mmDCP1_GRPH_ENABLE_BASE_IDX … #define mmDCP1_GRPH_CONTROL … #define mmDCP1_GRPH_CONTROL_BASE_IDX … #define mmDCP1_GRPH_LUT_10BIT_BYPASS … #define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP1_GRPH_SWAP_CNTL … #define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP1_GRPH_PITCH … #define mmDCP1_GRPH_PITCH_BASE_IDX … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP1_GRPH_SURFACE_OFFSET_X … #define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP1_GRPH_SURFACE_OFFSET_Y … #define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP1_GRPH_X_START … #define mmDCP1_GRPH_X_START_BASE_IDX … #define mmDCP1_GRPH_Y_START … #define mmDCP1_GRPH_Y_START_BASE_IDX … #define mmDCP1_GRPH_X_END … #define mmDCP1_GRPH_X_END_BASE_IDX … #define mmDCP1_GRPH_Y_END … #define mmDCP1_GRPH_Y_END_BASE_IDX … #define mmDCP1_INPUT_GAMMA_CONTROL … #define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP1_GRPH_UPDATE … #define mmDCP1_GRPH_UPDATE_BASE_IDX … #define mmDCP1_GRPH_FLIP_CONTROL … #define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP1_GRPH_DFQ_CONTROL … #define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP1_GRPH_DFQ_STATUS … #define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP1_GRPH_INTERRUPT_STATUS … #define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP1_GRPH_INTERRUPT_CONTROL … #define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP1_GRPH_COMPRESS_PITCH … #define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP1_PRESCALE_GRPH_CONTROL … #define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP1_PRESCALE_VALUES_GRPH_R … #define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP1_PRESCALE_VALUES_GRPH_G … #define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP1_PRESCALE_VALUES_GRPH_B … #define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP1_INPUT_CSC_CONTROL … #define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP1_INPUT_CSC_C11_C12 … #define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP1_INPUT_CSC_C13_C14 … #define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP1_INPUT_CSC_C21_C22 … #define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP1_INPUT_CSC_C23_C24 … #define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP1_INPUT_CSC_C31_C32 … #define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP1_INPUT_CSC_C33_C34 … #define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP1_OUTPUT_CSC_CONTROL … #define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C11_C12 … #define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C13_C14 … #define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C21_C22 … #define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C23_C24 … #define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C31_C32 … #define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP1_OUTPUT_CSC_C33_C34 … #define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP1_DENORM_CONTROL … #define mmDCP1_DENORM_CONTROL_BASE_IDX … #define mmDCP1_OUT_ROUND_CONTROL … #define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP1_OUT_CLAMP_CONTROL_R_CR … #define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP1_OUT_CLAMP_CONTROL_G_Y … #define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP1_OUT_CLAMP_CONTROL_B_CB … #define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP1_KEY_CONTROL … #define mmDCP1_KEY_CONTROL_BASE_IDX … #define mmDCP1_KEY_RANGE_ALPHA … #define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP1_KEY_RANGE_RED … #define mmDCP1_KEY_RANGE_RED_BASE_IDX … #define mmDCP1_KEY_RANGE_GREEN … #define mmDCP1_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP1_KEY_RANGE_BLUE … #define mmDCP1_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP1_DEGAMMA_CONTROL … #define mmDCP1_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP1_GAMUT_REMAP_CONTROL … #define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C11_C12 … #define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C13_C14 … #define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C21_C22 … #define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C23_C24 … #define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C31_C32 … #define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP1_GAMUT_REMAP_C33_C34 … #define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP1_DCP_SPATIAL_DITHER_CNTL … #define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP1_DCP_RANDOM_SEEDS … #define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP1_DCP_FP_CONVERTED_FIELD … #define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP1_CUR_CONTROL … #define mmDCP1_CUR_CONTROL_BASE_IDX … #define mmDCP1_CUR_SURFACE_ADDRESS … #define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP1_CUR_SIZE … #define mmDCP1_CUR_SIZE_BASE_IDX … #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP1_CUR_POSITION … #define mmDCP1_CUR_POSITION_BASE_IDX … #define mmDCP1_CUR_HOT_SPOT … #define mmDCP1_CUR_HOT_SPOT_BASE_IDX … #define mmDCP1_CUR_COLOR1 … #define mmDCP1_CUR_COLOR1_BASE_IDX … #define mmDCP1_CUR_COLOR2 … #define mmDCP1_CUR_COLOR2_BASE_IDX … #define mmDCP1_CUR_UPDATE … #define mmDCP1_CUR_UPDATE_BASE_IDX … #define mmDCP1_CUR_REQUEST_FILTER_CNTL … #define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP1_CUR_STEREO_CONTROL … #define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP1_DC_LUT_RW_MODE … #define mmDCP1_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP1_DC_LUT_RW_INDEX … #define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP1_DC_LUT_SEQ_COLOR … #define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP1_DC_LUT_PWL_DATA … #define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP1_DC_LUT_30_COLOR … #define mmDCP1_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP1_DC_LUT_WRITE_EN_MASK … #define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP1_DC_LUT_AUTOFILL … #define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP1_DC_LUT_CONTROL … #define mmDCP1_DC_LUT_CONTROL_BASE_IDX … #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP1_DC_LUT_BLACK_OFFSET_RED … #define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP1_DC_LUT_WHITE_OFFSET_RED … #define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP1_DCP_CRC_CONTROL … #define mmDCP1_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP1_DCP_CRC_MASK … #define mmDCP1_DCP_CRC_MASK_BASE_IDX … #define mmDCP1_DCP_CRC_CURRENT … #define mmDCP1_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP1_DVMM_PTE_CONTROL … #define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP1_DCP_CRC_LAST … #define mmDCP1_DCP_CRC_LAST_BASE_IDX … #define mmDCP1_DVMM_PTE_ARB_CONTROL … #define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP1_GRPH_FLIP_RATE_CNTL … #define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP1_DCP_GSL_CONTROL … #define mmDCP1_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP1_GRPH_STEREOSYNC_FLIP … #define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP1_HW_ROTATION … #define mmDCP1_HW_ROTATION_BASE_IDX … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP1_REGAMMA_CONTROL … #define mmDCP1_REGAMMA_CONTROL_BASE_IDX … #define mmDCP1_REGAMMA_LUT_INDEX … #define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP1_REGAMMA_LUT_DATA … #define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_START_CNTL … #define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_START_CNTL … #define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP1_ALPHA_CONTROL … #define mmDCP1_ALPHA_CONTROL_BASE_IDX … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb1_dispdec // base address: 0x800 #define mmLB1_LB_DATA_FORMAT … #define mmLB1_LB_DATA_FORMAT_BASE_IDX … #define mmLB1_LB_MEMORY_CTRL … #define mmLB1_LB_MEMORY_CTRL_BASE_IDX … #define mmLB1_LB_MEMORY_SIZE_STATUS … #define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB1_LB_DESKTOP_HEIGHT … #define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB1_LB_VLINE_START_END … #define mmLB1_LB_VLINE_START_END_BASE_IDX … #define mmLB1_LB_VLINE2_START_END … #define mmLB1_LB_VLINE2_START_END_BASE_IDX … #define mmLB1_LB_V_COUNTER … #define mmLB1_LB_V_COUNTER_BASE_IDX … #define mmLB1_LB_SNAPSHOT_V_COUNTER … #define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB1_LB_INTERRUPT_MASK … #define mmLB1_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB1_LB_VLINE_STATUS … #define mmLB1_LB_VLINE_STATUS_BASE_IDX … #define mmLB1_LB_VLINE2_STATUS … #define mmLB1_LB_VLINE2_STATUS_BASE_IDX … #define mmLB1_LB_VBLANK_STATUS … #define mmLB1_LB_VBLANK_STATUS_BASE_IDX … #define mmLB1_LB_SYNC_RESET_SEL … #define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB1_LB_BLACK_KEYER_R_CR … #define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB1_LB_BLACK_KEYER_G_Y … #define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB1_LB_BLACK_KEYER_B_CB … #define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_CTRL … #define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_R_CR … #define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_G_Y … #define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_B_CB … #define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_REP_R_CR … #define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_REP_G_Y … #define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB1_LB_KEYER_COLOR_REP_B_CB … #define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB1_LB_BUFFER_LEVEL_STATUS … #define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB1_LB_BUFFER_URGENCY_CTRL … #define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB1_LB_BUFFER_URGENCY_STATUS … #define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB1_LB_BUFFER_STATUS … #define mmLB1_LB_BUFFER_STATUS_BASE_IDX … #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB1_MVP_AFR_FLIP_MODE … #define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB1_MVP_FLIP_LINE_NUM_INSERT … #define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB1_DC_MVP_LB_CONTROL … #define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe1_dispdec // base address: 0x800 #define mmDCFE1_DCFE_CLOCK_CONTROL … #define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE1_DCFE_SOFT_RESET … #define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE1_DCFE_MEM_PWR_CTRL … #define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE1_DCFE_MEM_PWR_CTRL2 … #define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE1_DCFE_MEM_PWR_STATUS … #define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE1_DCFE_MISC … #define mmDCFE1_DCFE_MISC_BASE_IDX … #define mmDCFE1_DCFE_FLUSH … #define mmDCFE1_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon4_dispdec // base address: 0x2138 #define mmDC_PERFMON4_PERFCOUNTER_CNTL … #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON4_PERFCOUNTER_STATE … #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CNTL … #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CNTL2 … #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CVALUE_LOW … #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON4_PERFMON_HI … #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON4_PERFMON_LOW … #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg1_dispdec // base address: 0x800 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG1_DPG_REPEATER_PROGRAM … #define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG1_DPG_DVMM_STATUS … #define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl1_dispdec // base address: 0x800 #define mmSCL1_SCL_COEF_RAM_SELECT … #define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL1_SCL_COEF_RAM_TAP_DATA … #define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL1_SCL_MODE … #define mmSCL1_SCL_MODE_BASE_IDX … #define mmSCL1_SCL_TAP_CONTROL … #define mmSCL1_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL1_SCL_CONTROL … #define mmSCL1_SCL_CONTROL_BASE_IDX … #define mmSCL1_SCL_BYPASS_CONTROL … #define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL1_SCL_HORZ_FILTER_CONTROL … #define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL1_SCL_HORZ_FILTER_INIT … #define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL1_SCL_VERT_FILTER_CONTROL … #define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL1_SCL_VERT_FILTER_INIT … #define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL1_SCL_VERT_FILTER_INIT_BOT … #define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL1_SCL_ROUND_OFFSET … #define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL1_SCL_UPDATE … #define mmSCL1_SCL_UPDATE_BASE_IDX … #define mmSCL1_SCL_F_SHARP_CONTROL … #define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL1_SCL_ALU_CONTROL … #define mmSCL1_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL1_VIEWPORT_START_SECONDARY … #define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL1_VIEWPORT_START … #define mmSCL1_VIEWPORT_START_BASE_IDX … #define mmSCL1_VIEWPORT_SIZE … #define mmSCL1_VIEWPORT_SIZE_BASE_IDX … #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL1_SCL_MODE_CHANGE_DET1 … #define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL1_SCL_MODE_CHANGE_DET2 … #define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL1_SCL_MODE_CHANGE_DET3 … #define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL1_SCL_MODE_CHANGE_MASK … #define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd1_dispdec // base address: 0x800 #define mmBLND1_BLND_CONTROL … #define mmBLND1_BLND_CONTROL_BASE_IDX … #define mmBLND1_BLND_SM_CONTROL2 … #define mmBLND1_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND1_BLND_CONTROL2 … #define mmBLND1_BLND_CONTROL2_BASE_IDX … #define mmBLND1_BLND_UPDATE … #define mmBLND1_BLND_UPDATE_BASE_IDX … #define mmBLND1_BLND_UNDERFLOW_INTERRUPT … #define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND1_BLND_V_UPDATE_LOCK … #define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND1_BLND_REG_UPDATE_STATUS … #define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc1_dispdec // base address: 0x800 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC1_CRTC_H_TOTAL … #define mmCRTC1_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC1_CRTC_H_BLANK_START_END … #define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC1_CRTC_H_SYNC_A … #define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC1_CRTC_H_SYNC_A_CNTL … #define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC1_CRTC_H_SYNC_B … #define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC1_CRTC_H_SYNC_B_CNTL … #define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC1_CRTC_VBI_END … #define mmCRTC1_CRTC_VBI_END_BASE_IDX … #define mmCRTC1_CRTC_V_TOTAL … #define mmCRTC1_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC1_CRTC_V_TOTAL_MIN … #define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC1_CRTC_V_TOTAL_MAX … #define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC1_CRTC_V_TOTAL_CONTROL … #define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC1_CRTC_V_BLANK_START_END … #define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC1_CRTC_V_SYNC_A … #define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC1_CRTC_V_SYNC_A_CNTL … #define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC1_CRTC_V_SYNC_B … #define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC1_CRTC_V_SYNC_B_CNTL … #define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC1_CRTC_DTMTEST_CNTL … #define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC1_CRTC_TRIGA_CNTL … #define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC1_CRTC_TRIGB_CNTL … #define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC1_CRTC_FLOW_CONTROL … #define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC1_CRTC_AVSYNC_COUNTER … #define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC1_CRTC_CONTROL … #define mmCRTC1_CRTC_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_BLANK_CONTROL … #define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_INTERLACE_CONTROL … #define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_INTERLACE_STATUS … #define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC1_CRTC_STATUS … #define mmCRTC1_CRTC_STATUS_BASE_IDX … #define mmCRTC1_CRTC_STATUS_POSITION … #define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC1_CRTC_NOM_VERT_POSITION … #define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC1_CRTC_STATUS_FRAME_COUNT … #define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC1_CRTC_STATUS_VF_COUNT … #define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC1_CRTC_STATUS_HV_COUNT … #define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC1_CRTC_COUNT_CONTROL … #define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_COUNT_RESET … #define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC1_CRTC_VERT_SYNC_CONTROL … #define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_STEREO_STATUS … #define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC1_CRTC_STEREO_CONTROL … #define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_SNAPSHOT_STATUS … #define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC1_CRTC_SNAPSHOT_CONTROL … #define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_SNAPSHOT_POSITION … #define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC1_CRTC_SNAPSHOT_FRAME … #define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC1_CRTC_START_LINE_CONTROL … #define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_INTERRUPT_CONTROL … #define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_UPDATE_LOCK … #define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC1_CRTC_TEST_PATTERN_COLOR … #define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC1_CRTC_MASTER_UPDATE_MODE … #define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC1_CRTC_MVP_STATUS … #define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC1_CRTC_MASTER_EN … #define mmCRTC1_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC1_CRTC_OVERSCAN_COLOR … #define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC1_CRTC_BLANK_DATA_COLOR … #define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC1_CRTC_BLACK_COLOR … #define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC1_CRTC_BLACK_COLOR_EXT … #define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC_CNTL … #define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC0_DATA_RG … #define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC1_CRTC_CRC0_DATA_B … #define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_CRC1_DATA_RG … #define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC1_CRTC_CRC1_DATA_B … #define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_GSL_VSYNC_GAP … #define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC1_CRTC_GSL_WINDOW … #define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC1_CRTC_GSL_CONTROL … #define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC1_CRTC_DRR_CONTROL … #define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt1_dispdec // base address: 0x800 #define mmFMT1_FMT_CLAMP_COMPONENT_R … #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_G … #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_B … #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT1_FMT_CONTROL … #define mmFMT1_FMT_CONTROL_BASE_IDX … #define mmFMT1_FMT_BIT_DEPTH_CONTROL … #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_R_SEED … #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_G_SEED … #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_B_SEED … #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT1_FMT_CLAMP_CNTL … #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT1_FMT_CRC_CNTL … #define mmFMT1_FMT_CRC_CNTL_BASE_IDX … #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT1_FMT_CRC_SIG_RED_GREEN … #define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT1_FMT_420_HBLANK_EARLY_START … #define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_dcp2_dispdec // base address: 0x1000 #define mmDCP2_GRPH_ENABLE … #define mmDCP2_GRPH_ENABLE_BASE_IDX … #define mmDCP2_GRPH_CONTROL … #define mmDCP2_GRPH_CONTROL_BASE_IDX … #define mmDCP2_GRPH_LUT_10BIT_BYPASS … #define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP2_GRPH_SWAP_CNTL … #define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP2_GRPH_PITCH … #define mmDCP2_GRPH_PITCH_BASE_IDX … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP2_GRPH_SURFACE_OFFSET_X … #define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP2_GRPH_SURFACE_OFFSET_Y … #define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP2_GRPH_X_START … #define mmDCP2_GRPH_X_START_BASE_IDX … #define mmDCP2_GRPH_Y_START … #define mmDCP2_GRPH_Y_START_BASE_IDX … #define mmDCP2_GRPH_X_END … #define mmDCP2_GRPH_X_END_BASE_IDX … #define mmDCP2_GRPH_Y_END … #define mmDCP2_GRPH_Y_END_BASE_IDX … #define mmDCP2_INPUT_GAMMA_CONTROL … #define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP2_GRPH_UPDATE … #define mmDCP2_GRPH_UPDATE_BASE_IDX … #define mmDCP2_GRPH_FLIP_CONTROL … #define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP2_GRPH_DFQ_CONTROL … #define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP2_GRPH_DFQ_STATUS … #define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP2_GRPH_INTERRUPT_STATUS … #define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP2_GRPH_INTERRUPT_CONTROL … #define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP2_GRPH_COMPRESS_PITCH … #define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP2_PRESCALE_GRPH_CONTROL … #define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP2_PRESCALE_VALUES_GRPH_R … #define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP2_PRESCALE_VALUES_GRPH_G … #define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP2_PRESCALE_VALUES_GRPH_B … #define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP2_INPUT_CSC_CONTROL … #define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP2_INPUT_CSC_C11_C12 … #define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP2_INPUT_CSC_C13_C14 … #define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP2_INPUT_CSC_C21_C22 … #define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP2_INPUT_CSC_C23_C24 … #define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP2_INPUT_CSC_C31_C32 … #define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP2_INPUT_CSC_C33_C34 … #define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP2_OUTPUT_CSC_CONTROL … #define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C11_C12 … #define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C13_C14 … #define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C21_C22 … #define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C23_C24 … #define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C31_C32 … #define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP2_OUTPUT_CSC_C33_C34 … #define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP2_DENORM_CONTROL … #define mmDCP2_DENORM_CONTROL_BASE_IDX … #define mmDCP2_OUT_ROUND_CONTROL … #define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP2_OUT_CLAMP_CONTROL_R_CR … #define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP2_OUT_CLAMP_CONTROL_G_Y … #define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP2_OUT_CLAMP_CONTROL_B_CB … #define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP2_KEY_CONTROL … #define mmDCP2_KEY_CONTROL_BASE_IDX … #define mmDCP2_KEY_RANGE_ALPHA … #define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP2_KEY_RANGE_RED … #define mmDCP2_KEY_RANGE_RED_BASE_IDX … #define mmDCP2_KEY_RANGE_GREEN … #define mmDCP2_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP2_KEY_RANGE_BLUE … #define mmDCP2_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP2_DEGAMMA_CONTROL … #define mmDCP2_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP2_GAMUT_REMAP_CONTROL … #define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C11_C12 … #define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C13_C14 … #define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C21_C22 … #define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C23_C24 … #define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C31_C32 … #define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP2_GAMUT_REMAP_C33_C34 … #define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP2_DCP_SPATIAL_DITHER_CNTL … #define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP2_DCP_RANDOM_SEEDS … #define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP2_DCP_FP_CONVERTED_FIELD … #define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP2_CUR_CONTROL … #define mmDCP2_CUR_CONTROL_BASE_IDX … #define mmDCP2_CUR_SURFACE_ADDRESS … #define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP2_CUR_SIZE … #define mmDCP2_CUR_SIZE_BASE_IDX … #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP2_CUR_POSITION … #define mmDCP2_CUR_POSITION_BASE_IDX … #define mmDCP2_CUR_HOT_SPOT … #define mmDCP2_CUR_HOT_SPOT_BASE_IDX … #define mmDCP2_CUR_COLOR1 … #define mmDCP2_CUR_COLOR1_BASE_IDX … #define mmDCP2_CUR_COLOR2 … #define mmDCP2_CUR_COLOR2_BASE_IDX … #define mmDCP2_CUR_UPDATE … #define mmDCP2_CUR_UPDATE_BASE_IDX … #define mmDCP2_CUR_REQUEST_FILTER_CNTL … #define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP2_CUR_STEREO_CONTROL … #define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP2_DC_LUT_RW_MODE … #define mmDCP2_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP2_DC_LUT_RW_INDEX … #define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP2_DC_LUT_SEQ_COLOR … #define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP2_DC_LUT_PWL_DATA … #define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP2_DC_LUT_30_COLOR … #define mmDCP2_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP2_DC_LUT_WRITE_EN_MASK … #define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP2_DC_LUT_AUTOFILL … #define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP2_DC_LUT_CONTROL … #define mmDCP2_DC_LUT_CONTROL_BASE_IDX … #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP2_DC_LUT_BLACK_OFFSET_RED … #define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP2_DC_LUT_WHITE_OFFSET_RED … #define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP2_DCP_CRC_CONTROL … #define mmDCP2_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP2_DCP_CRC_MASK … #define mmDCP2_DCP_CRC_MASK_BASE_IDX … #define mmDCP2_DCP_CRC_CURRENT … #define mmDCP2_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP2_DVMM_PTE_CONTROL … #define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP2_DCP_CRC_LAST … #define mmDCP2_DCP_CRC_LAST_BASE_IDX … #define mmDCP2_DVMM_PTE_ARB_CONTROL … #define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP2_GRPH_FLIP_RATE_CNTL … #define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP2_DCP_GSL_CONTROL … #define mmDCP2_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP2_GRPH_STEREOSYNC_FLIP … #define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP2_HW_ROTATION … #define mmDCP2_HW_ROTATION_BASE_IDX … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP2_REGAMMA_CONTROL … #define mmDCP2_REGAMMA_CONTROL_BASE_IDX … #define mmDCP2_REGAMMA_LUT_INDEX … #define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP2_REGAMMA_LUT_DATA … #define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_START_CNTL … #define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_START_CNTL … #define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP2_ALPHA_CONTROL … #define mmDCP2_ALPHA_CONTROL_BASE_IDX … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb2_dispdec // base address: 0x1000 #define mmLB2_LB_DATA_FORMAT … #define mmLB2_LB_DATA_FORMAT_BASE_IDX … #define mmLB2_LB_MEMORY_CTRL … #define mmLB2_LB_MEMORY_CTRL_BASE_IDX … #define mmLB2_LB_MEMORY_SIZE_STATUS … #define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB2_LB_DESKTOP_HEIGHT … #define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB2_LB_VLINE_START_END … #define mmLB2_LB_VLINE_START_END_BASE_IDX … #define mmLB2_LB_VLINE2_START_END … #define mmLB2_LB_VLINE2_START_END_BASE_IDX … #define mmLB2_LB_V_COUNTER … #define mmLB2_LB_V_COUNTER_BASE_IDX … #define mmLB2_LB_SNAPSHOT_V_COUNTER … #define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB2_LB_INTERRUPT_MASK … #define mmLB2_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB2_LB_VLINE_STATUS … #define mmLB2_LB_VLINE_STATUS_BASE_IDX … #define mmLB2_LB_VLINE2_STATUS … #define mmLB2_LB_VLINE2_STATUS_BASE_IDX … #define mmLB2_LB_VBLANK_STATUS … #define mmLB2_LB_VBLANK_STATUS_BASE_IDX … #define mmLB2_LB_SYNC_RESET_SEL … #define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB2_LB_BLACK_KEYER_R_CR … #define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB2_LB_BLACK_KEYER_G_Y … #define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB2_LB_BLACK_KEYER_B_CB … #define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_CTRL … #define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_R_CR … #define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_G_Y … #define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_B_CB … #define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_REP_R_CR … #define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_REP_G_Y … #define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB2_LB_KEYER_COLOR_REP_B_CB … #define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB2_LB_BUFFER_LEVEL_STATUS … #define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB2_LB_BUFFER_URGENCY_CTRL … #define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB2_LB_BUFFER_URGENCY_STATUS … #define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB2_LB_BUFFER_STATUS … #define mmLB2_LB_BUFFER_STATUS_BASE_IDX … #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB2_MVP_AFR_FLIP_MODE … #define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB2_MVP_FLIP_LINE_NUM_INSERT … #define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB2_DC_MVP_LB_CONTROL … #define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe2_dispdec // base address: 0x1000 #define mmDCFE2_DCFE_CLOCK_CONTROL … #define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE2_DCFE_SOFT_RESET … #define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE2_DCFE_MEM_PWR_CTRL … #define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE2_DCFE_MEM_PWR_CTRL2 … #define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE2_DCFE_MEM_PWR_STATUS … #define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE2_DCFE_MISC … #define mmDCFE2_DCFE_MISC_BASE_IDX … #define mmDCFE2_DCFE_FLUSH … #define mmDCFE2_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon5_dispdec // base address: 0x2938 #define mmDC_PERFMON5_PERFCOUNTER_CNTL … #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON5_PERFCOUNTER_STATE … #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CNTL … #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CNTL2 … #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CVALUE_LOW … #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON5_PERFMON_HI … #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON5_PERFMON_LOW … #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg2_dispdec // base address: 0x1000 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG2_DPG_REPEATER_PROGRAM … #define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG2_DPG_DVMM_STATUS … #define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl2_dispdec // base address: 0x1000 #define mmSCL2_SCL_COEF_RAM_SELECT … #define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL2_SCL_COEF_RAM_TAP_DATA … #define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL2_SCL_MODE … #define mmSCL2_SCL_MODE_BASE_IDX … #define mmSCL2_SCL_TAP_CONTROL … #define mmSCL2_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL2_SCL_CONTROL … #define mmSCL2_SCL_CONTROL_BASE_IDX … #define mmSCL2_SCL_BYPASS_CONTROL … #define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL2_SCL_HORZ_FILTER_CONTROL … #define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL2_SCL_HORZ_FILTER_INIT … #define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL2_SCL_VERT_FILTER_CONTROL … #define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL2_SCL_VERT_FILTER_INIT … #define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL2_SCL_VERT_FILTER_INIT_BOT … #define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL2_SCL_ROUND_OFFSET … #define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL2_SCL_UPDATE … #define mmSCL2_SCL_UPDATE_BASE_IDX … #define mmSCL2_SCL_F_SHARP_CONTROL … #define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL2_SCL_ALU_CONTROL … #define mmSCL2_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL2_VIEWPORT_START_SECONDARY … #define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL2_VIEWPORT_START … #define mmSCL2_VIEWPORT_START_BASE_IDX … #define mmSCL2_VIEWPORT_SIZE … #define mmSCL2_VIEWPORT_SIZE_BASE_IDX … #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL2_SCL_MODE_CHANGE_DET1 … #define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL2_SCL_MODE_CHANGE_DET2 … #define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL2_SCL_MODE_CHANGE_DET3 … #define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL2_SCL_MODE_CHANGE_MASK … #define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd2_dispdec // base address: 0x1000 #define mmBLND2_BLND_CONTROL … #define mmBLND2_BLND_CONTROL_BASE_IDX … #define mmBLND2_BLND_SM_CONTROL2 … #define mmBLND2_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND2_BLND_CONTROL2 … #define mmBLND2_BLND_CONTROL2_BASE_IDX … #define mmBLND2_BLND_UPDATE … #define mmBLND2_BLND_UPDATE_BASE_IDX … #define mmBLND2_BLND_UNDERFLOW_INTERRUPT … #define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND2_BLND_V_UPDATE_LOCK … #define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND2_BLND_REG_UPDATE_STATUS … #define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc2_dispdec // base address: 0x1000 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC2_CRTC_H_TOTAL … #define mmCRTC2_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC2_CRTC_H_BLANK_START_END … #define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC2_CRTC_H_SYNC_A … #define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC2_CRTC_H_SYNC_A_CNTL … #define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC2_CRTC_H_SYNC_B … #define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC2_CRTC_H_SYNC_B_CNTL … #define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC2_CRTC_VBI_END … #define mmCRTC2_CRTC_VBI_END_BASE_IDX … #define mmCRTC2_CRTC_V_TOTAL … #define mmCRTC2_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC2_CRTC_V_TOTAL_MIN … #define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC2_CRTC_V_TOTAL_MAX … #define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC2_CRTC_V_TOTAL_CONTROL … #define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC2_CRTC_V_BLANK_START_END … #define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC2_CRTC_V_SYNC_A … #define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC2_CRTC_V_SYNC_A_CNTL … #define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC2_CRTC_V_SYNC_B … #define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC2_CRTC_V_SYNC_B_CNTL … #define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC2_CRTC_DTMTEST_CNTL … #define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC2_CRTC_TRIGA_CNTL … #define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC2_CRTC_TRIGB_CNTL … #define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC2_CRTC_FLOW_CONTROL … #define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC2_CRTC_AVSYNC_COUNTER … #define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC2_CRTC_CONTROL … #define mmCRTC2_CRTC_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_BLANK_CONTROL … #define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_INTERLACE_CONTROL … #define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_INTERLACE_STATUS … #define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC2_CRTC_STATUS … #define mmCRTC2_CRTC_STATUS_BASE_IDX … #define mmCRTC2_CRTC_STATUS_POSITION … #define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC2_CRTC_NOM_VERT_POSITION … #define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC2_CRTC_STATUS_FRAME_COUNT … #define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC2_CRTC_STATUS_VF_COUNT … #define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC2_CRTC_STATUS_HV_COUNT … #define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC2_CRTC_COUNT_CONTROL … #define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_COUNT_RESET … #define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC2_CRTC_VERT_SYNC_CONTROL … #define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_STEREO_STATUS … #define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC2_CRTC_STEREO_CONTROL … #define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_SNAPSHOT_STATUS … #define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC2_CRTC_SNAPSHOT_CONTROL … #define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_SNAPSHOT_POSITION … #define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC2_CRTC_SNAPSHOT_FRAME … #define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC2_CRTC_START_LINE_CONTROL … #define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_INTERRUPT_CONTROL … #define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_UPDATE_LOCK … #define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC2_CRTC_TEST_PATTERN_COLOR … #define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC2_CRTC_MASTER_UPDATE_MODE … #define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC2_CRTC_MVP_STATUS … #define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC2_CRTC_MASTER_EN … #define mmCRTC2_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC2_CRTC_OVERSCAN_COLOR … #define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC2_CRTC_BLANK_DATA_COLOR … #define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC2_CRTC_BLACK_COLOR … #define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC2_CRTC_BLACK_COLOR_EXT … #define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC_CNTL … #define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC0_DATA_RG … #define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC2_CRTC_CRC0_DATA_B … #define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_CRC1_DATA_RG … #define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC2_CRTC_CRC1_DATA_B … #define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_GSL_VSYNC_GAP … #define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC2_CRTC_GSL_WINDOW … #define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC2_CRTC_GSL_CONTROL … #define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC2_CRTC_DRR_CONTROL … #define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt2_dispdec // base address: 0x1000 #define mmFMT2_FMT_CLAMP_COMPONENT_R … #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT2_FMT_CLAMP_COMPONENT_G … #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT2_FMT_CLAMP_COMPONENT_B … #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT2_FMT_DYNAMIC_EXP_CNTL … #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT2_FMT_CONTROL … #define mmFMT2_FMT_CONTROL_BASE_IDX … #define mmFMT2_FMT_BIT_DEPTH_CONTROL … #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_R_SEED … #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_G_SEED … #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_B_SEED … #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT2_FMT_CLAMP_CNTL … #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT2_FMT_CRC_CNTL … #define mmFMT2_FMT_CRC_CNTL_BASE_IDX … #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT2_FMT_CRC_SIG_RED_GREEN … #define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT2_FMT_420_HBLANK_EARLY_START … #define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_dcp3_dispdec // base address: 0x1800 #define mmDCP3_GRPH_ENABLE … #define mmDCP3_GRPH_ENABLE_BASE_IDX … #define mmDCP3_GRPH_CONTROL … #define mmDCP3_GRPH_CONTROL_BASE_IDX … #define mmDCP3_GRPH_LUT_10BIT_BYPASS … #define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP3_GRPH_SWAP_CNTL … #define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP3_GRPH_PITCH … #define mmDCP3_GRPH_PITCH_BASE_IDX … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP3_GRPH_SURFACE_OFFSET_X … #define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP3_GRPH_SURFACE_OFFSET_Y … #define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP3_GRPH_X_START … #define mmDCP3_GRPH_X_START_BASE_IDX … #define mmDCP3_GRPH_Y_START … #define mmDCP3_GRPH_Y_START_BASE_IDX … #define mmDCP3_GRPH_X_END … #define mmDCP3_GRPH_X_END_BASE_IDX … #define mmDCP3_GRPH_Y_END … #define mmDCP3_GRPH_Y_END_BASE_IDX … #define mmDCP3_INPUT_GAMMA_CONTROL … #define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP3_GRPH_UPDATE … #define mmDCP3_GRPH_UPDATE_BASE_IDX … #define mmDCP3_GRPH_FLIP_CONTROL … #define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP3_GRPH_DFQ_CONTROL … #define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP3_GRPH_DFQ_STATUS … #define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP3_GRPH_INTERRUPT_STATUS … #define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP3_GRPH_INTERRUPT_CONTROL … #define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP3_GRPH_COMPRESS_PITCH … #define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP3_PRESCALE_GRPH_CONTROL … #define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP3_PRESCALE_VALUES_GRPH_R … #define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP3_PRESCALE_VALUES_GRPH_G … #define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP3_PRESCALE_VALUES_GRPH_B … #define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP3_INPUT_CSC_CONTROL … #define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP3_INPUT_CSC_C11_C12 … #define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP3_INPUT_CSC_C13_C14 … #define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP3_INPUT_CSC_C21_C22 … #define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP3_INPUT_CSC_C23_C24 … #define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP3_INPUT_CSC_C31_C32 … #define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP3_INPUT_CSC_C33_C34 … #define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP3_OUTPUT_CSC_CONTROL … #define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C11_C12 … #define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C13_C14 … #define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C21_C22 … #define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C23_C24 … #define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C31_C32 … #define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP3_OUTPUT_CSC_C33_C34 … #define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP3_DENORM_CONTROL … #define mmDCP3_DENORM_CONTROL_BASE_IDX … #define mmDCP3_OUT_ROUND_CONTROL … #define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP3_OUT_CLAMP_CONTROL_R_CR … #define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP3_OUT_CLAMP_CONTROL_G_Y … #define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP3_OUT_CLAMP_CONTROL_B_CB … #define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP3_KEY_CONTROL … #define mmDCP3_KEY_CONTROL_BASE_IDX … #define mmDCP3_KEY_RANGE_ALPHA … #define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP3_KEY_RANGE_RED … #define mmDCP3_KEY_RANGE_RED_BASE_IDX … #define mmDCP3_KEY_RANGE_GREEN … #define mmDCP3_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP3_KEY_RANGE_BLUE … #define mmDCP3_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP3_DEGAMMA_CONTROL … #define mmDCP3_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP3_GAMUT_REMAP_CONTROL … #define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C11_C12 … #define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C13_C14 … #define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C21_C22 … #define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C23_C24 … #define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C31_C32 … #define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP3_GAMUT_REMAP_C33_C34 … #define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP3_DCP_SPATIAL_DITHER_CNTL … #define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP3_DCP_RANDOM_SEEDS … #define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP3_DCP_FP_CONVERTED_FIELD … #define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP3_CUR_CONTROL … #define mmDCP3_CUR_CONTROL_BASE_IDX … #define mmDCP3_CUR_SURFACE_ADDRESS … #define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP3_CUR_SIZE … #define mmDCP3_CUR_SIZE_BASE_IDX … #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP3_CUR_POSITION … #define mmDCP3_CUR_POSITION_BASE_IDX … #define mmDCP3_CUR_HOT_SPOT … #define mmDCP3_CUR_HOT_SPOT_BASE_IDX … #define mmDCP3_CUR_COLOR1 … #define mmDCP3_CUR_COLOR1_BASE_IDX … #define mmDCP3_CUR_COLOR2 … #define mmDCP3_CUR_COLOR2_BASE_IDX … #define mmDCP3_CUR_UPDATE … #define mmDCP3_CUR_UPDATE_BASE_IDX … #define mmDCP3_CUR_REQUEST_FILTER_CNTL … #define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP3_CUR_STEREO_CONTROL … #define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP3_DC_LUT_RW_MODE … #define mmDCP3_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP3_DC_LUT_RW_INDEX … #define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP3_DC_LUT_SEQ_COLOR … #define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP3_DC_LUT_PWL_DATA … #define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP3_DC_LUT_30_COLOR … #define mmDCP3_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP3_DC_LUT_WRITE_EN_MASK … #define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP3_DC_LUT_AUTOFILL … #define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP3_DC_LUT_CONTROL … #define mmDCP3_DC_LUT_CONTROL_BASE_IDX … #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP3_DC_LUT_BLACK_OFFSET_RED … #define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP3_DC_LUT_WHITE_OFFSET_RED … #define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP3_DCP_CRC_CONTROL … #define mmDCP3_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP3_DCP_CRC_MASK … #define mmDCP3_DCP_CRC_MASK_BASE_IDX … #define mmDCP3_DCP_CRC_CURRENT … #define mmDCP3_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP3_DVMM_PTE_CONTROL … #define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP3_DCP_CRC_LAST … #define mmDCP3_DCP_CRC_LAST_BASE_IDX … #define mmDCP3_DVMM_PTE_ARB_CONTROL … #define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP3_GRPH_FLIP_RATE_CNTL … #define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP3_DCP_GSL_CONTROL … #define mmDCP3_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP3_GRPH_STEREOSYNC_FLIP … #define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP3_HW_ROTATION … #define mmDCP3_HW_ROTATION_BASE_IDX … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP3_REGAMMA_CONTROL … #define mmDCP3_REGAMMA_CONTROL_BASE_IDX … #define mmDCP3_REGAMMA_LUT_INDEX … #define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP3_REGAMMA_LUT_DATA … #define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_START_CNTL … #define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_START_CNTL … #define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP3_ALPHA_CONTROL … #define mmDCP3_ALPHA_CONTROL_BASE_IDX … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb3_dispdec // base address: 0x1800 #define mmLB3_LB_DATA_FORMAT … #define mmLB3_LB_DATA_FORMAT_BASE_IDX … #define mmLB3_LB_MEMORY_CTRL … #define mmLB3_LB_MEMORY_CTRL_BASE_IDX … #define mmLB3_LB_MEMORY_SIZE_STATUS … #define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB3_LB_DESKTOP_HEIGHT … #define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB3_LB_VLINE_START_END … #define mmLB3_LB_VLINE_START_END_BASE_IDX … #define mmLB3_LB_VLINE2_START_END … #define mmLB3_LB_VLINE2_START_END_BASE_IDX … #define mmLB3_LB_V_COUNTER … #define mmLB3_LB_V_COUNTER_BASE_IDX … #define mmLB3_LB_SNAPSHOT_V_COUNTER … #define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB3_LB_INTERRUPT_MASK … #define mmLB3_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB3_LB_VLINE_STATUS … #define mmLB3_LB_VLINE_STATUS_BASE_IDX … #define mmLB3_LB_VLINE2_STATUS … #define mmLB3_LB_VLINE2_STATUS_BASE_IDX … #define mmLB3_LB_VBLANK_STATUS … #define mmLB3_LB_VBLANK_STATUS_BASE_IDX … #define mmLB3_LB_SYNC_RESET_SEL … #define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB3_LB_BLACK_KEYER_R_CR … #define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB3_LB_BLACK_KEYER_G_Y … #define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB3_LB_BLACK_KEYER_B_CB … #define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_CTRL … #define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_R_CR … #define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_G_Y … #define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_B_CB … #define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_REP_R_CR … #define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_REP_G_Y … #define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB3_LB_KEYER_COLOR_REP_B_CB … #define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB3_LB_BUFFER_LEVEL_STATUS … #define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB3_LB_BUFFER_URGENCY_CTRL … #define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB3_LB_BUFFER_URGENCY_STATUS … #define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB3_LB_BUFFER_STATUS … #define mmLB3_LB_BUFFER_STATUS_BASE_IDX … #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB3_MVP_AFR_FLIP_MODE … #define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB3_MVP_FLIP_LINE_NUM_INSERT … #define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB3_DC_MVP_LB_CONTROL … #define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe3_dispdec // base address: 0x1800 #define mmDCFE3_DCFE_CLOCK_CONTROL … #define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE3_DCFE_SOFT_RESET … #define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE3_DCFE_MEM_PWR_CTRL … #define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE3_DCFE_MEM_PWR_CTRL2 … #define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE3_DCFE_MEM_PWR_STATUS … #define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE3_DCFE_MISC … #define mmDCFE3_DCFE_MISC_BASE_IDX … #define mmDCFE3_DCFE_FLUSH … #define mmDCFE3_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon6_dispdec // base address: 0x3138 #define mmDC_PERFMON6_PERFCOUNTER_CNTL … #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON6_PERFCOUNTER_STATE … #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CNTL … #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CNTL2 … #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CVALUE_LOW … #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON6_PERFMON_HI … #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON6_PERFMON_LOW … #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg3_dispdec // base address: 0x1800 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG3_DPG_REPEATER_PROGRAM … #define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG3_DPG_DVMM_STATUS … #define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl3_dispdec // base address: 0x1800 #define mmSCL3_SCL_COEF_RAM_SELECT … #define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL3_SCL_COEF_RAM_TAP_DATA … #define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL3_SCL_MODE … #define mmSCL3_SCL_MODE_BASE_IDX … #define mmSCL3_SCL_TAP_CONTROL … #define mmSCL3_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL3_SCL_CONTROL … #define mmSCL3_SCL_CONTROL_BASE_IDX … #define mmSCL3_SCL_BYPASS_CONTROL … #define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL3_SCL_HORZ_FILTER_CONTROL … #define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL3_SCL_HORZ_FILTER_INIT … #define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL3_SCL_VERT_FILTER_CONTROL … #define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL3_SCL_VERT_FILTER_INIT … #define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL3_SCL_VERT_FILTER_INIT_BOT … #define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL3_SCL_ROUND_OFFSET … #define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL3_SCL_UPDATE … #define mmSCL3_SCL_UPDATE_BASE_IDX … #define mmSCL3_SCL_F_SHARP_CONTROL … #define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL3_SCL_ALU_CONTROL … #define mmSCL3_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL3_VIEWPORT_START_SECONDARY … #define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL3_VIEWPORT_START … #define mmSCL3_VIEWPORT_START_BASE_IDX … #define mmSCL3_VIEWPORT_SIZE … #define mmSCL3_VIEWPORT_SIZE_BASE_IDX … #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL3_SCL_MODE_CHANGE_DET1 … #define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL3_SCL_MODE_CHANGE_DET2 … #define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL3_SCL_MODE_CHANGE_DET3 … #define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL3_SCL_MODE_CHANGE_MASK … #define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd3_dispdec // base address: 0x1800 #define mmBLND3_BLND_CONTROL … #define mmBLND3_BLND_CONTROL_BASE_IDX … #define mmBLND3_BLND_SM_CONTROL2 … #define mmBLND3_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND3_BLND_CONTROL2 … #define mmBLND3_BLND_CONTROL2_BASE_IDX … #define mmBLND3_BLND_UPDATE … #define mmBLND3_BLND_UPDATE_BASE_IDX … #define mmBLND3_BLND_UNDERFLOW_INTERRUPT … #define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND3_BLND_V_UPDATE_LOCK … #define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND3_BLND_REG_UPDATE_STATUS … #define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc3_dispdec // base address: 0x1800 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC3_CRTC_H_TOTAL … #define mmCRTC3_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC3_CRTC_H_BLANK_START_END … #define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC3_CRTC_H_SYNC_A … #define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC3_CRTC_H_SYNC_A_CNTL … #define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC3_CRTC_H_SYNC_B … #define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC3_CRTC_H_SYNC_B_CNTL … #define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC3_CRTC_VBI_END … #define mmCRTC3_CRTC_VBI_END_BASE_IDX … #define mmCRTC3_CRTC_V_TOTAL … #define mmCRTC3_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC3_CRTC_V_TOTAL_MIN … #define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC3_CRTC_V_TOTAL_MAX … #define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC3_CRTC_V_TOTAL_CONTROL … #define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC3_CRTC_V_BLANK_START_END … #define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC3_CRTC_V_SYNC_A … #define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC3_CRTC_V_SYNC_A_CNTL … #define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC3_CRTC_V_SYNC_B … #define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC3_CRTC_V_SYNC_B_CNTL … #define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC3_CRTC_DTMTEST_CNTL … #define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC3_CRTC_TRIGA_CNTL … #define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC3_CRTC_TRIGB_CNTL … #define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC3_CRTC_FLOW_CONTROL … #define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC3_CRTC_AVSYNC_COUNTER … #define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC3_CRTC_CONTROL … #define mmCRTC3_CRTC_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_BLANK_CONTROL … #define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_INTERLACE_CONTROL … #define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_INTERLACE_STATUS … #define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC3_CRTC_STATUS … #define mmCRTC3_CRTC_STATUS_BASE_IDX … #define mmCRTC3_CRTC_STATUS_POSITION … #define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC3_CRTC_NOM_VERT_POSITION … #define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC3_CRTC_STATUS_FRAME_COUNT … #define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC3_CRTC_STATUS_VF_COUNT … #define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC3_CRTC_STATUS_HV_COUNT … #define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC3_CRTC_COUNT_CONTROL … #define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_COUNT_RESET … #define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC3_CRTC_VERT_SYNC_CONTROL … #define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_STEREO_STATUS … #define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC3_CRTC_STEREO_CONTROL … #define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_SNAPSHOT_STATUS … #define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC3_CRTC_SNAPSHOT_CONTROL … #define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_SNAPSHOT_POSITION … #define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC3_CRTC_SNAPSHOT_FRAME … #define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC3_CRTC_START_LINE_CONTROL … #define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_INTERRUPT_CONTROL … #define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_UPDATE_LOCK … #define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC3_CRTC_TEST_PATTERN_COLOR … #define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC3_CRTC_MASTER_UPDATE_MODE … #define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC3_CRTC_MVP_STATUS … #define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC3_CRTC_MASTER_EN … #define mmCRTC3_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC3_CRTC_OVERSCAN_COLOR … #define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC3_CRTC_BLANK_DATA_COLOR … #define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC3_CRTC_BLACK_COLOR … #define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC3_CRTC_BLACK_COLOR_EXT … #define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC_CNTL … #define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC0_DATA_RG … #define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC3_CRTC_CRC0_DATA_B … #define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_CRC1_DATA_RG … #define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC3_CRTC_CRC1_DATA_B … #define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_GSL_VSYNC_GAP … #define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC3_CRTC_GSL_WINDOW … #define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC3_CRTC_GSL_CONTROL … #define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC3_CRTC_DRR_CONTROL … #define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt3_dispdec // base address: 0x1800 #define mmFMT3_FMT_CLAMP_COMPONENT_R … #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT3_FMT_CLAMP_COMPONENT_G … #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT3_FMT_CLAMP_COMPONENT_B … #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT3_FMT_DYNAMIC_EXP_CNTL … #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT3_FMT_CONTROL … #define mmFMT3_FMT_CONTROL_BASE_IDX … #define mmFMT3_FMT_BIT_DEPTH_CONTROL … #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_R_SEED … #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_G_SEED … #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_B_SEED … #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT3_FMT_CLAMP_CNTL … #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT3_FMT_CRC_CNTL … #define mmFMT3_FMT_CRC_CNTL_BASE_IDX … #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT3_FMT_CRC_SIG_RED_GREEN … #define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT3_FMT_420_HBLANK_EARLY_START … #define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_dcp4_dispdec // base address: 0x2000 #define mmDCP4_GRPH_ENABLE … #define mmDCP4_GRPH_ENABLE_BASE_IDX … #define mmDCP4_GRPH_CONTROL … #define mmDCP4_GRPH_CONTROL_BASE_IDX … #define mmDCP4_GRPH_LUT_10BIT_BYPASS … #define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP4_GRPH_SWAP_CNTL … #define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP4_GRPH_PITCH … #define mmDCP4_GRPH_PITCH_BASE_IDX … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP4_GRPH_SURFACE_OFFSET_X … #define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP4_GRPH_SURFACE_OFFSET_Y … #define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP4_GRPH_X_START … #define mmDCP4_GRPH_X_START_BASE_IDX … #define mmDCP4_GRPH_Y_START … #define mmDCP4_GRPH_Y_START_BASE_IDX … #define mmDCP4_GRPH_X_END … #define mmDCP4_GRPH_X_END_BASE_IDX … #define mmDCP4_GRPH_Y_END … #define mmDCP4_GRPH_Y_END_BASE_IDX … #define mmDCP4_INPUT_GAMMA_CONTROL … #define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP4_GRPH_UPDATE … #define mmDCP4_GRPH_UPDATE_BASE_IDX … #define mmDCP4_GRPH_FLIP_CONTROL … #define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP4_GRPH_DFQ_CONTROL … #define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP4_GRPH_DFQ_STATUS … #define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP4_GRPH_INTERRUPT_STATUS … #define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP4_GRPH_INTERRUPT_CONTROL … #define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP4_GRPH_COMPRESS_PITCH … #define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP4_PRESCALE_GRPH_CONTROL … #define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP4_PRESCALE_VALUES_GRPH_R … #define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP4_PRESCALE_VALUES_GRPH_G … #define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP4_PRESCALE_VALUES_GRPH_B … #define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP4_INPUT_CSC_CONTROL … #define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP4_INPUT_CSC_C11_C12 … #define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP4_INPUT_CSC_C13_C14 … #define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP4_INPUT_CSC_C21_C22 … #define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP4_INPUT_CSC_C23_C24 … #define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP4_INPUT_CSC_C31_C32 … #define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP4_INPUT_CSC_C33_C34 … #define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP4_OUTPUT_CSC_CONTROL … #define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C11_C12 … #define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C13_C14 … #define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C21_C22 … #define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C23_C24 … #define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C31_C32 … #define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP4_OUTPUT_CSC_C33_C34 … #define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP4_DENORM_CONTROL … #define mmDCP4_DENORM_CONTROL_BASE_IDX … #define mmDCP4_OUT_ROUND_CONTROL … #define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP4_OUT_CLAMP_CONTROL_R_CR … #define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP4_OUT_CLAMP_CONTROL_G_Y … #define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP4_OUT_CLAMP_CONTROL_B_CB … #define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP4_KEY_CONTROL … #define mmDCP4_KEY_CONTROL_BASE_IDX … #define mmDCP4_KEY_RANGE_ALPHA … #define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP4_KEY_RANGE_RED … #define mmDCP4_KEY_RANGE_RED_BASE_IDX … #define mmDCP4_KEY_RANGE_GREEN … #define mmDCP4_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP4_KEY_RANGE_BLUE … #define mmDCP4_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP4_DEGAMMA_CONTROL … #define mmDCP4_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP4_GAMUT_REMAP_CONTROL … #define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C11_C12 … #define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C13_C14 … #define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C21_C22 … #define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C23_C24 … #define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C31_C32 … #define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP4_GAMUT_REMAP_C33_C34 … #define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP4_DCP_SPATIAL_DITHER_CNTL … #define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP4_DCP_RANDOM_SEEDS … #define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP4_DCP_FP_CONVERTED_FIELD … #define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP4_CUR_CONTROL … #define mmDCP4_CUR_CONTROL_BASE_IDX … #define mmDCP4_CUR_SURFACE_ADDRESS … #define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP4_CUR_SIZE … #define mmDCP4_CUR_SIZE_BASE_IDX … #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP4_CUR_POSITION … #define mmDCP4_CUR_POSITION_BASE_IDX … #define mmDCP4_CUR_HOT_SPOT … #define mmDCP4_CUR_HOT_SPOT_BASE_IDX … #define mmDCP4_CUR_COLOR1 … #define mmDCP4_CUR_COLOR1_BASE_IDX … #define mmDCP4_CUR_COLOR2 … #define mmDCP4_CUR_COLOR2_BASE_IDX … #define mmDCP4_CUR_UPDATE … #define mmDCP4_CUR_UPDATE_BASE_IDX … #define mmDCP4_CUR_REQUEST_FILTER_CNTL … #define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP4_CUR_STEREO_CONTROL … #define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP4_DC_LUT_RW_MODE … #define mmDCP4_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP4_DC_LUT_RW_INDEX … #define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP4_DC_LUT_SEQ_COLOR … #define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP4_DC_LUT_PWL_DATA … #define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP4_DC_LUT_30_COLOR … #define mmDCP4_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP4_DC_LUT_WRITE_EN_MASK … #define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP4_DC_LUT_AUTOFILL … #define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP4_DC_LUT_CONTROL … #define mmDCP4_DC_LUT_CONTROL_BASE_IDX … #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP4_DC_LUT_BLACK_OFFSET_RED … #define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP4_DC_LUT_WHITE_OFFSET_RED … #define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP4_DCP_CRC_CONTROL … #define mmDCP4_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP4_DCP_CRC_MASK … #define mmDCP4_DCP_CRC_MASK_BASE_IDX … #define mmDCP4_DCP_CRC_CURRENT … #define mmDCP4_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP4_DVMM_PTE_CONTROL … #define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP4_DCP_CRC_LAST … #define mmDCP4_DCP_CRC_LAST_BASE_IDX … #define mmDCP4_DVMM_PTE_ARB_CONTROL … #define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP4_GRPH_FLIP_RATE_CNTL … #define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP4_DCP_GSL_CONTROL … #define mmDCP4_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP4_GRPH_STEREOSYNC_FLIP … #define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP4_HW_ROTATION … #define mmDCP4_HW_ROTATION_BASE_IDX … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP4_REGAMMA_CONTROL … #define mmDCP4_REGAMMA_CONTROL_BASE_IDX … #define mmDCP4_REGAMMA_LUT_INDEX … #define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP4_REGAMMA_LUT_DATA … #define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_START_CNTL … #define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_START_CNTL … #define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP4_ALPHA_CONTROL … #define mmDCP4_ALPHA_CONTROL_BASE_IDX … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb4_dispdec // base address: 0x2000 #define mmLB4_LB_DATA_FORMAT … #define mmLB4_LB_DATA_FORMAT_BASE_IDX … #define mmLB4_LB_MEMORY_CTRL … #define mmLB4_LB_MEMORY_CTRL_BASE_IDX … #define mmLB4_LB_MEMORY_SIZE_STATUS … #define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB4_LB_DESKTOP_HEIGHT … #define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB4_LB_VLINE_START_END … #define mmLB4_LB_VLINE_START_END_BASE_IDX … #define mmLB4_LB_VLINE2_START_END … #define mmLB4_LB_VLINE2_START_END_BASE_IDX … #define mmLB4_LB_V_COUNTER … #define mmLB4_LB_V_COUNTER_BASE_IDX … #define mmLB4_LB_SNAPSHOT_V_COUNTER … #define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB4_LB_INTERRUPT_MASK … #define mmLB4_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB4_LB_VLINE_STATUS … #define mmLB4_LB_VLINE_STATUS_BASE_IDX … #define mmLB4_LB_VLINE2_STATUS … #define mmLB4_LB_VLINE2_STATUS_BASE_IDX … #define mmLB4_LB_VBLANK_STATUS … #define mmLB4_LB_VBLANK_STATUS_BASE_IDX … #define mmLB4_LB_SYNC_RESET_SEL … #define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB4_LB_BLACK_KEYER_R_CR … #define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB4_LB_BLACK_KEYER_G_Y … #define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB4_LB_BLACK_KEYER_B_CB … #define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_CTRL … #define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_R_CR … #define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_G_Y … #define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_B_CB … #define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_REP_R_CR … #define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_REP_G_Y … #define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB4_LB_KEYER_COLOR_REP_B_CB … #define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB4_LB_BUFFER_LEVEL_STATUS … #define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB4_LB_BUFFER_URGENCY_CTRL … #define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB4_LB_BUFFER_URGENCY_STATUS … #define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB4_LB_BUFFER_STATUS … #define mmLB4_LB_BUFFER_STATUS_BASE_IDX … #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB4_MVP_AFR_FLIP_MODE … #define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB4_MVP_FLIP_LINE_NUM_INSERT … #define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB4_DC_MVP_LB_CONTROL … #define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe4_dispdec // base address: 0x2000 #define mmDCFE4_DCFE_CLOCK_CONTROL … #define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE4_DCFE_SOFT_RESET … #define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE4_DCFE_MEM_PWR_CTRL … #define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE4_DCFE_MEM_PWR_CTRL2 … #define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE4_DCFE_MEM_PWR_STATUS … #define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE4_DCFE_MISC … #define mmDCFE4_DCFE_MISC_BASE_IDX … #define mmDCFE4_DCFE_FLUSH … #define mmDCFE4_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon7_dispdec // base address: 0x3938 #define mmDC_PERFMON7_PERFCOUNTER_CNTL … #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON7_PERFCOUNTER_STATE … #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CNTL … #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CNTL2 … #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CVALUE_LOW … #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON7_PERFMON_HI … #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON7_PERFMON_LOW … #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg4_dispdec // base address: 0x2000 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG4_DPG_REPEATER_PROGRAM … #define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG4_DPG_DVMM_STATUS … #define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl4_dispdec // base address: 0x2000 #define mmSCL4_SCL_COEF_RAM_SELECT … #define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL4_SCL_COEF_RAM_TAP_DATA … #define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL4_SCL_MODE … #define mmSCL4_SCL_MODE_BASE_IDX … #define mmSCL4_SCL_TAP_CONTROL … #define mmSCL4_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL4_SCL_CONTROL … #define mmSCL4_SCL_CONTROL_BASE_IDX … #define mmSCL4_SCL_BYPASS_CONTROL … #define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL4_SCL_HORZ_FILTER_CONTROL … #define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL4_SCL_HORZ_FILTER_INIT … #define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL4_SCL_VERT_FILTER_CONTROL … #define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL4_SCL_VERT_FILTER_INIT … #define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL4_SCL_VERT_FILTER_INIT_BOT … #define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL4_SCL_ROUND_OFFSET … #define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL4_SCL_UPDATE … #define mmSCL4_SCL_UPDATE_BASE_IDX … #define mmSCL4_SCL_F_SHARP_CONTROL … #define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL4_SCL_ALU_CONTROL … #define mmSCL4_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL4_VIEWPORT_START_SECONDARY … #define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL4_VIEWPORT_START … #define mmSCL4_VIEWPORT_START_BASE_IDX … #define mmSCL4_VIEWPORT_SIZE … #define mmSCL4_VIEWPORT_SIZE_BASE_IDX … #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL4_SCL_MODE_CHANGE_DET1 … #define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL4_SCL_MODE_CHANGE_DET2 … #define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL4_SCL_MODE_CHANGE_DET3 … #define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL4_SCL_MODE_CHANGE_MASK … #define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd4_dispdec // base address: 0x2000 #define mmBLND4_BLND_CONTROL … #define mmBLND4_BLND_CONTROL_BASE_IDX … #define mmBLND4_BLND_SM_CONTROL2 … #define mmBLND4_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND4_BLND_CONTROL2 … #define mmBLND4_BLND_CONTROL2_BASE_IDX … #define mmBLND4_BLND_UPDATE … #define mmBLND4_BLND_UPDATE_BASE_IDX … #define mmBLND4_BLND_UNDERFLOW_INTERRUPT … #define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND4_BLND_V_UPDATE_LOCK … #define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND4_BLND_REG_UPDATE_STATUS … #define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc4_dispdec // base address: 0x2000 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC4_CRTC_H_TOTAL … #define mmCRTC4_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC4_CRTC_H_BLANK_START_END … #define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC4_CRTC_H_SYNC_A … #define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC4_CRTC_H_SYNC_A_CNTL … #define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC4_CRTC_H_SYNC_B … #define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC4_CRTC_H_SYNC_B_CNTL … #define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC4_CRTC_VBI_END … #define mmCRTC4_CRTC_VBI_END_BASE_IDX … #define mmCRTC4_CRTC_V_TOTAL … #define mmCRTC4_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC4_CRTC_V_TOTAL_MIN … #define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC4_CRTC_V_TOTAL_MAX … #define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC4_CRTC_V_TOTAL_CONTROL … #define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC4_CRTC_V_BLANK_START_END … #define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC4_CRTC_V_SYNC_A … #define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC4_CRTC_V_SYNC_A_CNTL … #define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC4_CRTC_V_SYNC_B … #define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC4_CRTC_V_SYNC_B_CNTL … #define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC4_CRTC_DTMTEST_CNTL … #define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC4_CRTC_TRIGA_CNTL … #define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC4_CRTC_TRIGB_CNTL … #define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC4_CRTC_FLOW_CONTROL … #define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC4_CRTC_AVSYNC_COUNTER … #define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC4_CRTC_CONTROL … #define mmCRTC4_CRTC_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_BLANK_CONTROL … #define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_INTERLACE_CONTROL … #define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_INTERLACE_STATUS … #define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC4_CRTC_STATUS … #define mmCRTC4_CRTC_STATUS_BASE_IDX … #define mmCRTC4_CRTC_STATUS_POSITION … #define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC4_CRTC_NOM_VERT_POSITION … #define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC4_CRTC_STATUS_FRAME_COUNT … #define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC4_CRTC_STATUS_VF_COUNT … #define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC4_CRTC_STATUS_HV_COUNT … #define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC4_CRTC_COUNT_CONTROL … #define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_COUNT_RESET … #define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC4_CRTC_VERT_SYNC_CONTROL … #define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_STEREO_STATUS … #define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC4_CRTC_STEREO_CONTROL … #define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_SNAPSHOT_STATUS … #define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC4_CRTC_SNAPSHOT_CONTROL … #define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_SNAPSHOT_POSITION … #define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC4_CRTC_SNAPSHOT_FRAME … #define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC4_CRTC_START_LINE_CONTROL … #define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_INTERRUPT_CONTROL … #define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_UPDATE_LOCK … #define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC4_CRTC_TEST_PATTERN_COLOR … #define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC4_CRTC_MASTER_UPDATE_MODE … #define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC4_CRTC_MVP_STATUS … #define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC4_CRTC_MASTER_EN … #define mmCRTC4_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC4_CRTC_OVERSCAN_COLOR … #define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC4_CRTC_BLANK_DATA_COLOR … #define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC4_CRTC_BLACK_COLOR … #define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC4_CRTC_BLACK_COLOR_EXT … #define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC_CNTL … #define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC0_DATA_RG … #define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC4_CRTC_CRC0_DATA_B … #define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_CRC1_DATA_RG … #define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC4_CRTC_CRC1_DATA_B … #define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_GSL_VSYNC_GAP … #define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC4_CRTC_GSL_WINDOW … #define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC4_CRTC_GSL_CONTROL … #define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC4_CRTC_DRR_CONTROL … #define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt4_dispdec // base address: 0x2000 #define mmFMT4_FMT_CLAMP_COMPONENT_R … #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT4_FMT_CLAMP_COMPONENT_G … #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT4_FMT_CLAMP_COMPONENT_B … #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT4_FMT_DYNAMIC_EXP_CNTL … #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT4_FMT_CONTROL … #define mmFMT4_FMT_CONTROL_BASE_IDX … #define mmFMT4_FMT_BIT_DEPTH_CONTROL … #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_R_SEED … #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_G_SEED … #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_B_SEED … #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT4_FMT_CLAMP_CNTL … #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT4_FMT_CRC_CNTL … #define mmFMT4_FMT_CRC_CNTL_BASE_IDX … #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT4_FMT_CRC_SIG_RED_GREEN … #define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT4_FMT_420_HBLANK_EARLY_START … #define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_dcp5_dispdec // base address: 0x2800 #define mmDCP5_GRPH_ENABLE … #define mmDCP5_GRPH_ENABLE_BASE_IDX … #define mmDCP5_GRPH_CONTROL … #define mmDCP5_GRPH_CONTROL_BASE_IDX … #define mmDCP5_GRPH_LUT_10BIT_BYPASS … #define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX … #define mmDCP5_GRPH_SWAP_CNTL … #define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP5_GRPH_PITCH … #define mmDCP5_GRPH_PITCH_BASE_IDX … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP5_GRPH_SURFACE_OFFSET_X … #define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX … #define mmDCP5_GRPH_SURFACE_OFFSET_Y … #define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX … #define mmDCP5_GRPH_X_START … #define mmDCP5_GRPH_X_START_BASE_IDX … #define mmDCP5_GRPH_Y_START … #define mmDCP5_GRPH_Y_START_BASE_IDX … #define mmDCP5_GRPH_X_END … #define mmDCP5_GRPH_X_END_BASE_IDX … #define mmDCP5_GRPH_Y_END … #define mmDCP5_GRPH_Y_END_BASE_IDX … #define mmDCP5_INPUT_GAMMA_CONTROL … #define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX … #define mmDCP5_GRPH_UPDATE … #define mmDCP5_GRPH_UPDATE_BASE_IDX … #define mmDCP5_GRPH_FLIP_CONTROL … #define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX … #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE … #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX … #define mmDCP5_GRPH_DFQ_CONTROL … #define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX … #define mmDCP5_GRPH_DFQ_STATUS … #define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX … #define mmDCP5_GRPH_INTERRUPT_STATUS … #define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmDCP5_GRPH_INTERRUPT_CONTROL … #define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE … #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX … #define mmDCP5_GRPH_COMPRESS_PITCH … #define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmDCP5_PRESCALE_GRPH_CONTROL … #define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX … #define mmDCP5_PRESCALE_VALUES_GRPH_R … #define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX … #define mmDCP5_PRESCALE_VALUES_GRPH_G … #define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX … #define mmDCP5_PRESCALE_VALUES_GRPH_B … #define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX … #define mmDCP5_INPUT_CSC_CONTROL … #define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX … #define mmDCP5_INPUT_CSC_C11_C12 … #define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX … #define mmDCP5_INPUT_CSC_C13_C14 … #define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX … #define mmDCP5_INPUT_CSC_C21_C22 … #define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX … #define mmDCP5_INPUT_CSC_C23_C24 … #define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX … #define mmDCP5_INPUT_CSC_C31_C32 … #define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX … #define mmDCP5_INPUT_CSC_C33_C34 … #define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX … #define mmDCP5_OUTPUT_CSC_CONTROL … #define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C11_C12 … #define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C13_C14 … #define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C21_C22 … #define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C23_C24 … #define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C31_C32 … #define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX … #define mmDCP5_OUTPUT_CSC_C33_C34 … #define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 … #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 … #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 … #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 … #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 … #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX … #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 … #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 … #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 … #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 … #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 … #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 … #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX … #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 … #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX … #define mmDCP5_DENORM_CONTROL … #define mmDCP5_DENORM_CONTROL_BASE_IDX … #define mmDCP5_OUT_ROUND_CONTROL … #define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX … #define mmDCP5_OUT_CLAMP_CONTROL_R_CR … #define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX … #define mmDCP5_OUT_CLAMP_CONTROL_G_Y … #define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX … #define mmDCP5_OUT_CLAMP_CONTROL_B_CB … #define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX … #define mmDCP5_KEY_CONTROL … #define mmDCP5_KEY_CONTROL_BASE_IDX … #define mmDCP5_KEY_RANGE_ALPHA … #define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX … #define mmDCP5_KEY_RANGE_RED … #define mmDCP5_KEY_RANGE_RED_BASE_IDX … #define mmDCP5_KEY_RANGE_GREEN … #define mmDCP5_KEY_RANGE_GREEN_BASE_IDX … #define mmDCP5_KEY_RANGE_BLUE … #define mmDCP5_KEY_RANGE_BLUE_BASE_IDX … #define mmDCP5_DEGAMMA_CONTROL … #define mmDCP5_DEGAMMA_CONTROL_BASE_IDX … #define mmDCP5_GAMUT_REMAP_CONTROL … #define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C11_C12 … #define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C13_C14 … #define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C21_C22 … #define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C23_C24 … #define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C31_C32 … #define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmDCP5_GAMUT_REMAP_C33_C34 … #define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmDCP5_DCP_SPATIAL_DITHER_CNTL … #define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX … #define mmDCP5_DCP_RANDOM_SEEDS … #define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX … #define mmDCP5_DCP_FP_CONVERTED_FIELD … #define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX … #define mmDCP5_CUR_CONTROL … #define mmDCP5_CUR_CONTROL_BASE_IDX … #define mmDCP5_CUR_SURFACE_ADDRESS … #define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX … #define mmDCP5_CUR_SIZE … #define mmDCP5_CUR_SIZE_BASE_IDX … #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH … #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP5_CUR_POSITION … #define mmDCP5_CUR_POSITION_BASE_IDX … #define mmDCP5_CUR_HOT_SPOT … #define mmDCP5_CUR_HOT_SPOT_BASE_IDX … #define mmDCP5_CUR_COLOR1 … #define mmDCP5_CUR_COLOR1_BASE_IDX … #define mmDCP5_CUR_COLOR2 … #define mmDCP5_CUR_COLOR2_BASE_IDX … #define mmDCP5_CUR_UPDATE … #define mmDCP5_CUR_UPDATE_BASE_IDX … #define mmDCP5_CUR_REQUEST_FILTER_CNTL … #define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX … #define mmDCP5_CUR_STEREO_CONTROL … #define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX … #define mmDCP5_DC_LUT_RW_MODE … #define mmDCP5_DC_LUT_RW_MODE_BASE_IDX … #define mmDCP5_DC_LUT_RW_INDEX … #define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX … #define mmDCP5_DC_LUT_SEQ_COLOR … #define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX … #define mmDCP5_DC_LUT_PWL_DATA … #define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX … #define mmDCP5_DC_LUT_30_COLOR … #define mmDCP5_DC_LUT_30_COLOR_BASE_IDX … #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE … #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX … #define mmDCP5_DC_LUT_WRITE_EN_MASK … #define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP5_DC_LUT_AUTOFILL … #define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX … #define mmDCP5_DC_LUT_CONTROL … #define mmDCP5_DC_LUT_CONTROL_BASE_IDX … #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE … #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX … #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN … #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX … #define mmDCP5_DC_LUT_BLACK_OFFSET_RED … #define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX … #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE … #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX … #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN … #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX … #define mmDCP5_DC_LUT_WHITE_OFFSET_RED … #define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX … #define mmDCP5_DCP_CRC_CONTROL … #define mmDCP5_DCP_CRC_CONTROL_BASE_IDX … #define mmDCP5_DCP_CRC_MASK … #define mmDCP5_DCP_CRC_MASK_BASE_IDX … #define mmDCP5_DCP_CRC_CURRENT … #define mmDCP5_DCP_CRC_CURRENT_BASE_IDX … #define mmDCP5_DVMM_PTE_CONTROL … #define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX … #define mmDCP5_DCP_CRC_LAST … #define mmDCP5_DCP_CRC_LAST_BASE_IDX … #define mmDCP5_DVMM_PTE_ARB_CONTROL … #define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmDCP5_GRPH_FLIP_RATE_CNTL … #define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX … #define mmDCP5_DCP_GSL_CONTROL … #define mmDCP5_DCP_GSL_CONTROL_BASE_IDX … #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmDCP5_GRPH_STEREOSYNC_FLIP … #define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmDCP5_HW_ROTATION … #define mmDCP5_HW_ROTATION_BASE_IDX … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX … #define mmDCP5_REGAMMA_CONTROL … #define mmDCP5_REGAMMA_CONTROL_BASE_IDX … #define mmDCP5_REGAMMA_LUT_INDEX … #define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX … #define mmDCP5_REGAMMA_LUT_DATA … #define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX … #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK … #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_START_CNTL … #define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL … #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 … #define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 … #define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 … #define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 … #define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 … #define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 … #define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 … #define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 … #define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 … #define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 … #define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_START_CNTL … #define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL … #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 … #define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 … #define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 … #define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 … #define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 … #define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 … #define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 … #define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 … #define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 … #define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 … #define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmDCP5_ALPHA_CONTROL … #define mmDCP5_ALPHA_CONTROL_BASE_IDX … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH … #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS … #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX … #define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT … #define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX … #define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY … #define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX … #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL … #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX … #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT … #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX … // addressBlock: dce_dc_lb5_dispdec // base address: 0x2800 #define mmLB5_LB_DATA_FORMAT … #define mmLB5_LB_DATA_FORMAT_BASE_IDX … #define mmLB5_LB_MEMORY_CTRL … #define mmLB5_LB_MEMORY_CTRL_BASE_IDX … #define mmLB5_LB_MEMORY_SIZE_STATUS … #define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLB5_LB_DESKTOP_HEIGHT … #define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX … #define mmLB5_LB_VLINE_START_END … #define mmLB5_LB_VLINE_START_END_BASE_IDX … #define mmLB5_LB_VLINE2_START_END … #define mmLB5_LB_VLINE2_START_END_BASE_IDX … #define mmLB5_LB_V_COUNTER … #define mmLB5_LB_V_COUNTER_BASE_IDX … #define mmLB5_LB_SNAPSHOT_V_COUNTER … #define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLB5_LB_INTERRUPT_MASK … #define mmLB5_LB_INTERRUPT_MASK_BASE_IDX … #define mmLB5_LB_VLINE_STATUS … #define mmLB5_LB_VLINE_STATUS_BASE_IDX … #define mmLB5_LB_VLINE2_STATUS … #define mmLB5_LB_VLINE2_STATUS_BASE_IDX … #define mmLB5_LB_VBLANK_STATUS … #define mmLB5_LB_VBLANK_STATUS_BASE_IDX … #define mmLB5_LB_SYNC_RESET_SEL … #define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX … #define mmLB5_LB_BLACK_KEYER_R_CR … #define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX … #define mmLB5_LB_BLACK_KEYER_G_Y … #define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX … #define mmLB5_LB_BLACK_KEYER_B_CB … #define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_CTRL … #define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_R_CR … #define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_G_Y … #define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_B_CB … #define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_REP_R_CR … #define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_REP_G_Y … #define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLB5_LB_KEYER_COLOR_REP_B_CB … #define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLB5_LB_BUFFER_LEVEL_STATUS … #define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLB5_LB_BUFFER_URGENCY_CTRL … #define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLB5_LB_BUFFER_URGENCY_STATUS … #define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLB5_LB_BUFFER_STATUS … #define mmLB5_LB_BUFFER_STATUS_BASE_IDX … #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS … #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … #define mmLB5_MVP_AFR_FLIP_MODE … #define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX … #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL … #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX … #define mmLB5_MVP_FLIP_LINE_NUM_INSERT … #define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX … #define mmLB5_DC_MVP_LB_CONTROL … #define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX … // addressBlock: dce_dc_dcfe5_dispdec // base address: 0x2800 #define mmDCFE5_DCFE_CLOCK_CONTROL … #define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX … #define mmDCFE5_DCFE_SOFT_RESET … #define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX … #define mmDCFE5_DCFE_MEM_PWR_CTRL … #define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX … #define mmDCFE5_DCFE_MEM_PWR_CTRL2 … #define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFE5_DCFE_MEM_PWR_STATUS … #define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX … #define mmDCFE5_DCFE_MISC … #define mmDCFE5_DCFE_MISC_BASE_IDX … #define mmDCFE5_DCFE_FLUSH … #define mmDCFE5_DCFE_FLUSH_BASE_IDX … // addressBlock: dce_dc_dc_perfmon8_dispdec // base address: 0x4138 #define mmDC_PERFMON8_PERFCOUNTER_CNTL … #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON8_PERFCOUNTER_STATE … #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CNTL … #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CNTL2 … #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CVALUE_LOW … #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON8_PERFMON_HI … #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON8_PERFMON_LOW … #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmif_pg5_dispdec // base address: 0x2800 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 … #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 … #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL … #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL … #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL … #define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 … #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX … #define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL … #define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX … #define mmDMIF_PG5_DPG_REPEATER_PROGRAM … #define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX … #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL … #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIF_PG5_DPG_DVMM_STATUS … #define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX … // addressBlock: dce_dc_scl5_dispdec // base address: 0x2800 #define mmSCL5_SCL_COEF_RAM_SELECT … #define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX … #define mmSCL5_SCL_COEF_RAM_TAP_DATA … #define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCL5_SCL_MODE … #define mmSCL5_SCL_MODE_BASE_IDX … #define mmSCL5_SCL_TAP_CONTROL … #define mmSCL5_SCL_TAP_CONTROL_BASE_IDX … #define mmSCL5_SCL_CONTROL … #define mmSCL5_SCL_CONTROL_BASE_IDX … #define mmSCL5_SCL_BYPASS_CONTROL … #define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX … #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL … #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL … #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCL5_SCL_HORZ_FILTER_CONTROL … #define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO … #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL5_SCL_HORZ_FILTER_INIT … #define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmSCL5_SCL_VERT_FILTER_CONTROL … #define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO … #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCL5_SCL_VERT_FILTER_INIT … #define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmSCL5_SCL_VERT_FILTER_INIT_BOT … #define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCL5_SCL_ROUND_OFFSET … #define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX … #define mmSCL5_SCL_UPDATE … #define mmSCL5_SCL_UPDATE_BASE_IDX … #define mmSCL5_SCL_F_SHARP_CONTROL … #define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX … #define mmSCL5_SCL_ALU_CONTROL … #define mmSCL5_SCL_ALU_CONTROL_BASE_IDX … #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS … #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmSCL5_VIEWPORT_START_SECONDARY … #define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCL5_VIEWPORT_START … #define mmSCL5_VIEWPORT_START_BASE_IDX … #define mmSCL5_VIEWPORT_SIZE … #define mmSCL5_VIEWPORT_SIZE_BASE_IDX … #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCL5_SCL_MODE_CHANGE_DET1 … #define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX … #define mmSCL5_SCL_MODE_CHANGE_DET2 … #define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX … #define mmSCL5_SCL_MODE_CHANGE_DET3 … #define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX … #define mmSCL5_SCL_MODE_CHANGE_MASK … #define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX … // addressBlock: dce_dc_blnd5_dispdec // base address: 0x2800 #define mmBLND5_BLND_CONTROL … #define mmBLND5_BLND_CONTROL_BASE_IDX … #define mmBLND5_BLND_SM_CONTROL2 … #define mmBLND5_BLND_SM_CONTROL2_BASE_IDX … #define mmBLND5_BLND_CONTROL2 … #define mmBLND5_BLND_CONTROL2_BASE_IDX … #define mmBLND5_BLND_UPDATE … #define mmBLND5_BLND_UPDATE_BASE_IDX … #define mmBLND5_BLND_UNDERFLOW_INTERRUPT … #define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLND5_BLND_V_UPDATE_LOCK … #define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX … #define mmBLND5_BLND_REG_UPDATE_STATUS … #define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtc5_dispdec // base address: 0x2800 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM … #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTC5_CRTC_H_TOTAL … #define mmCRTC5_CRTC_H_TOTAL_BASE_IDX … #define mmCRTC5_CRTC_H_BLANK_START_END … #define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX … #define mmCRTC5_CRTC_H_SYNC_A … #define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX … #define mmCRTC5_CRTC_H_SYNC_A_CNTL … #define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTC5_CRTC_H_SYNC_B … #define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX … #define mmCRTC5_CRTC_H_SYNC_B_CNTL … #define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTC5_CRTC_VBI_END … #define mmCRTC5_CRTC_VBI_END_BASE_IDX … #define mmCRTC5_CRTC_V_TOTAL … #define mmCRTC5_CRTC_V_TOTAL_BASE_IDX … #define mmCRTC5_CRTC_V_TOTAL_MIN … #define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX … #define mmCRTC5_CRTC_V_TOTAL_MAX … #define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX … #define mmCRTC5_CRTC_V_TOTAL_CONTROL … #define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS … #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS … #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTC5_CRTC_V_BLANK_START_END … #define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX … #define mmCRTC5_CRTC_V_SYNC_A … #define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX … #define mmCRTC5_CRTC_V_SYNC_A_CNTL … #define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTC5_CRTC_V_SYNC_B … #define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX … #define mmCRTC5_CRTC_V_SYNC_B_CNTL … #define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTC5_CRTC_DTMTEST_CNTL … #define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX … #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION … #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTC5_CRTC_TRIGA_CNTL … #define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX … #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG … #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTC5_CRTC_TRIGB_CNTL … #define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX … #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG … #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL … #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTC5_CRTC_FLOW_CONTROL … #define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE … #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTC5_CRTC_AVSYNC_COUNTER … #define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX … #define mmCRTC5_CRTC_CONTROL … #define mmCRTC5_CRTC_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_BLANK_CONTROL … #define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_INTERLACE_CONTROL … #define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_INTERLACE_STATUS … #define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX … #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL … #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 … #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTC5_CRTC_STATUS … #define mmCRTC5_CRTC_STATUS_BASE_IDX … #define mmCRTC5_CRTC_STATUS_POSITION … #define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX … #define mmCRTC5_CRTC_NOM_VERT_POSITION … #define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX … #define mmCRTC5_CRTC_STATUS_FRAME_COUNT … #define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTC5_CRTC_STATUS_VF_COUNT … #define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX … #define mmCRTC5_CRTC_STATUS_HV_COUNT … #define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX … #define mmCRTC5_CRTC_COUNT_CONTROL … #define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_COUNT_RESET … #define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX … #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTC5_CRTC_VERT_SYNC_CONTROL … #define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_STEREO_STATUS … #define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX … #define mmCRTC5_CRTC_STEREO_CONTROL … #define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_SNAPSHOT_STATUS … #define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTC5_CRTC_SNAPSHOT_CONTROL … #define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_SNAPSHOT_POSITION … #define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTC5_CRTC_SNAPSHOT_FRAME … #define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTC5_CRTC_START_LINE_CONTROL … #define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_INTERRUPT_CONTROL … #define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_UPDATE_LOCK … #define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX … #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL … #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL … #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS … #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTC5_CRTC_TEST_PATTERN_COLOR … #define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK … #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTC5_CRTC_MASTER_UPDATE_MODE … #define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTC5_CRTC_MVP_STATUS … #define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX … #define mmCRTC5_CRTC_MASTER_EN … #define mmCRTC5_CRTC_MASTER_EN_BASE_IDX … #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT … #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS … #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTC5_CRTC_OVERSCAN_COLOR … #define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX … #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT … #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTC5_CRTC_BLANK_DATA_COLOR … #define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT … #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTC5_CRTC_BLACK_COLOR … #define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX … #define mmCRTC5_CRTC_BLACK_COLOR_EXT … #define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC_CNTL … #define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX … #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL … #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC0_DATA_RG … #define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX … #define mmCRTC5_CRTC_CRC0_DATA_B … #define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX … #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL … #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_CRC1_DATA_RG … #define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX … #define mmCRTC5_CRTC_CRC1_DATA_B … #define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL … #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL … #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_GSL_VSYNC_GAP … #define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTC5_CRTC_GSL_WINDOW … #define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX … #define mmCRTC5_CRTC_GSL_CONTROL … #define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX … #define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS … #define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmCRTC5_CRTC_DRR_CONTROL … #define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX … // addressBlock: dce_dc_fmt5_dispdec // base address: 0x2800 #define mmFMT5_FMT_CLAMP_COMPONENT_R … #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT5_FMT_CLAMP_COMPONENT_G … #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT5_FMT_CLAMP_COMPONENT_B … #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT5_FMT_DYNAMIC_EXP_CNTL … #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT5_FMT_CONTROL … #define mmFMT5_FMT_CONTROL_BASE_IDX … #define mmFMT5_FMT_BIT_DEPTH_CONTROL … #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_R_SEED … #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_G_SEED … #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_B_SEED … #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT5_FMT_CLAMP_CNTL … #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT5_FMT_CRC_CNTL … #define mmFMT5_FMT_CRC_CNTL_BASE_IDX … #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK … #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmFMT5_FMT_CRC_SIG_RED_GREEN … #define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL … #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX … #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT5_FMT_420_HBLANK_EARLY_START … #define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX … // addressBlock: dce_dc_unp0_dispdec // base address: 0x0 #define mmUNP0_UNP_GRPH_ENABLE … #define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX … #define mmUNP0_UNP_GRPH_CONTROL … #define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX … #define mmUNP0_UNP_GRPH_CONTROL_C … #define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX … #define mmUNP0_UNP_GRPH_CONTROL_EXP … #define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX … #define mmUNP0_UNP_GRPH_SWAP_CNTL … #define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP0_UNP_GRPH_PITCH_L … #define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX … #define mmUNP0_UNP_GRPH_PITCH_C … #define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C … #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX … #define mmUNP0_UNP_GRPH_X_START_L … #define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX … #define mmUNP0_UNP_GRPH_X_START_C … #define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX … #define mmUNP0_UNP_GRPH_Y_START_L … #define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX … #define mmUNP0_UNP_GRPH_Y_START_C … #define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX … #define mmUNP0_UNP_GRPH_X_END_L … #define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX … #define mmUNP0_UNP_GRPH_X_END_C … #define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX … #define mmUNP0_UNP_GRPH_Y_END_L … #define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX … #define mmUNP0_UNP_GRPH_Y_END_C … #define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX … #define mmUNP0_UNP_GRPH_UPDATE … #define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX … #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C … #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX … #define mmUNP0_UNP_DVMM_PTE_CONTROL … #define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX … #define mmUNP0_UNP_DVMM_PTE_CONTROL_C … #define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX … #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL … #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C … #define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX … #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS … #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL … #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP … #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmUNP0_UNP_FLIP_CONTROL … #define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX … #define mmUNP0_UNP_CRC_CONTROL … #define mmUNP0_UNP_CRC_CONTROL_BASE_IDX … #define mmUNP0_UNP_CRC_MASK … #define mmUNP0_UNP_CRC_MASK_BASE_IDX … #define mmUNP0_UNP_CRC_CURRENT … #define mmUNP0_UNP_CRC_CURRENT_BASE_IDX … #define mmUNP0_UNP_CRC_LAST … #define mmUNP0_UNP_CRC_LAST_BASE_IDX … #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmUNP0_UNP_HW_ROTATION … #define mmUNP0_UNP_HW_ROTATION_BASE_IDX … // addressBlock: dce_dc_lbv0_dispdec // base address: 0x0 #define mmLBV0_LBV_DATA_FORMAT … #define mmLBV0_LBV_DATA_FORMAT_BASE_IDX … #define mmLBV0_LBV_MEMORY_CTRL … #define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX … #define mmLBV0_LBV_MEMORY_SIZE_STATUS … #define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLBV0_LBV_DESKTOP_HEIGHT … #define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX … #define mmLBV0_LBV_VLINE_START_END … #define mmLBV0_LBV_VLINE_START_END_BASE_IDX … #define mmLBV0_LBV_VLINE2_START_END … #define mmLBV0_LBV_VLINE2_START_END_BASE_IDX … #define mmLBV0_LBV_V_COUNTER … #define mmLBV0_LBV_V_COUNTER_BASE_IDX … #define mmLBV0_LBV_SNAPSHOT_V_COUNTER … #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLBV0_LBV_V_COUNTER_CHROMA … #define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX … #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA … #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX … #define mmLBV0_LBV_INTERRUPT_MASK … #define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX … #define mmLBV0_LBV_VLINE_STATUS … #define mmLBV0_LBV_VLINE_STATUS_BASE_IDX … #define mmLBV0_LBV_VLINE2_STATUS … #define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX … #define mmLBV0_LBV_VBLANK_STATUS … #define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX … #define mmLBV0_LBV_SYNC_RESET_SEL … #define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX … #define mmLBV0_LBV_BLACK_KEYER_R_CR … #define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX … #define mmLBV0_LBV_BLACK_KEYER_G_Y … #define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX … #define mmLBV0_LBV_BLACK_KEYER_B_CB … #define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_CTRL … #define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_R_CR … #define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_G_Y … #define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_B_CB … #define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR … #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y … #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB … #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLBV0_LBV_BUFFER_LEVEL_STATUS … #define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLBV0_LBV_BUFFER_URGENCY_CTRL … #define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLBV0_LBV_BUFFER_URGENCY_STATUS … #define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLBV0_LBV_BUFFER_STATUS … #define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX … #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS … #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … // addressBlock: dce_dc_sclv0_dispdec // base address: 0x0 #define mmSCLV0_SCLV_COEF_RAM_SELECT … #define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX … #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA … #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCLV0_SCLV_MODE … #define mmSCLV0_SCLV_MODE_BASE_IDX … #define mmSCLV0_SCLV_TAP_CONTROL … #define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_CONTROL … #define mmSCLV0_SCLV_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL … #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL … #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL … #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO … #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_INIT … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C … #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_CONTROL … #define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO … #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_INIT … #define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT … #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C … #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_INIT_C … #define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX … #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C … #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmSCLV0_SCLV_ROUND_OFFSET … #define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX … #define mmSCLV0_SCLV_UPDATE … #define mmSCLV0_SCLV_UPDATE_BASE_IDX … #define mmSCLV0_SCLV_ALU_CONTROL … #define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_START … #define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY … #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_SIZE … #define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_START_C … #define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C … #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX … #define mmSCLV0_SCLV_VIEWPORT_SIZE_C … #define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX … #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCLV0_SCLV_MODE_CHANGE_DET1 … #define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX … #define mmSCLV0_SCLV_MODE_CHANGE_DET2 … #define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX … #define mmSCLV0_SCLV_MODE_CHANGE_DET3 … #define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX … #define mmSCLV0_SCLV_MODE_CHANGE_MASK … #define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C … #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX … // addressBlock: dce_dc_col_man0_dispdec // base address: 0x0 #define mmCOL_MAN0_COL_MAN_UPDATE … #define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX … #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL … #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C11_C12_A … #define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C13_C14_A … #define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C21_C22_A … #define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C23_C24_A … #define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C31_C32_A … #define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C33_C34_A … #define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C11_C12_B … #define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C13_C14_B … #define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C21_C22_B … #define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C23_C24_B … #define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C31_C32_B … #define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX … #define mmCOL_MAN0_INPUT_CSC_C33_C34_B … #define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX … #define mmCOL_MAN0_PRESCALE_CONTROL … #define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX … #define mmCOL_MAN0_PRESCALE_VALUES_R … #define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX … #define mmCOL_MAN0_PRESCALE_VALUES_G … #define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX … #define mmCOL_MAN0_PRESCALE_VALUES_B … #define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX … #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL … #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A … #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A … #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A … #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A … #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A … #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A … #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B … #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B … #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B … #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B … #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B … #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX … #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B … #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX … #define mmCOL_MAN0_DENORM_CLAMP_CONTROL … #define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB … #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX … #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD … #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL … #define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK … #define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 … #define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmCOL_MAN0_PACK_FIFO_ERROR … #define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX … #define mmCOL_MAN0_OUTPUT_FIFO_ERROR … #define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL … #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR … #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA … #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR … #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX … #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 … #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX … #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 … #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R … #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX … #define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL … #define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 … #define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX … // addressBlock: dce_dc_dcfev0_dispdec // base address: 0x0 #define mmDCFEV0_DCFEV_CLOCK_CONTROL … #define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX … #define mmDCFEV0_DCFEV_SOFT_RESET … #define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX … #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL … #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX … #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL … #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX … #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS … #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX … #define mmDCFEV0_DCFEV_MEM_PWR_CTRL … #define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX … #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 … #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFEV0_DCFEV_MEM_PWR_STATUS … #define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX … #define mmDCFEV0_DCFEV_L_FLUSH … #define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX … #define mmDCFEV0_DCFEV_C_FLUSH … #define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX … #define mmDCFEV0_DCFEV_MISC … #define mmDCFEV0_DCFEV_MISC_BASE_IDX … // addressBlock: dce_dc_dc_perfmon11_dispdec // base address: 0x49c8 #define mmDC_PERFMON11_PERFCOUNTER_CNTL … #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON11_PERFCOUNTER_STATE … #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CNTL … #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CNTL2 … #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CVALUE_LOW … #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON11_PERFMON_HI … #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON11_PERFMON_LOW … #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmifv_pg0_dispdec // base address: 0x0 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 … #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 … #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL … #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL … #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL … #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL … #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX … #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM … #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX … #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL … #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 … #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 … #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL … #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL … #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL … #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL … #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX … #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX … #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM … #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX … #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL … #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX … // addressBlock: dce_dc_blndv0_dispdec // base address: 0x0 #define mmBLNDV0_BLNDV_CONTROL … #define mmBLNDV0_BLNDV_CONTROL_BASE_IDX … #define mmBLNDV0_BLNDV_SM_CONTROL2 … #define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX … #define mmBLNDV0_BLNDV_CONTROL2 … #define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX … #define mmBLNDV0_BLNDV_UPDATE … #define mmBLNDV0_BLNDV_UPDATE_BASE_IDX … #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT … #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLNDV0_BLNDV_V_UPDATE_LOCK … #define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX … #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS … #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtcv0_dispdec // base address: 0x0 #define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM … #define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTCV0_CRTCV_H_TOTAL … #define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX … #define mmCRTCV0_CRTCV_H_BLANK_START_END … #define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX … #define mmCRTCV0_CRTCV_H_SYNC_A … #define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX … #define mmCRTCV0_CRTCV_H_SYNC_A_CNTL … #define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_H_SYNC_B … #define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX … #define mmCRTCV0_CRTCV_H_SYNC_B_CNTL … #define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_VBI_END … #define mmCRTCV0_CRTCV_VBI_END_BASE_IDX … #define mmCRTCV0_CRTCV_V_TOTAL … #define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX … #define mmCRTCV0_CRTCV_V_TOTAL_MIN … #define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX … #define mmCRTCV0_CRTCV_V_TOTAL_MAX … #define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX … #define mmCRTCV0_CRTCV_V_TOTAL_CONTROL … #define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS … #define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS … #define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_V_BLANK_START_END … #define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX … #define mmCRTCV0_CRTCV_V_SYNC_A … #define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX … #define mmCRTCV0_CRTCV_V_SYNC_A_CNTL … #define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_V_SYNC_B … #define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX … #define mmCRTCV0_CRTCV_V_SYNC_B_CNTL … #define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_DTMTEST_CNTL … #define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION … #define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_TRIGA_CNTL … #define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG … #define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTCV0_CRTCV_TRIGB_CNTL … #define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG … #define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL … #define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_FLOW_CONTROL … #define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE … #define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTCV0_CRTCV_AVSYNC_COUNTER … #define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX … #define mmCRTCV0_CRTCV_CONTROL … #define mmCRTCV0_CRTCV_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_BLANK_CONTROL … #define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_INTERLACE_CONTROL … #define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_INTERLACE_STATUS … #define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL … #define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 … #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 … #define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTCV0_CRTCV_STATUS … #define mmCRTCV0_CRTCV_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_STATUS_POSITION … #define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_NOM_VERT_POSITION … #define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT … #define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTCV0_CRTCV_STATUS_VF_COUNT … #define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX … #define mmCRTCV0_CRTCV_STATUS_HV_COUNT … #define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX … #define mmCRTCV0_CRTCV_COUNT_CONTROL … #define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_COUNT_RESET … #define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX … #define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL … #define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_STEREO_STATUS … #define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_STEREO_CONTROL … #define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_SNAPSHOT_STATUS … #define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL … #define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_SNAPSHOT_POSITION … #define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_SNAPSHOT_FRAME … #define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTCV0_CRTCV_START_LINE_CONTROL … #define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_INTERRUPT_CONTROL … #define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_UPDATE_LOCK … #define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX … #define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL … #define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL … #define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS … #define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR … #define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK … #define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE … #define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT … #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTCV0_CRTCV_MVP_STATUS … #define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_MASTER_EN … #define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX … #define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT … #define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS … #define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTCV0_CRTCV_OVERSCAN_COLOR … #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX … #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT … #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR … #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT … #define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTCV0_CRTCV_BLACK_COLOR … #define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX … #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT … #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC_CNTL … #define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL … #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL … #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL … #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL … #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_DATA_RG … #define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX … #define mmCRTCV0_CRTCV_CRC0_DATA_B … #define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL … #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL … #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL … #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL … #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_DATA_RG … #define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX … #define mmCRTCV0_CRTCV_CRC1_DATA_B … #define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL … #define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL … #define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTCV0_CRTCV_GSL_VSYNC_GAP … #define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTCV0_CRTCV_GSL_WINDOW … #define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX … #define mmCRTCV0_CRTCV_GSL_CONTROL … #define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX … // addressBlock: dce_dc_unp1_dispdec // base address: 0x800 #define mmUNP1_UNP_GRPH_ENABLE … #define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX … #define mmUNP1_UNP_GRPH_CONTROL … #define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX … #define mmUNP1_UNP_GRPH_CONTROL_C … #define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX … #define mmUNP1_UNP_GRPH_CONTROL_EXP … #define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX … #define mmUNP1_UNP_GRPH_SWAP_CNTL … #define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C … #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmUNP1_UNP_GRPH_PITCH_L … #define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX … #define mmUNP1_UNP_GRPH_PITCH_C … #define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C … #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX … #define mmUNP1_UNP_GRPH_X_START_L … #define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX … #define mmUNP1_UNP_GRPH_X_START_C … #define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX … #define mmUNP1_UNP_GRPH_Y_START_L … #define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX … #define mmUNP1_UNP_GRPH_Y_START_C … #define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX … #define mmUNP1_UNP_GRPH_X_END_L … #define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX … #define mmUNP1_UNP_GRPH_X_END_C … #define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX … #define mmUNP1_UNP_GRPH_Y_END_L … #define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX … #define mmUNP1_UNP_GRPH_Y_END_C … #define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX … #define mmUNP1_UNP_GRPH_UPDATE … #define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX … #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT … #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C … #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX … #define mmUNP1_UNP_DVMM_PTE_CONTROL … #define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX … #define mmUNP1_UNP_DVMM_PTE_CONTROL_C … #define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX … #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL … #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX … #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C … #define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX … #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS … #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX … #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL … #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX … #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP … #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX … #define mmUNP1_UNP_FLIP_CONTROL … #define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX … #define mmUNP1_UNP_CRC_CONTROL … #define mmUNP1_UNP_CRC_CONTROL_BASE_IDX … #define mmUNP1_UNP_CRC_MASK … #define mmUNP1_UNP_CRC_MASK_BASE_IDX … #define mmUNP1_UNP_CRC_CURRENT … #define mmUNP1_UNP_CRC_CURRENT_BASE_IDX … #define mmUNP1_UNP_CRC_LAST … #define mmUNP1_UNP_CRC_LAST_BASE_IDX … #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK … #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX … #define mmUNP1_UNP_HW_ROTATION … #define mmUNP1_UNP_HW_ROTATION_BASE_IDX … // addressBlock: dce_dc_lbv1_dispdec // base address: 0x800 #define mmLBV1_LBV_DATA_FORMAT … #define mmLBV1_LBV_DATA_FORMAT_BASE_IDX … #define mmLBV1_LBV_MEMORY_CTRL … #define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX … #define mmLBV1_LBV_MEMORY_SIZE_STATUS … #define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX … #define mmLBV1_LBV_DESKTOP_HEIGHT … #define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX … #define mmLBV1_LBV_VLINE_START_END … #define mmLBV1_LBV_VLINE_START_END_BASE_IDX … #define mmLBV1_LBV_VLINE2_START_END … #define mmLBV1_LBV_VLINE2_START_END_BASE_IDX … #define mmLBV1_LBV_V_COUNTER … #define mmLBV1_LBV_V_COUNTER_BASE_IDX … #define mmLBV1_LBV_SNAPSHOT_V_COUNTER … #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX … #define mmLBV1_LBV_V_COUNTER_CHROMA … #define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX … #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA … #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX … #define mmLBV1_LBV_INTERRUPT_MASK … #define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX … #define mmLBV1_LBV_VLINE_STATUS … #define mmLBV1_LBV_VLINE_STATUS_BASE_IDX … #define mmLBV1_LBV_VLINE2_STATUS … #define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX … #define mmLBV1_LBV_VBLANK_STATUS … #define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX … #define mmLBV1_LBV_SYNC_RESET_SEL … #define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX … #define mmLBV1_LBV_BLACK_KEYER_R_CR … #define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX … #define mmLBV1_LBV_BLACK_KEYER_G_Y … #define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX … #define mmLBV1_LBV_BLACK_KEYER_B_CB … #define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_CTRL … #define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_R_CR … #define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_G_Y … #define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_B_CB … #define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR … #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y … #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX … #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB … #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX … #define mmLBV1_LBV_BUFFER_LEVEL_STATUS … #define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX … #define mmLBV1_LBV_BUFFER_URGENCY_CTRL … #define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX … #define mmLBV1_LBV_BUFFER_URGENCY_STATUS … #define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX … #define mmLBV1_LBV_BUFFER_STATUS … #define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX … #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS … #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX … // addressBlock: dce_dc_sclv1_dispdec // base address: 0x800 #define mmSCLV1_SCLV_COEF_RAM_SELECT … #define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX … #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA … #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX … #define mmSCLV1_SCLV_MODE … #define mmSCLV1_SCLV_MODE_BASE_IDX … #define mmSCLV1_SCLV_TAP_CONTROL … #define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_CONTROL … #define mmSCLV1_SCLV_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL … #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL … #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL … #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO … #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_INIT … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C … #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_CONTROL … #define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO … #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_INIT … #define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT … #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C … #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_INIT_C … #define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX … #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C … #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmSCLV1_SCLV_ROUND_OFFSET … #define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX … #define mmSCLV1_SCLV_UPDATE … #define mmSCLV1_SCLV_UPDATE_BASE_IDX … #define mmSCLV1_SCLV_ALU_CONTROL … #define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_START … #define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY … #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_SIZE … #define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_START_C … #define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C … #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX … #define mmSCLV1_SCLV_VIEWPORT_SIZE_C … #define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX … #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT … #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM … #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmSCLV1_SCLV_MODE_CHANGE_DET1 … #define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX … #define mmSCLV1_SCLV_MODE_CHANGE_DET2 … #define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX … #define mmSCLV1_SCLV_MODE_CHANGE_DET3 … #define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX … #define mmSCLV1_SCLV_MODE_CHANGE_MASK … #define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C … #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX … // addressBlock: dce_dc_col_man1_dispdec // base address: 0x800 #define mmCOL_MAN1_COL_MAN_UPDATE … #define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX … #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL … #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C11_C12_A … #define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C13_C14_A … #define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C21_C22_A … #define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C23_C24_A … #define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C31_C32_A … #define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C33_C34_A … #define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C11_C12_B … #define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C13_C14_B … #define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C21_C22_B … #define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C23_C24_B … #define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C31_C32_B … #define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX … #define mmCOL_MAN1_INPUT_CSC_C33_C34_B … #define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX … #define mmCOL_MAN1_PRESCALE_CONTROL … #define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX … #define mmCOL_MAN1_PRESCALE_VALUES_R … #define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX … #define mmCOL_MAN1_PRESCALE_VALUES_G … #define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX … #define mmCOL_MAN1_PRESCALE_VALUES_B … #define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX … #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL … #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A … #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A … #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A … #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A … #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A … #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A … #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B … #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B … #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B … #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B … #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B … #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX … #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B … #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX … #define mmCOL_MAN1_DENORM_CLAMP_CONTROL … #define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB … #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX … #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD … #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL … #define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK … #define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 … #define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX … #define mmCOL_MAN1_PACK_FIFO_ERROR … #define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX … #define mmCOL_MAN1_OUTPUT_FIFO_ERROR … #define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL … #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR … #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA … #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR … #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX … #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 … #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX … #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 … #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R … #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX … #define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL … #define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 … #define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX … // addressBlock: dce_dc_dcfev1_dispdec // base address: 0x800 #define mmDCFEV1_DCFEV_CLOCK_CONTROL … #define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX … #define mmDCFEV1_DCFEV_SOFT_RESET … #define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX … #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL … #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX … #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL … #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX … #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS … #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX … #define mmDCFEV1_DCFEV_MEM_PWR_CTRL … #define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX … #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 … #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX … #define mmDCFEV1_DCFEV_MEM_PWR_STATUS … #define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX … #define mmDCFEV1_DCFEV_L_FLUSH … #define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX … #define mmDCFEV1_DCFEV_C_FLUSH … #define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX … #define mmDCFEV1_DCFEV_MISC … #define mmDCFEV1_DCFEV_MISC_BASE_IDX … // addressBlock: dce_dc_dc_perfmon12_dispdec // base address: 0x51c8 #define mmDC_PERFMON12_PERFCOUNTER_CNTL … #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON12_PERFCOUNTER_STATE … #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CNTL … #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CNTL2 … #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CVALUE_LOW … #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON12_PERFMON_HI … #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON12_PERFMON_LOW … #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmifv_pg1_dispdec // base address: 0x800 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 … #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 … #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL … #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL … #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL … #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL … #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX … #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM … #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX … #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL … #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 … #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 … #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX … #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL … #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL … #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL … #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL … #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL … #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX … #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH … #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX … #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM … #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX … #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL … #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX … // addressBlock: dce_dc_blndv1_dispdec // base address: 0x800 #define mmBLNDV1_BLNDV_CONTROL … #define mmBLNDV1_BLNDV_CONTROL_BASE_IDX … #define mmBLNDV1_BLNDV_SM_CONTROL2 … #define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX … #define mmBLNDV1_BLNDV_CONTROL2 … #define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX … #define mmBLNDV1_BLNDV_UPDATE … #define mmBLNDV1_BLNDV_UPDATE_BASE_IDX … #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT … #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX … #define mmBLNDV1_BLNDV_V_UPDATE_LOCK … #define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX … #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS … #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX … // addressBlock: dce_dc_crtcv1_dispdec // base address: 0x800 #define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM … #define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX … #define mmCRTCV1_CRTCV_H_TOTAL … #define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX … #define mmCRTCV1_CRTCV_H_BLANK_START_END … #define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX … #define mmCRTCV1_CRTCV_H_SYNC_A … #define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX … #define mmCRTCV1_CRTCV_H_SYNC_A_CNTL … #define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_H_SYNC_B … #define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX … #define mmCRTCV1_CRTCV_H_SYNC_B_CNTL … #define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_VBI_END … #define mmCRTCV1_CRTCV_VBI_END_BASE_IDX … #define mmCRTCV1_CRTCV_V_TOTAL … #define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX … #define mmCRTCV1_CRTCV_V_TOTAL_MIN … #define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX … #define mmCRTCV1_CRTCV_V_TOTAL_MAX … #define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX … #define mmCRTCV1_CRTCV_V_TOTAL_CONTROL … #define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS … #define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS … #define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_V_BLANK_START_END … #define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX … #define mmCRTCV1_CRTCV_V_SYNC_A … #define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX … #define mmCRTCV1_CRTCV_V_SYNC_A_CNTL … #define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_V_SYNC_B … #define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX … #define mmCRTCV1_CRTCV_V_SYNC_B_CNTL … #define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_DTMTEST_CNTL … #define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION … #define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_TRIGA_CNTL … #define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG … #define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmCRTCV1_CRTCV_TRIGB_CNTL … #define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG … #define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL … #define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_FLOW_CONTROL … #define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE … #define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmCRTCV1_CRTCV_AVSYNC_COUNTER … #define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX … #define mmCRTCV1_CRTCV_CONTROL … #define mmCRTCV1_CRTCV_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_BLANK_CONTROL … #define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_INTERLACE_CONTROL … #define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_INTERLACE_STATUS … #define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL … #define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 … #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX … #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 … #define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX … #define mmCRTCV1_CRTCV_STATUS … #define mmCRTCV1_CRTCV_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_STATUS_POSITION … #define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_NOM_VERT_POSITION … #define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT … #define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX … #define mmCRTCV1_CRTCV_STATUS_VF_COUNT … #define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX … #define mmCRTCV1_CRTCV_STATUS_HV_COUNT … #define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX … #define mmCRTCV1_CRTCV_COUNT_CONTROL … #define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_COUNT_RESET … #define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX … #define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL … #define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_STEREO_STATUS … #define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_STEREO_CONTROL … #define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_SNAPSHOT_STATUS … #define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL … #define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_SNAPSHOT_POSITION … #define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_SNAPSHOT_FRAME … #define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX … #define mmCRTCV1_CRTCV_START_LINE_CONTROL … #define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_INTERRUPT_CONTROL … #define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_UPDATE_LOCK … #define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX … #define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL … #define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE … #define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX … #define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL … #define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS … #define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR … #define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX … #define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK … #define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX … #define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE … #define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX … #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT … #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX … #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER … #define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX … #define mmCRTCV1_CRTCV_MVP_STATUS … #define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_MASTER_EN … #define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX … #define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT … #define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX … #define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS … #define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX … #define mmCRTCV1_CRTCV_OVERSCAN_COLOR … #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX … #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT … #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX … #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR … #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX … #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT … #define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmCRTCV1_CRTCV_BLACK_COLOR … #define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX … #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT … #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL … #define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC_CNTL … #define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL … #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL … #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL … #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL … #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_DATA_RG … #define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX … #define mmCRTCV1_CRTCV_CRC0_DATA_B … #define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL … #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL … #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL … #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL … #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_DATA_RG … #define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX … #define mmCRTCV1_CRTCV_CRC1_DATA_B … #define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL … #define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL … #define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmCRTCV1_CRTCV_GSL_VSYNC_GAP … #define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX … #define mmCRTCV1_CRTCV_GSL_WINDOW … #define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX … #define mmCRTCV1_CRTCV_GSL_CONTROL … #define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX … // addressBlock: dce_dc_hpd0_dispdec // base address: 0x0 #define mmHPD0_DC_HPD_INT_STATUS … #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD0_DC_HPD_INT_CONTROL … #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_CONTROL … #define mmHPD0_DC_HPD_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_hpd1_dispdec // base address: 0x20 #define mmHPD1_DC_HPD_INT_STATUS … #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD1_DC_HPD_INT_CONTROL … #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_CONTROL … #define mmHPD1_DC_HPD_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_hpd2_dispdec // base address: 0x40 #define mmHPD2_DC_HPD_INT_STATUS … #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD2_DC_HPD_INT_CONTROL … #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD2_DC_HPD_CONTROL … #define mmHPD2_DC_HPD_CONTROL_BASE_IDX … #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_hpd3_dispdec // base address: 0x60 #define mmHPD3_DC_HPD_INT_STATUS … #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD3_DC_HPD_INT_CONTROL … #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD3_DC_HPD_CONTROL … #define mmHPD3_DC_HPD_CONTROL_BASE_IDX … #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_hpd4_dispdec // base address: 0x80 #define mmHPD4_DC_HPD_INT_STATUS … #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD4_DC_HPD_INT_CONTROL … #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD4_DC_HPD_CONTROL … #define mmHPD4_DC_HPD_CONTROL_BASE_IDX … #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_hpd5_dispdec // base address: 0xa0 #define mmHPD5_DC_HPD_INT_STATUS … #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD5_DC_HPD_INT_CONTROL … #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD5_DC_HPD_CONTROL … #define mmHPD5_DC_HPD_CONTROL_BASE_IDX … #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dc_perfmon2_dispdec // base address: 0x5840 #define mmDC_PERFMON2_PERFCOUNTER_CNTL … #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON2_PERFCOUNTER_STATE … #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CNTL … #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CNTL2 … #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CVALUE_LOW … #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON2_PERFMON_HI … #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON2_PERFMON_LOW … #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dp_aux0_dispdec // base address: 0x0 #define mmDP_AUX0_AUX_CONTROL … #define mmDP_AUX0_AUX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_CONTROL … #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_ARB_CONTROL … #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_STATUS … #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_LS_STATUS … #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_SW_DATA … #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX0_AUX_LS_DATA … #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_STATUS … #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_STATUS … #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dp_aux1_dispdec // base address: 0x70 #define mmDP_AUX1_AUX_CONTROL … #define mmDP_AUX1_AUX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_CONTROL … #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_ARB_CONTROL … #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_STATUS … #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_LS_STATUS … #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_SW_DATA … #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX1_AUX_LS_DATA … #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_STATUS … #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_STATUS … #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dp_aux2_dispdec // base address: 0xe0 #define mmDP_AUX2_AUX_CONTROL … #define mmDP_AUX2_AUX_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_SW_CONTROL … #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_ARB_CONTROL … #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_INTERRUPT_CONTROL … #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_SW_STATUS … #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_LS_STATUS … #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_SW_DATA … #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX2_AUX_LS_DATA … #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_STATUS … #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_STATUS … #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dp_aux3_dispdec // base address: 0x150 #define mmDP_AUX3_AUX_CONTROL … #define mmDP_AUX3_AUX_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_SW_CONTROL … #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_ARB_CONTROL … #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_INTERRUPT_CONTROL … #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_SW_STATUS … #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_LS_STATUS … #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_SW_DATA … #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX3_AUX_LS_DATA … #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_STATUS … #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_STATUS … #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dp_aux4_dispdec // base address: 0x1c0 #define mmDP_AUX4_AUX_CONTROL … #define mmDP_AUX4_AUX_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_SW_CONTROL … #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_ARB_CONTROL … #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_INTERRUPT_CONTROL … #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_SW_STATUS … #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_LS_STATUS … #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_SW_DATA … #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX4_AUX_LS_DATA … #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_STATUS … #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_STATUS … #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dp_aux5_dispdec // base address: 0x230 #define mmDP_AUX5_AUX_CONTROL … #define mmDP_AUX5_AUX_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_SW_CONTROL … #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_ARB_CONTROL … #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_INTERRUPT_CONTROL … #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_SW_STATUS … #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_LS_STATUS … #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_SW_DATA … #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX5_AUX_LS_DATA … #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_STATUS … #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_STATUS … #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dig0_dispdec // base address: 0x0 #define mmDIG0_DIG_FE_CNTL … #define mmDIG0_DIG_FE_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_CNTL … #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_RESULT … #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG0_DIG_CLOCK_PATTERN … #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG0_DIG_TEST_PATTERN … #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG0_DIG_RANDOM_PATTERN_SEED … #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG0_DIG_FIFO_STATUS … #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG0_HDMI_CONTROL … #define mmDIG0_HDMI_CONTROL_BASE_IDX … #define mmDIG0_HDMI_STATUS … #define mmDIG0_HDMI_STATUS_BASE_IDX … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_ACR_PACKET_CONTROL … #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_VBI_PACKET_CONTROL … #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL0 … #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL1 … #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_INTERRUPT_STATUS … #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG0_HDMI_GC … #define mmDIG0_HDMI_GC_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_0 … #define mmDIG0_AFMT_ISRC1_0_BASE_IDX … #define mmDIG0_AFMT_ISRC1_1 … #define mmDIG0_AFMT_ISRC1_1_BASE_IDX … #define mmDIG0_AFMT_ISRC1_2 … #define mmDIG0_AFMT_ISRC1_2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_3 … #define mmDIG0_AFMT_ISRC1_3_BASE_IDX … #define mmDIG0_AFMT_ISRC1_4 … #define mmDIG0_AFMT_ISRC1_4_BASE_IDX … #define mmDIG0_AFMT_ISRC2_0 … #define mmDIG0_AFMT_ISRC2_0_BASE_IDX … #define mmDIG0_AFMT_ISRC2_1 … #define mmDIG0_AFMT_ISRC2_1_BASE_IDX … #define mmDIG0_AFMT_ISRC2_2 … #define mmDIG0_AFMT_ISRC2_2_BASE_IDX … #define mmDIG0_AFMT_ISRC2_3 … #define mmDIG0_AFMT_ISRC2_3_BASE_IDX … #define mmDIG0_AFMT_AVI_INFO0 … #define mmDIG0_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG0_AFMT_AVI_INFO1 … #define mmDIG0_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG0_AFMT_AVI_INFO2 … #define mmDIG0_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG0_AFMT_AVI_INFO3 … #define mmDIG0_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO0 … #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO1 … #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_HDR … #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG0_AFMT_GENERIC_0 … #define mmDIG0_AFMT_GENERIC_0_BASE_IDX … #define mmDIG0_AFMT_GENERIC_1 … #define mmDIG0_AFMT_GENERIC_1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_2 … #define mmDIG0_AFMT_GENERIC_2_BASE_IDX … #define mmDIG0_AFMT_GENERIC_3 … #define mmDIG0_AFMT_GENERIC_3_BASE_IDX … #define mmDIG0_AFMT_GENERIC_4 … #define mmDIG0_AFMT_GENERIC_4_BASE_IDX … #define mmDIG0_AFMT_GENERIC_5 … #define mmDIG0_AFMT_GENERIC_5_BASE_IDX … #define mmDIG0_AFMT_GENERIC_6 … #define mmDIG0_AFMT_GENERIC_6_BASE_IDX … #define mmDIG0_AFMT_GENERIC_7 … #define mmDIG0_AFMT_GENERIC_7_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_ACR_32_0 … #define mmDIG0_HDMI_ACR_32_0_BASE_IDX … #define mmDIG0_HDMI_ACR_32_1 … #define mmDIG0_HDMI_ACR_32_1_BASE_IDX … #define mmDIG0_HDMI_ACR_44_0 … #define mmDIG0_HDMI_ACR_44_0_BASE_IDX … #define mmDIG0_HDMI_ACR_44_1 … #define mmDIG0_HDMI_ACR_44_1_BASE_IDX … #define mmDIG0_HDMI_ACR_48_0 … #define mmDIG0_HDMI_ACR_48_0_BASE_IDX … #define mmDIG0_HDMI_ACR_48_1 … #define mmDIG0_HDMI_ACR_48_1_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_0 … #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_1 … #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO0 … #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO1 … #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG0_AFMT_60958_0 … #define mmDIG0_AFMT_60958_0_BASE_IDX … #define mmDIG0_AFMT_60958_1 … #define mmDIG0_AFMT_60958_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL0 … #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL1 … #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL2 … #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL3 … #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG0_AFMT_60958_2 … #define mmDIG0_AFMT_60958_2_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_RESULT … #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG0_AFMT_STATUS … #define mmDIG0_AFMT_STATUS_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_VBI_PACKET_CONTROL … #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_INFOFRAME_CONTROL0 … #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG0_DIG_BE_CNTL … #define mmDIG0_DIG_BE_CNTL_BASE_IDX … #define mmDIG0_DIG_BE_EN_CNTL … #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CNTL … #define mmDIG0_TMDS_CNTL_BASE_IDX … #define mmDIG0_TMDS_CONTROL_CHAR … #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG0_TMDS_CONTROL0_FEEDBACK … #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG0_TMDS_CTL_BITS … #define mmDIG0_TMDS_CTL_BITS_BASE_IDX … #define mmDIG0_TMDS_DCBALANCER_CONTROL … #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG0_DIG_VERSION … #define mmDIG0_DIG_VERSION_BASE_IDX … #define mmDIG0_DIG_LANE_ENABLE … #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG0_AFMT_CNTL … #define mmDIG0_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp0_dispdec // base address: 0x0 #define mmDP0_DP_LINK_CNTL … #define mmDP0_DP_LINK_CNTL_BASE_IDX … #define mmDP0_DP_PIXEL_FORMAT … #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP0_DP_MSA_COLORIMETRY … #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP0_DP_CONFIG … #define mmDP0_DP_CONFIG_BASE_IDX … #define mmDP0_DP_VID_STREAM_CNTL … #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP0_DP_STEER_FIFO … #define mmDP0_DP_STEER_FIFO_BASE_IDX … #define mmDP0_DP_MSA_MISC … #define mmDP0_DP_MSA_MISC_BASE_IDX … #define mmDP0_DP_VID_TIMING … #define mmDP0_DP_VID_TIMING_BASE_IDX … #define mmDP0_DP_VID_N … #define mmDP0_DP_VID_N_BASE_IDX … #define mmDP0_DP_VID_M … #define mmDP0_DP_VID_M_BASE_IDX … #define mmDP0_DP_LINK_FRAMING_CNTL … #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP0_DP_HBR2_EYE_PATTERN … #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP0_DP_VID_MSA_VBID … #define mmDP0_DP_VID_MSA_VBID_BASE_IDX … #define mmDP0_DP_VID_INTERRUPT_CNTL … #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CNTL … #define mmDP0_DP_DPHY_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP0_DP_DPHY_SYM0 … #define mmDP0_DP_DPHY_SYM0_BASE_IDX … #define mmDP0_DP_DPHY_SYM1 … #define mmDP0_DP_DPHY_SYM1_BASE_IDX … #define mmDP0_DP_DPHY_SYM2 … #define mmDP0_DP_DPHY_SYM2_BASE_IDX … #define mmDP0_DP_DPHY_8B10B_CNTL … #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_PRBS_CNTL … #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_SCRAM_CNTL … #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_EN … #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP0_DP_DPHY_CRC_CNTL … #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_RESULT … #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_CNTL … #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_STATUS … #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING … #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP0_DP_SEC_CNTL … #define mmDP0_DP_SEC_CNTL_BASE_IDX … #define mmDP0_DP_SEC_CNTL1 … #define mmDP0_DP_SEC_CNTL1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING1 … #define mmDP0_DP_SEC_FRAMING1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING2 … #define mmDP0_DP_SEC_FRAMING2_BASE_IDX … #define mmDP0_DP_SEC_FRAMING3 … #define mmDP0_DP_SEC_FRAMING3_BASE_IDX … #define mmDP0_DP_SEC_FRAMING4 … #define mmDP0_DP_SEC_FRAMING4_BASE_IDX … #define mmDP0_DP_SEC_AUD_N … #define mmDP0_DP_SEC_AUD_N_BASE_IDX … #define mmDP0_DP_SEC_AUD_N_READBACK … #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP0_DP_SEC_AUD_M … #define mmDP0_DP_SEC_AUD_M_BASE_IDX … #define mmDP0_DP_SEC_AUD_M_READBACK … #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP0_DP_SEC_TIMESTAMP … #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP0_DP_SEC_PACKET_CNTL … #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_CNTL … #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_UPDATE … #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_SAT0 … #define mmDP0_DP_MSE_SAT0_BASE_IDX … #define mmDP0_DP_MSE_SAT1 … #define mmDP0_DP_MSE_SAT1_BASE_IDX … #define mmDP0_DP_MSE_SAT2 … #define mmDP0_DP_MSE_SAT2_BASE_IDX … #define mmDP0_DP_MSE_SAT_UPDATE … #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_LINK_TIMING … #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP0_DP_MSE_MISC_CNTL … #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP0_DP_MSE_SAT0_STATUS … #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT1_STATUS … #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT2_STATUS … #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig1_dispdec // base address: 0x400 #define mmDIG1_DIG_FE_CNTL … #define mmDIG1_DIG_FE_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_CNTL … #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_RESULT … #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG1_DIG_CLOCK_PATTERN … #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG1_DIG_TEST_PATTERN … #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG1_DIG_RANDOM_PATTERN_SEED … #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG1_DIG_FIFO_STATUS … #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG1_HDMI_CONTROL … #define mmDIG1_HDMI_CONTROL_BASE_IDX … #define mmDIG1_HDMI_STATUS … #define mmDIG1_HDMI_STATUS_BASE_IDX … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_ACR_PACKET_CONTROL … #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_VBI_PACKET_CONTROL … #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL0 … #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL1 … #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_INTERRUPT_STATUS … #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG1_HDMI_GC … #define mmDIG1_HDMI_GC_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_0 … #define mmDIG1_AFMT_ISRC1_0_BASE_IDX … #define mmDIG1_AFMT_ISRC1_1 … #define mmDIG1_AFMT_ISRC1_1_BASE_IDX … #define mmDIG1_AFMT_ISRC1_2 … #define mmDIG1_AFMT_ISRC1_2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_3 … #define mmDIG1_AFMT_ISRC1_3_BASE_IDX … #define mmDIG1_AFMT_ISRC1_4 … #define mmDIG1_AFMT_ISRC1_4_BASE_IDX … #define mmDIG1_AFMT_ISRC2_0 … #define mmDIG1_AFMT_ISRC2_0_BASE_IDX … #define mmDIG1_AFMT_ISRC2_1 … #define mmDIG1_AFMT_ISRC2_1_BASE_IDX … #define mmDIG1_AFMT_ISRC2_2 … #define mmDIG1_AFMT_ISRC2_2_BASE_IDX … #define mmDIG1_AFMT_ISRC2_3 … #define mmDIG1_AFMT_ISRC2_3_BASE_IDX … #define mmDIG1_AFMT_AVI_INFO0 … #define mmDIG1_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG1_AFMT_AVI_INFO1 … #define mmDIG1_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG1_AFMT_AVI_INFO2 … #define mmDIG1_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG1_AFMT_AVI_INFO3 … #define mmDIG1_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO0 … #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO1 … #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_HDR … #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG1_AFMT_GENERIC_0 … #define mmDIG1_AFMT_GENERIC_0_BASE_IDX … #define mmDIG1_AFMT_GENERIC_1 … #define mmDIG1_AFMT_GENERIC_1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_2 … #define mmDIG1_AFMT_GENERIC_2_BASE_IDX … #define mmDIG1_AFMT_GENERIC_3 … #define mmDIG1_AFMT_GENERIC_3_BASE_IDX … #define mmDIG1_AFMT_GENERIC_4 … #define mmDIG1_AFMT_GENERIC_4_BASE_IDX … #define mmDIG1_AFMT_GENERIC_5 … #define mmDIG1_AFMT_GENERIC_5_BASE_IDX … #define mmDIG1_AFMT_GENERIC_6 … #define mmDIG1_AFMT_GENERIC_6_BASE_IDX … #define mmDIG1_AFMT_GENERIC_7 … #define mmDIG1_AFMT_GENERIC_7_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_ACR_32_0 … #define mmDIG1_HDMI_ACR_32_0_BASE_IDX … #define mmDIG1_HDMI_ACR_32_1 … #define mmDIG1_HDMI_ACR_32_1_BASE_IDX … #define mmDIG1_HDMI_ACR_44_0 … #define mmDIG1_HDMI_ACR_44_0_BASE_IDX … #define mmDIG1_HDMI_ACR_44_1 … #define mmDIG1_HDMI_ACR_44_1_BASE_IDX … #define mmDIG1_HDMI_ACR_48_0 … #define mmDIG1_HDMI_ACR_48_0_BASE_IDX … #define mmDIG1_HDMI_ACR_48_1 … #define mmDIG1_HDMI_ACR_48_1_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_0 … #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_1 … #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO0 … #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO1 … #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG1_AFMT_60958_0 … #define mmDIG1_AFMT_60958_0_BASE_IDX … #define mmDIG1_AFMT_60958_1 … #define mmDIG1_AFMT_60958_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL0 … #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL1 … #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL2 … #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL3 … #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG1_AFMT_60958_2 … #define mmDIG1_AFMT_60958_2_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_RESULT … #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG1_AFMT_STATUS … #define mmDIG1_AFMT_STATUS_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_VBI_PACKET_CONTROL … #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_INFOFRAME_CONTROL0 … #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG1_DIG_BE_CNTL … #define mmDIG1_DIG_BE_CNTL_BASE_IDX … #define mmDIG1_DIG_BE_EN_CNTL … #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CNTL … #define mmDIG1_TMDS_CNTL_BASE_IDX … #define mmDIG1_TMDS_CONTROL_CHAR … #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG1_TMDS_CONTROL0_FEEDBACK … #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG1_TMDS_CTL_BITS … #define mmDIG1_TMDS_CTL_BITS_BASE_IDX … #define mmDIG1_TMDS_DCBALANCER_CONTROL … #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG1_DIG_VERSION … #define mmDIG1_DIG_VERSION_BASE_IDX … #define mmDIG1_DIG_LANE_ENABLE … #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG1_AFMT_CNTL … #define mmDIG1_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp1_dispdec // base address: 0x400 #define mmDP1_DP_LINK_CNTL … #define mmDP1_DP_LINK_CNTL_BASE_IDX … #define mmDP1_DP_PIXEL_FORMAT … #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP1_DP_MSA_COLORIMETRY … #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP1_DP_CONFIG … #define mmDP1_DP_CONFIG_BASE_IDX … #define mmDP1_DP_VID_STREAM_CNTL … #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP1_DP_STEER_FIFO … #define mmDP1_DP_STEER_FIFO_BASE_IDX … #define mmDP1_DP_MSA_MISC … #define mmDP1_DP_MSA_MISC_BASE_IDX … #define mmDP1_DP_VID_TIMING … #define mmDP1_DP_VID_TIMING_BASE_IDX … #define mmDP1_DP_VID_N … #define mmDP1_DP_VID_N_BASE_IDX … #define mmDP1_DP_VID_M … #define mmDP1_DP_VID_M_BASE_IDX … #define mmDP1_DP_LINK_FRAMING_CNTL … #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP1_DP_HBR2_EYE_PATTERN … #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP1_DP_VID_MSA_VBID … #define mmDP1_DP_VID_MSA_VBID_BASE_IDX … #define mmDP1_DP_VID_INTERRUPT_CNTL … #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CNTL … #define mmDP1_DP_DPHY_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP1_DP_DPHY_SYM0 … #define mmDP1_DP_DPHY_SYM0_BASE_IDX … #define mmDP1_DP_DPHY_SYM1 … #define mmDP1_DP_DPHY_SYM1_BASE_IDX … #define mmDP1_DP_DPHY_SYM2 … #define mmDP1_DP_DPHY_SYM2_BASE_IDX … #define mmDP1_DP_DPHY_8B10B_CNTL … #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_PRBS_CNTL … #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_SCRAM_CNTL … #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_EN … #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP1_DP_DPHY_CRC_CNTL … #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_RESULT … #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_CNTL … #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_STATUS … #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING … #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP1_DP_SEC_CNTL … #define mmDP1_DP_SEC_CNTL_BASE_IDX … #define mmDP1_DP_SEC_CNTL1 … #define mmDP1_DP_SEC_CNTL1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING1 … #define mmDP1_DP_SEC_FRAMING1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING2 … #define mmDP1_DP_SEC_FRAMING2_BASE_IDX … #define mmDP1_DP_SEC_FRAMING3 … #define mmDP1_DP_SEC_FRAMING3_BASE_IDX … #define mmDP1_DP_SEC_FRAMING4 … #define mmDP1_DP_SEC_FRAMING4_BASE_IDX … #define mmDP1_DP_SEC_AUD_N … #define mmDP1_DP_SEC_AUD_N_BASE_IDX … #define mmDP1_DP_SEC_AUD_N_READBACK … #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP1_DP_SEC_AUD_M … #define mmDP1_DP_SEC_AUD_M_BASE_IDX … #define mmDP1_DP_SEC_AUD_M_READBACK … #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP1_DP_SEC_TIMESTAMP … #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP1_DP_SEC_PACKET_CNTL … #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_CNTL … #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_UPDATE … #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_SAT0 … #define mmDP1_DP_MSE_SAT0_BASE_IDX … #define mmDP1_DP_MSE_SAT1 … #define mmDP1_DP_MSE_SAT1_BASE_IDX … #define mmDP1_DP_MSE_SAT2 … #define mmDP1_DP_MSE_SAT2_BASE_IDX … #define mmDP1_DP_MSE_SAT_UPDATE … #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_LINK_TIMING … #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP1_DP_MSE_MISC_CNTL … #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP1_DP_MSE_SAT0_STATUS … #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT1_STATUS … #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT2_STATUS … #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig2_dispdec // base address: 0x800 #define mmDIG2_DIG_FE_CNTL … #define mmDIG2_DIG_FE_CNTL_BASE_IDX … #define mmDIG2_DIG_OUTPUT_CRC_CNTL … #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG2_DIG_OUTPUT_CRC_RESULT … #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG2_DIG_CLOCK_PATTERN … #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG2_DIG_TEST_PATTERN … #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG2_DIG_RANDOM_PATTERN_SEED … #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG2_DIG_FIFO_STATUS … #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG2_HDMI_CONTROL … #define mmDIG2_HDMI_CONTROL_BASE_IDX … #define mmDIG2_HDMI_STATUS … #define mmDIG2_HDMI_STATUS_BASE_IDX … #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_ACR_PACKET_CONTROL … #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_VBI_PACKET_CONTROL … #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_INFOFRAME_CONTROL0 … #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG2_HDMI_INFOFRAME_CONTROL1 … #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_INTERRUPT_STATUS … #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG2_HDMI_GC … #define mmDIG2_HDMI_GC_BASE_IDX … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG2_AFMT_ISRC1_0 … #define mmDIG2_AFMT_ISRC1_0_BASE_IDX … #define mmDIG2_AFMT_ISRC1_1 … #define mmDIG2_AFMT_ISRC1_1_BASE_IDX … #define mmDIG2_AFMT_ISRC1_2 … #define mmDIG2_AFMT_ISRC1_2_BASE_IDX … #define mmDIG2_AFMT_ISRC1_3 … #define mmDIG2_AFMT_ISRC1_3_BASE_IDX … #define mmDIG2_AFMT_ISRC1_4 … #define mmDIG2_AFMT_ISRC1_4_BASE_IDX … #define mmDIG2_AFMT_ISRC2_0 … #define mmDIG2_AFMT_ISRC2_0_BASE_IDX … #define mmDIG2_AFMT_ISRC2_1 … #define mmDIG2_AFMT_ISRC2_1_BASE_IDX … #define mmDIG2_AFMT_ISRC2_2 … #define mmDIG2_AFMT_ISRC2_2_BASE_IDX … #define mmDIG2_AFMT_ISRC2_3 … #define mmDIG2_AFMT_ISRC2_3_BASE_IDX … #define mmDIG2_AFMT_AVI_INFO0 … #define mmDIG2_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG2_AFMT_AVI_INFO1 … #define mmDIG2_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG2_AFMT_AVI_INFO2 … #define mmDIG2_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG2_AFMT_AVI_INFO3 … #define mmDIG2_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG2_AFMT_MPEG_INFO0 … #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG2_AFMT_MPEG_INFO1 … #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG2_AFMT_GENERIC_HDR … #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG2_AFMT_GENERIC_0 … #define mmDIG2_AFMT_GENERIC_0_BASE_IDX … #define mmDIG2_AFMT_GENERIC_1 … #define mmDIG2_AFMT_GENERIC_1_BASE_IDX … #define mmDIG2_AFMT_GENERIC_2 … #define mmDIG2_AFMT_GENERIC_2_BASE_IDX … #define mmDIG2_AFMT_GENERIC_3 … #define mmDIG2_AFMT_GENERIC_3_BASE_IDX … #define mmDIG2_AFMT_GENERIC_4 … #define mmDIG2_AFMT_GENERIC_4_BASE_IDX … #define mmDIG2_AFMT_GENERIC_5 … #define mmDIG2_AFMT_GENERIC_5_BASE_IDX … #define mmDIG2_AFMT_GENERIC_6 … #define mmDIG2_AFMT_GENERIC_6_BASE_IDX … #define mmDIG2_AFMT_GENERIC_7 … #define mmDIG2_AFMT_GENERIC_7_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG2_HDMI_ACR_32_0 … #define mmDIG2_HDMI_ACR_32_0_BASE_IDX … #define mmDIG2_HDMI_ACR_32_1 … #define mmDIG2_HDMI_ACR_32_1_BASE_IDX … #define mmDIG2_HDMI_ACR_44_0 … #define mmDIG2_HDMI_ACR_44_0_BASE_IDX … #define mmDIG2_HDMI_ACR_44_1 … #define mmDIG2_HDMI_ACR_44_1_BASE_IDX … #define mmDIG2_HDMI_ACR_48_0 … #define mmDIG2_HDMI_ACR_48_0_BASE_IDX … #define mmDIG2_HDMI_ACR_48_1 … #define mmDIG2_HDMI_ACR_48_1_BASE_IDX … #define mmDIG2_HDMI_ACR_STATUS_0 … #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG2_HDMI_ACR_STATUS_1 … #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG2_AFMT_AUDIO_INFO0 … #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG2_AFMT_AUDIO_INFO1 … #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG2_AFMT_60958_0 … #define mmDIG2_AFMT_60958_0_BASE_IDX … #define mmDIG2_AFMT_60958_1 … #define mmDIG2_AFMT_60958_1_BASE_IDX … #define mmDIG2_AFMT_AUDIO_CRC_CONTROL … #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL0 … #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL1 … #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL2 … #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL3 … #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG2_AFMT_60958_2 … #define mmDIG2_AFMT_60958_2_BASE_IDX … #define mmDIG2_AFMT_AUDIO_CRC_RESULT … #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG2_AFMT_STATUS … #define mmDIG2_AFMT_STATUS_BASE_IDX … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG2_AFMT_VBI_PACKET_CONTROL … #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG2_AFMT_INFOFRAME_CONTROL0 … #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_AUDIO_SRC_CONTROL … #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG2_DIG_BE_CNTL … #define mmDIG2_DIG_BE_CNTL_BASE_IDX … #define mmDIG2_DIG_BE_EN_CNTL … #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG2_TMDS_CNTL … #define mmDIG2_TMDS_CNTL_BASE_IDX … #define mmDIG2_TMDS_CONTROL_CHAR … #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG2_TMDS_CONTROL0_FEEDBACK … #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG2_TMDS_CTL_BITS … #define mmDIG2_TMDS_CTL_BITS_BASE_IDX … #define mmDIG2_TMDS_DCBALANCER_CONTROL … #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG2_TMDS_CTL0_1_GEN_CNTL … #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG2_TMDS_CTL2_3_GEN_CNTL … #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG2_DIG_VERSION … #define mmDIG2_DIG_VERSION_BASE_IDX … #define mmDIG2_DIG_LANE_ENABLE … #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG2_AFMT_CNTL … #define mmDIG2_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp2_dispdec // base address: 0x800 #define mmDP2_DP_LINK_CNTL … #define mmDP2_DP_LINK_CNTL_BASE_IDX … #define mmDP2_DP_PIXEL_FORMAT … #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP2_DP_MSA_COLORIMETRY … #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP2_DP_CONFIG … #define mmDP2_DP_CONFIG_BASE_IDX … #define mmDP2_DP_VID_STREAM_CNTL … #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP2_DP_STEER_FIFO … #define mmDP2_DP_STEER_FIFO_BASE_IDX … #define mmDP2_DP_MSA_MISC … #define mmDP2_DP_MSA_MISC_BASE_IDX … #define mmDP2_DP_VID_TIMING … #define mmDP2_DP_VID_TIMING_BASE_IDX … #define mmDP2_DP_VID_N … #define mmDP2_DP_VID_N_BASE_IDX … #define mmDP2_DP_VID_M … #define mmDP2_DP_VID_M_BASE_IDX … #define mmDP2_DP_LINK_FRAMING_CNTL … #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP2_DP_HBR2_EYE_PATTERN … #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP2_DP_VID_MSA_VBID … #define mmDP2_DP_VID_MSA_VBID_BASE_IDX … #define mmDP2_DP_VID_INTERRUPT_CNTL … #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CNTL … #define mmDP2_DP_DPHY_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP2_DP_DPHY_SYM0 … #define mmDP2_DP_DPHY_SYM0_BASE_IDX … #define mmDP2_DP_DPHY_SYM1 … #define mmDP2_DP_DPHY_SYM1_BASE_IDX … #define mmDP2_DP_DPHY_SYM2 … #define mmDP2_DP_DPHY_SYM2_BASE_IDX … #define mmDP2_DP_DPHY_8B10B_CNTL … #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_PRBS_CNTL … #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_SCRAM_CNTL … #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_EN … #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP2_DP_DPHY_CRC_CNTL … #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_RESULT … #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP2_DP_DPHY_CRC_MST_CNTL … #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_MST_STATUS … #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP2_DP_DPHY_FAST_TRAINING … #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP2_DP_SEC_CNTL … #define mmDP2_DP_SEC_CNTL_BASE_IDX … #define mmDP2_DP_SEC_CNTL1 … #define mmDP2_DP_SEC_CNTL1_BASE_IDX … #define mmDP2_DP_SEC_FRAMING1 … #define mmDP2_DP_SEC_FRAMING1_BASE_IDX … #define mmDP2_DP_SEC_FRAMING2 … #define mmDP2_DP_SEC_FRAMING2_BASE_IDX … #define mmDP2_DP_SEC_FRAMING3 … #define mmDP2_DP_SEC_FRAMING3_BASE_IDX … #define mmDP2_DP_SEC_FRAMING4 … #define mmDP2_DP_SEC_FRAMING4_BASE_IDX … #define mmDP2_DP_SEC_AUD_N … #define mmDP2_DP_SEC_AUD_N_BASE_IDX … #define mmDP2_DP_SEC_AUD_N_READBACK … #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP2_DP_SEC_AUD_M … #define mmDP2_DP_SEC_AUD_M_BASE_IDX … #define mmDP2_DP_SEC_AUD_M_READBACK … #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP2_DP_SEC_TIMESTAMP … #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP2_DP_SEC_PACKET_CNTL … #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP2_DP_MSE_RATE_CNTL … #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP2_DP_MSE_RATE_UPDATE … #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP2_DP_MSE_SAT0 … #define mmDP2_DP_MSE_SAT0_BASE_IDX … #define mmDP2_DP_MSE_SAT1 … #define mmDP2_DP_MSE_SAT1_BASE_IDX … #define mmDP2_DP_MSE_SAT2 … #define mmDP2_DP_MSE_SAT2_BASE_IDX … #define mmDP2_DP_MSE_SAT_UPDATE … #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP2_DP_MSE_LINK_TIMING … #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP2_DP_MSE_MISC_CNTL … #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP2_DP_MSE_SAT0_STATUS … #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP2_DP_MSE_SAT1_STATUS … #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP2_DP_MSE_SAT2_STATUS … #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig3_dispdec // base address: 0xc00 #define mmDIG3_DIG_FE_CNTL … #define mmDIG3_DIG_FE_CNTL_BASE_IDX … #define mmDIG3_DIG_OUTPUT_CRC_CNTL … #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG3_DIG_OUTPUT_CRC_RESULT … #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG3_DIG_CLOCK_PATTERN … #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG3_DIG_TEST_PATTERN … #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG3_DIG_RANDOM_PATTERN_SEED … #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG3_DIG_FIFO_STATUS … #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG3_HDMI_CONTROL … #define mmDIG3_HDMI_CONTROL_BASE_IDX … #define mmDIG3_HDMI_STATUS … #define mmDIG3_HDMI_STATUS_BASE_IDX … #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_ACR_PACKET_CONTROL … #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_VBI_PACKET_CONTROL … #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_INFOFRAME_CONTROL0 … #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG3_HDMI_INFOFRAME_CONTROL1 … #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_INTERRUPT_STATUS … #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG3_HDMI_GC … #define mmDIG3_HDMI_GC_BASE_IDX … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG3_AFMT_ISRC1_0 … #define mmDIG3_AFMT_ISRC1_0_BASE_IDX … #define mmDIG3_AFMT_ISRC1_1 … #define mmDIG3_AFMT_ISRC1_1_BASE_IDX … #define mmDIG3_AFMT_ISRC1_2 … #define mmDIG3_AFMT_ISRC1_2_BASE_IDX … #define mmDIG3_AFMT_ISRC1_3 … #define mmDIG3_AFMT_ISRC1_3_BASE_IDX … #define mmDIG3_AFMT_ISRC1_4 … #define mmDIG3_AFMT_ISRC1_4_BASE_IDX … #define mmDIG3_AFMT_ISRC2_0 … #define mmDIG3_AFMT_ISRC2_0_BASE_IDX … #define mmDIG3_AFMT_ISRC2_1 … #define mmDIG3_AFMT_ISRC2_1_BASE_IDX … #define mmDIG3_AFMT_ISRC2_2 … #define mmDIG3_AFMT_ISRC2_2_BASE_IDX … #define mmDIG3_AFMT_ISRC2_3 … #define mmDIG3_AFMT_ISRC2_3_BASE_IDX … #define mmDIG3_AFMT_AVI_INFO0 … #define mmDIG3_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG3_AFMT_AVI_INFO1 … #define mmDIG3_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG3_AFMT_AVI_INFO2 … #define mmDIG3_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG3_AFMT_AVI_INFO3 … #define mmDIG3_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG3_AFMT_MPEG_INFO0 … #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG3_AFMT_MPEG_INFO1 … #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG3_AFMT_GENERIC_HDR … #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG3_AFMT_GENERIC_0 … #define mmDIG3_AFMT_GENERIC_0_BASE_IDX … #define mmDIG3_AFMT_GENERIC_1 … #define mmDIG3_AFMT_GENERIC_1_BASE_IDX … #define mmDIG3_AFMT_GENERIC_2 … #define mmDIG3_AFMT_GENERIC_2_BASE_IDX … #define mmDIG3_AFMT_GENERIC_3 … #define mmDIG3_AFMT_GENERIC_3_BASE_IDX … #define mmDIG3_AFMT_GENERIC_4 … #define mmDIG3_AFMT_GENERIC_4_BASE_IDX … #define mmDIG3_AFMT_GENERIC_5 … #define mmDIG3_AFMT_GENERIC_5_BASE_IDX … #define mmDIG3_AFMT_GENERIC_6 … #define mmDIG3_AFMT_GENERIC_6_BASE_IDX … #define mmDIG3_AFMT_GENERIC_7 … #define mmDIG3_AFMT_GENERIC_7_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG3_HDMI_ACR_32_0 … #define mmDIG3_HDMI_ACR_32_0_BASE_IDX … #define mmDIG3_HDMI_ACR_32_1 … #define mmDIG3_HDMI_ACR_32_1_BASE_IDX … #define mmDIG3_HDMI_ACR_44_0 … #define mmDIG3_HDMI_ACR_44_0_BASE_IDX … #define mmDIG3_HDMI_ACR_44_1 … #define mmDIG3_HDMI_ACR_44_1_BASE_IDX … #define mmDIG3_HDMI_ACR_48_0 … #define mmDIG3_HDMI_ACR_48_0_BASE_IDX … #define mmDIG3_HDMI_ACR_48_1 … #define mmDIG3_HDMI_ACR_48_1_BASE_IDX … #define mmDIG3_HDMI_ACR_STATUS_0 … #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG3_HDMI_ACR_STATUS_1 … #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG3_AFMT_AUDIO_INFO0 … #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG3_AFMT_AUDIO_INFO1 … #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG3_AFMT_60958_0 … #define mmDIG3_AFMT_60958_0_BASE_IDX … #define mmDIG3_AFMT_60958_1 … #define mmDIG3_AFMT_60958_1_BASE_IDX … #define mmDIG3_AFMT_AUDIO_CRC_CONTROL … #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL0 … #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL1 … #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL2 … #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL3 … #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG3_AFMT_60958_2 … #define mmDIG3_AFMT_60958_2_BASE_IDX … #define mmDIG3_AFMT_AUDIO_CRC_RESULT … #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG3_AFMT_STATUS … #define mmDIG3_AFMT_STATUS_BASE_IDX … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG3_AFMT_VBI_PACKET_CONTROL … #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG3_AFMT_INFOFRAME_CONTROL0 … #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_AUDIO_SRC_CONTROL … #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG3_DIG_BE_CNTL … #define mmDIG3_DIG_BE_CNTL_BASE_IDX … #define mmDIG3_DIG_BE_EN_CNTL … #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG3_TMDS_CNTL … #define mmDIG3_TMDS_CNTL_BASE_IDX … #define mmDIG3_TMDS_CONTROL_CHAR … #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG3_TMDS_CONTROL0_FEEDBACK … #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG3_TMDS_CTL_BITS … #define mmDIG3_TMDS_CTL_BITS_BASE_IDX … #define mmDIG3_TMDS_DCBALANCER_CONTROL … #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG3_TMDS_CTL0_1_GEN_CNTL … #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG3_TMDS_CTL2_3_GEN_CNTL … #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG3_DIG_VERSION … #define mmDIG3_DIG_VERSION_BASE_IDX … #define mmDIG3_DIG_LANE_ENABLE … #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG3_AFMT_CNTL … #define mmDIG3_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp3_dispdec // base address: 0xc00 #define mmDP3_DP_LINK_CNTL … #define mmDP3_DP_LINK_CNTL_BASE_IDX … #define mmDP3_DP_PIXEL_FORMAT … #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP3_DP_MSA_COLORIMETRY … #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP3_DP_CONFIG … #define mmDP3_DP_CONFIG_BASE_IDX … #define mmDP3_DP_VID_STREAM_CNTL … #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP3_DP_STEER_FIFO … #define mmDP3_DP_STEER_FIFO_BASE_IDX … #define mmDP3_DP_MSA_MISC … #define mmDP3_DP_MSA_MISC_BASE_IDX … #define mmDP3_DP_VID_TIMING … #define mmDP3_DP_VID_TIMING_BASE_IDX … #define mmDP3_DP_VID_N … #define mmDP3_DP_VID_N_BASE_IDX … #define mmDP3_DP_VID_M … #define mmDP3_DP_VID_M_BASE_IDX … #define mmDP3_DP_LINK_FRAMING_CNTL … #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP3_DP_HBR2_EYE_PATTERN … #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP3_DP_VID_MSA_VBID … #define mmDP3_DP_VID_MSA_VBID_BASE_IDX … #define mmDP3_DP_VID_INTERRUPT_CNTL … #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CNTL … #define mmDP3_DP_DPHY_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP3_DP_DPHY_SYM0 … #define mmDP3_DP_DPHY_SYM0_BASE_IDX … #define mmDP3_DP_DPHY_SYM1 … #define mmDP3_DP_DPHY_SYM1_BASE_IDX … #define mmDP3_DP_DPHY_SYM2 … #define mmDP3_DP_DPHY_SYM2_BASE_IDX … #define mmDP3_DP_DPHY_8B10B_CNTL … #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_PRBS_CNTL … #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_SCRAM_CNTL … #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_EN … #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP3_DP_DPHY_CRC_CNTL … #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_RESULT … #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP3_DP_DPHY_CRC_MST_CNTL … #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_MST_STATUS … #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP3_DP_DPHY_FAST_TRAINING … #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP3_DP_SEC_CNTL … #define mmDP3_DP_SEC_CNTL_BASE_IDX … #define mmDP3_DP_SEC_CNTL1 … #define mmDP3_DP_SEC_CNTL1_BASE_IDX … #define mmDP3_DP_SEC_FRAMING1 … #define mmDP3_DP_SEC_FRAMING1_BASE_IDX … #define mmDP3_DP_SEC_FRAMING2 … #define mmDP3_DP_SEC_FRAMING2_BASE_IDX … #define mmDP3_DP_SEC_FRAMING3 … #define mmDP3_DP_SEC_FRAMING3_BASE_IDX … #define mmDP3_DP_SEC_FRAMING4 … #define mmDP3_DP_SEC_FRAMING4_BASE_IDX … #define mmDP3_DP_SEC_AUD_N … #define mmDP3_DP_SEC_AUD_N_BASE_IDX … #define mmDP3_DP_SEC_AUD_N_READBACK … #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP3_DP_SEC_AUD_M … #define mmDP3_DP_SEC_AUD_M_BASE_IDX … #define mmDP3_DP_SEC_AUD_M_READBACK … #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP3_DP_SEC_TIMESTAMP … #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP3_DP_SEC_PACKET_CNTL … #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP3_DP_MSE_RATE_CNTL … #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP3_DP_MSE_RATE_UPDATE … #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP3_DP_MSE_SAT0 … #define mmDP3_DP_MSE_SAT0_BASE_IDX … #define mmDP3_DP_MSE_SAT1 … #define mmDP3_DP_MSE_SAT1_BASE_IDX … #define mmDP3_DP_MSE_SAT2 … #define mmDP3_DP_MSE_SAT2_BASE_IDX … #define mmDP3_DP_MSE_SAT_UPDATE … #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP3_DP_MSE_LINK_TIMING … #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP3_DP_MSE_MISC_CNTL … #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP3_DP_MSE_SAT0_STATUS … #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP3_DP_MSE_SAT1_STATUS … #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP3_DP_MSE_SAT2_STATUS … #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig4_dispdec // base address: 0x1000 #define mmDIG4_DIG_FE_CNTL … #define mmDIG4_DIG_FE_CNTL_BASE_IDX … #define mmDIG4_DIG_OUTPUT_CRC_CNTL … #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG4_DIG_OUTPUT_CRC_RESULT … #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG4_DIG_CLOCK_PATTERN … #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG4_DIG_TEST_PATTERN … #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG4_DIG_RANDOM_PATTERN_SEED … #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG4_DIG_FIFO_STATUS … #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG4_HDMI_CONTROL … #define mmDIG4_HDMI_CONTROL_BASE_IDX … #define mmDIG4_HDMI_STATUS … #define mmDIG4_HDMI_STATUS_BASE_IDX … #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_ACR_PACKET_CONTROL … #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_VBI_PACKET_CONTROL … #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_INFOFRAME_CONTROL0 … #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG4_HDMI_INFOFRAME_CONTROL1 … #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_INTERRUPT_STATUS … #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG4_HDMI_GC … #define mmDIG4_HDMI_GC_BASE_IDX … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG4_AFMT_ISRC1_0 … #define mmDIG4_AFMT_ISRC1_0_BASE_IDX … #define mmDIG4_AFMT_ISRC1_1 … #define mmDIG4_AFMT_ISRC1_1_BASE_IDX … #define mmDIG4_AFMT_ISRC1_2 … #define mmDIG4_AFMT_ISRC1_2_BASE_IDX … #define mmDIG4_AFMT_ISRC1_3 … #define mmDIG4_AFMT_ISRC1_3_BASE_IDX … #define mmDIG4_AFMT_ISRC1_4 … #define mmDIG4_AFMT_ISRC1_4_BASE_IDX … #define mmDIG4_AFMT_ISRC2_0 … #define mmDIG4_AFMT_ISRC2_0_BASE_IDX … #define mmDIG4_AFMT_ISRC2_1 … #define mmDIG4_AFMT_ISRC2_1_BASE_IDX … #define mmDIG4_AFMT_ISRC2_2 … #define mmDIG4_AFMT_ISRC2_2_BASE_IDX … #define mmDIG4_AFMT_ISRC2_3 … #define mmDIG4_AFMT_ISRC2_3_BASE_IDX … #define mmDIG4_AFMT_AVI_INFO0 … #define mmDIG4_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG4_AFMT_AVI_INFO1 … #define mmDIG4_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG4_AFMT_AVI_INFO2 … #define mmDIG4_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG4_AFMT_AVI_INFO3 … #define mmDIG4_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG4_AFMT_MPEG_INFO0 … #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG4_AFMT_MPEG_INFO1 … #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG4_AFMT_GENERIC_HDR … #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG4_AFMT_GENERIC_0 … #define mmDIG4_AFMT_GENERIC_0_BASE_IDX … #define mmDIG4_AFMT_GENERIC_1 … #define mmDIG4_AFMT_GENERIC_1_BASE_IDX … #define mmDIG4_AFMT_GENERIC_2 … #define mmDIG4_AFMT_GENERIC_2_BASE_IDX … #define mmDIG4_AFMT_GENERIC_3 … #define mmDIG4_AFMT_GENERIC_3_BASE_IDX … #define mmDIG4_AFMT_GENERIC_4 … #define mmDIG4_AFMT_GENERIC_4_BASE_IDX … #define mmDIG4_AFMT_GENERIC_5 … #define mmDIG4_AFMT_GENERIC_5_BASE_IDX … #define mmDIG4_AFMT_GENERIC_6 … #define mmDIG4_AFMT_GENERIC_6_BASE_IDX … #define mmDIG4_AFMT_GENERIC_7 … #define mmDIG4_AFMT_GENERIC_7_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG4_HDMI_ACR_32_0 … #define mmDIG4_HDMI_ACR_32_0_BASE_IDX … #define mmDIG4_HDMI_ACR_32_1 … #define mmDIG4_HDMI_ACR_32_1_BASE_IDX … #define mmDIG4_HDMI_ACR_44_0 … #define mmDIG4_HDMI_ACR_44_0_BASE_IDX … #define mmDIG4_HDMI_ACR_44_1 … #define mmDIG4_HDMI_ACR_44_1_BASE_IDX … #define mmDIG4_HDMI_ACR_48_0 … #define mmDIG4_HDMI_ACR_48_0_BASE_IDX … #define mmDIG4_HDMI_ACR_48_1 … #define mmDIG4_HDMI_ACR_48_1_BASE_IDX … #define mmDIG4_HDMI_ACR_STATUS_0 … #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG4_HDMI_ACR_STATUS_1 … #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG4_AFMT_AUDIO_INFO0 … #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG4_AFMT_AUDIO_INFO1 … #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG4_AFMT_60958_0 … #define mmDIG4_AFMT_60958_0_BASE_IDX … #define mmDIG4_AFMT_60958_1 … #define mmDIG4_AFMT_60958_1_BASE_IDX … #define mmDIG4_AFMT_AUDIO_CRC_CONTROL … #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL0 … #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL1 … #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL2 … #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL3 … #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG4_AFMT_60958_2 … #define mmDIG4_AFMT_60958_2_BASE_IDX … #define mmDIG4_AFMT_AUDIO_CRC_RESULT … #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG4_AFMT_STATUS … #define mmDIG4_AFMT_STATUS_BASE_IDX … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG4_AFMT_VBI_PACKET_CONTROL … #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG4_AFMT_INFOFRAME_CONTROL0 … #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_AUDIO_SRC_CONTROL … #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG4_DIG_BE_CNTL … #define mmDIG4_DIG_BE_CNTL_BASE_IDX … #define mmDIG4_DIG_BE_EN_CNTL … #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG4_TMDS_CNTL … #define mmDIG4_TMDS_CNTL_BASE_IDX … #define mmDIG4_TMDS_CONTROL_CHAR … #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG4_TMDS_CONTROL0_FEEDBACK … #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG4_TMDS_CTL_BITS … #define mmDIG4_TMDS_CTL_BITS_BASE_IDX … #define mmDIG4_TMDS_DCBALANCER_CONTROL … #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG4_TMDS_CTL0_1_GEN_CNTL … #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG4_TMDS_CTL2_3_GEN_CNTL … #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG4_DIG_VERSION … #define mmDIG4_DIG_VERSION_BASE_IDX … #define mmDIG4_DIG_LANE_ENABLE … #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG4_AFMT_CNTL … #define mmDIG4_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp4_dispdec // base address: 0x1000 #define mmDP4_DP_LINK_CNTL … #define mmDP4_DP_LINK_CNTL_BASE_IDX … #define mmDP4_DP_PIXEL_FORMAT … #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP4_DP_MSA_COLORIMETRY … #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP4_DP_CONFIG … #define mmDP4_DP_CONFIG_BASE_IDX … #define mmDP4_DP_VID_STREAM_CNTL … #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP4_DP_STEER_FIFO … #define mmDP4_DP_STEER_FIFO_BASE_IDX … #define mmDP4_DP_MSA_MISC … #define mmDP4_DP_MSA_MISC_BASE_IDX … #define mmDP4_DP_VID_TIMING … #define mmDP4_DP_VID_TIMING_BASE_IDX … #define mmDP4_DP_VID_N … #define mmDP4_DP_VID_N_BASE_IDX … #define mmDP4_DP_VID_M … #define mmDP4_DP_VID_M_BASE_IDX … #define mmDP4_DP_LINK_FRAMING_CNTL … #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP4_DP_HBR2_EYE_PATTERN … #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP4_DP_VID_MSA_VBID … #define mmDP4_DP_VID_MSA_VBID_BASE_IDX … #define mmDP4_DP_VID_INTERRUPT_CNTL … #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CNTL … #define mmDP4_DP_DPHY_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP4_DP_DPHY_SYM0 … #define mmDP4_DP_DPHY_SYM0_BASE_IDX … #define mmDP4_DP_DPHY_SYM1 … #define mmDP4_DP_DPHY_SYM1_BASE_IDX … #define mmDP4_DP_DPHY_SYM2 … #define mmDP4_DP_DPHY_SYM2_BASE_IDX … #define mmDP4_DP_DPHY_8B10B_CNTL … #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_PRBS_CNTL … #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_SCRAM_CNTL … #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_EN … #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP4_DP_DPHY_CRC_CNTL … #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_RESULT … #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP4_DP_DPHY_CRC_MST_CNTL … #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_MST_STATUS … #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP4_DP_DPHY_FAST_TRAINING … #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP4_DP_SEC_CNTL … #define mmDP4_DP_SEC_CNTL_BASE_IDX … #define mmDP4_DP_SEC_CNTL1 … #define mmDP4_DP_SEC_CNTL1_BASE_IDX … #define mmDP4_DP_SEC_FRAMING1 … #define mmDP4_DP_SEC_FRAMING1_BASE_IDX … #define mmDP4_DP_SEC_FRAMING2 … #define mmDP4_DP_SEC_FRAMING2_BASE_IDX … #define mmDP4_DP_SEC_FRAMING3 … #define mmDP4_DP_SEC_FRAMING3_BASE_IDX … #define mmDP4_DP_SEC_FRAMING4 … #define mmDP4_DP_SEC_FRAMING4_BASE_IDX … #define mmDP4_DP_SEC_AUD_N … #define mmDP4_DP_SEC_AUD_N_BASE_IDX … #define mmDP4_DP_SEC_AUD_N_READBACK … #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP4_DP_SEC_AUD_M … #define mmDP4_DP_SEC_AUD_M_BASE_IDX … #define mmDP4_DP_SEC_AUD_M_READBACK … #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP4_DP_SEC_TIMESTAMP … #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP4_DP_SEC_PACKET_CNTL … #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP4_DP_MSE_RATE_CNTL … #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP4_DP_MSE_RATE_UPDATE … #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP4_DP_MSE_SAT0 … #define mmDP4_DP_MSE_SAT0_BASE_IDX … #define mmDP4_DP_MSE_SAT1 … #define mmDP4_DP_MSE_SAT1_BASE_IDX … #define mmDP4_DP_MSE_SAT2 … #define mmDP4_DP_MSE_SAT2_BASE_IDX … #define mmDP4_DP_MSE_SAT_UPDATE … #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP4_DP_MSE_LINK_TIMING … #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP4_DP_MSE_MISC_CNTL … #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP4_DP_MSE_SAT0_STATUS … #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP4_DP_MSE_SAT1_STATUS … #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP4_DP_MSE_SAT2_STATUS … #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig5_dispdec // base address: 0x1400 #define mmDIG5_DIG_FE_CNTL … #define mmDIG5_DIG_FE_CNTL_BASE_IDX … #define mmDIG5_DIG_OUTPUT_CRC_CNTL … #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG5_DIG_OUTPUT_CRC_RESULT … #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG5_DIG_CLOCK_PATTERN … #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG5_DIG_TEST_PATTERN … #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG5_DIG_RANDOM_PATTERN_SEED … #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG5_DIG_FIFO_STATUS … #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG5_HDMI_CONTROL … #define mmDIG5_HDMI_CONTROL_BASE_IDX … #define mmDIG5_HDMI_STATUS … #define mmDIG5_HDMI_STATUS_BASE_IDX … #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_ACR_PACKET_CONTROL … #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_VBI_PACKET_CONTROL … #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_INFOFRAME_CONTROL0 … #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG5_HDMI_INFOFRAME_CONTROL1 … #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_INTERRUPT_STATUS … #define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG5_HDMI_GC … #define mmDIG5_HDMI_GC_BASE_IDX … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG5_AFMT_ISRC1_0 … #define mmDIG5_AFMT_ISRC1_0_BASE_IDX … #define mmDIG5_AFMT_ISRC1_1 … #define mmDIG5_AFMT_ISRC1_1_BASE_IDX … #define mmDIG5_AFMT_ISRC1_2 … #define mmDIG5_AFMT_ISRC1_2_BASE_IDX … #define mmDIG5_AFMT_ISRC1_3 … #define mmDIG5_AFMT_ISRC1_3_BASE_IDX … #define mmDIG5_AFMT_ISRC1_4 … #define mmDIG5_AFMT_ISRC1_4_BASE_IDX … #define mmDIG5_AFMT_ISRC2_0 … #define mmDIG5_AFMT_ISRC2_0_BASE_IDX … #define mmDIG5_AFMT_ISRC2_1 … #define mmDIG5_AFMT_ISRC2_1_BASE_IDX … #define mmDIG5_AFMT_ISRC2_2 … #define mmDIG5_AFMT_ISRC2_2_BASE_IDX … #define mmDIG5_AFMT_ISRC2_3 … #define mmDIG5_AFMT_ISRC2_3_BASE_IDX … #define mmDIG5_AFMT_AVI_INFO0 … #define mmDIG5_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG5_AFMT_AVI_INFO1 … #define mmDIG5_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG5_AFMT_AVI_INFO2 … #define mmDIG5_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG5_AFMT_AVI_INFO3 … #define mmDIG5_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG5_AFMT_MPEG_INFO0 … #define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG5_AFMT_MPEG_INFO1 … #define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG5_AFMT_GENERIC_HDR … #define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG5_AFMT_GENERIC_0 … #define mmDIG5_AFMT_GENERIC_0_BASE_IDX … #define mmDIG5_AFMT_GENERIC_1 … #define mmDIG5_AFMT_GENERIC_1_BASE_IDX … #define mmDIG5_AFMT_GENERIC_2 … #define mmDIG5_AFMT_GENERIC_2_BASE_IDX … #define mmDIG5_AFMT_GENERIC_3 … #define mmDIG5_AFMT_GENERIC_3_BASE_IDX … #define mmDIG5_AFMT_GENERIC_4 … #define mmDIG5_AFMT_GENERIC_4_BASE_IDX … #define mmDIG5_AFMT_GENERIC_5 … #define mmDIG5_AFMT_GENERIC_5_BASE_IDX … #define mmDIG5_AFMT_GENERIC_6 … #define mmDIG5_AFMT_GENERIC_6_BASE_IDX … #define mmDIG5_AFMT_GENERIC_7 … #define mmDIG5_AFMT_GENERIC_7_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG5_HDMI_ACR_32_0 … #define mmDIG5_HDMI_ACR_32_0_BASE_IDX … #define mmDIG5_HDMI_ACR_32_1 … #define mmDIG5_HDMI_ACR_32_1_BASE_IDX … #define mmDIG5_HDMI_ACR_44_0 … #define mmDIG5_HDMI_ACR_44_0_BASE_IDX … #define mmDIG5_HDMI_ACR_44_1 … #define mmDIG5_HDMI_ACR_44_1_BASE_IDX … #define mmDIG5_HDMI_ACR_48_0 … #define mmDIG5_HDMI_ACR_48_0_BASE_IDX … #define mmDIG5_HDMI_ACR_48_1 … #define mmDIG5_HDMI_ACR_48_1_BASE_IDX … #define mmDIG5_HDMI_ACR_STATUS_0 … #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG5_HDMI_ACR_STATUS_1 … #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG5_AFMT_AUDIO_INFO0 … #define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG5_AFMT_AUDIO_INFO1 … #define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG5_AFMT_60958_0 … #define mmDIG5_AFMT_60958_0_BASE_IDX … #define mmDIG5_AFMT_60958_1 … #define mmDIG5_AFMT_60958_1_BASE_IDX … #define mmDIG5_AFMT_AUDIO_CRC_CONTROL … #define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL0 … #define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL1 … #define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL2 … #define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL3 … #define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG5_AFMT_60958_2 … #define mmDIG5_AFMT_60958_2_BASE_IDX … #define mmDIG5_AFMT_AUDIO_CRC_RESULT … #define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG5_AFMT_STATUS … #define mmDIG5_AFMT_STATUS_BASE_IDX … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG5_AFMT_VBI_PACKET_CONTROL … #define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG5_AFMT_INFOFRAME_CONTROL0 … #define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_AUDIO_SRC_CONTROL … #define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG5_DIG_BE_CNTL … #define mmDIG5_DIG_BE_CNTL_BASE_IDX … #define mmDIG5_DIG_BE_EN_CNTL … #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG5_TMDS_CNTL … #define mmDIG5_TMDS_CNTL_BASE_IDX … #define mmDIG5_TMDS_CONTROL_CHAR … #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG5_TMDS_CONTROL0_FEEDBACK … #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG5_TMDS_CTL_BITS … #define mmDIG5_TMDS_CTL_BITS_BASE_IDX … #define mmDIG5_TMDS_DCBALANCER_CONTROL … #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG5_TMDS_CTL0_1_GEN_CNTL … #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG5_TMDS_CTL2_3_GEN_CNTL … #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG5_DIG_VERSION … #define mmDIG5_DIG_VERSION_BASE_IDX … #define mmDIG5_DIG_LANE_ENABLE … #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG5_AFMT_CNTL … #define mmDIG5_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp5_dispdec // base address: 0x1400 #define mmDP5_DP_LINK_CNTL … #define mmDP5_DP_LINK_CNTL_BASE_IDX … #define mmDP5_DP_PIXEL_FORMAT … #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP5_DP_MSA_COLORIMETRY … #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP5_DP_CONFIG … #define mmDP5_DP_CONFIG_BASE_IDX … #define mmDP5_DP_VID_STREAM_CNTL … #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP5_DP_STEER_FIFO … #define mmDP5_DP_STEER_FIFO_BASE_IDX … #define mmDP5_DP_MSA_MISC … #define mmDP5_DP_MSA_MISC_BASE_IDX … #define mmDP5_DP_VID_TIMING … #define mmDP5_DP_VID_TIMING_BASE_IDX … #define mmDP5_DP_VID_N … #define mmDP5_DP_VID_N_BASE_IDX … #define mmDP5_DP_VID_M … #define mmDP5_DP_VID_M_BASE_IDX … #define mmDP5_DP_LINK_FRAMING_CNTL … #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP5_DP_HBR2_EYE_PATTERN … #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP5_DP_VID_MSA_VBID … #define mmDP5_DP_VID_MSA_VBID_BASE_IDX … #define mmDP5_DP_VID_INTERRUPT_CNTL … #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CNTL … #define mmDP5_DP_DPHY_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP5_DP_DPHY_SYM0 … #define mmDP5_DP_DPHY_SYM0_BASE_IDX … #define mmDP5_DP_DPHY_SYM1 … #define mmDP5_DP_DPHY_SYM1_BASE_IDX … #define mmDP5_DP_DPHY_SYM2 … #define mmDP5_DP_DPHY_SYM2_BASE_IDX … #define mmDP5_DP_DPHY_8B10B_CNTL … #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_PRBS_CNTL … #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_SCRAM_CNTL … #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_EN … #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP5_DP_DPHY_CRC_CNTL … #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_RESULT … #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP5_DP_DPHY_CRC_MST_CNTL … #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_MST_STATUS … #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP5_DP_DPHY_FAST_TRAINING … #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP5_DP_SEC_CNTL … #define mmDP5_DP_SEC_CNTL_BASE_IDX … #define mmDP5_DP_SEC_CNTL1 … #define mmDP5_DP_SEC_CNTL1_BASE_IDX … #define mmDP5_DP_SEC_FRAMING1 … #define mmDP5_DP_SEC_FRAMING1_BASE_IDX … #define mmDP5_DP_SEC_FRAMING2 … #define mmDP5_DP_SEC_FRAMING2_BASE_IDX … #define mmDP5_DP_SEC_FRAMING3 … #define mmDP5_DP_SEC_FRAMING3_BASE_IDX … #define mmDP5_DP_SEC_FRAMING4 … #define mmDP5_DP_SEC_FRAMING4_BASE_IDX … #define mmDP5_DP_SEC_AUD_N … #define mmDP5_DP_SEC_AUD_N_BASE_IDX … #define mmDP5_DP_SEC_AUD_N_READBACK … #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP5_DP_SEC_AUD_M … #define mmDP5_DP_SEC_AUD_M_BASE_IDX … #define mmDP5_DP_SEC_AUD_M_READBACK … #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP5_DP_SEC_TIMESTAMP … #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP5_DP_SEC_PACKET_CNTL … #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP5_DP_MSE_RATE_CNTL … #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP5_DP_MSE_RATE_UPDATE … #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP5_DP_MSE_SAT0 … #define mmDP5_DP_MSE_SAT0_BASE_IDX … #define mmDP5_DP_MSE_SAT1 … #define mmDP5_DP_MSE_SAT1_BASE_IDX … #define mmDP5_DP_MSE_SAT2 … #define mmDP5_DP_MSE_SAT2_BASE_IDX … #define mmDP5_DP_MSE_SAT_UPDATE … #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP5_DP_MSE_LINK_TIMING … #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP5_DP_MSE_MISC_CNTL … #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP5_DP_MSE_SAT0_STATUS … #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP5_DP_MSE_SAT1_STATUS … #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP5_DP_MSE_SAT2_STATUS … #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dig6_dispdec // base address: 0x1800 #define mmDIG6_DIG_FE_CNTL … #define mmDIG6_DIG_FE_CNTL_BASE_IDX … #define mmDIG6_DIG_OUTPUT_CRC_CNTL … #define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG6_DIG_OUTPUT_CRC_RESULT … #define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG6_DIG_CLOCK_PATTERN … #define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG6_DIG_TEST_PATTERN … #define mmDIG6_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG6_DIG_RANDOM_PATTERN_SEED … #define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG6_DIG_FIFO_STATUS … #define mmDIG6_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG6_HDMI_CONTROL … #define mmDIG6_HDMI_CONTROL_BASE_IDX … #define mmDIG6_HDMI_STATUS … #define mmDIG6_HDMI_STATUS_BASE_IDX … #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_ACR_PACKET_CONTROL … #define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_VBI_PACKET_CONTROL … #define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_INFOFRAME_CONTROL0 … #define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG6_HDMI_INFOFRAME_CONTROL1 … #define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_INTERRUPT_STATUS … #define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG6_HDMI_GC … #define mmDIG6_HDMI_GC_BASE_IDX … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG6_AFMT_ISRC1_0 … #define mmDIG6_AFMT_ISRC1_0_BASE_IDX … #define mmDIG6_AFMT_ISRC1_1 … #define mmDIG6_AFMT_ISRC1_1_BASE_IDX … #define mmDIG6_AFMT_ISRC1_2 … #define mmDIG6_AFMT_ISRC1_2_BASE_IDX … #define mmDIG6_AFMT_ISRC1_3 … #define mmDIG6_AFMT_ISRC1_3_BASE_IDX … #define mmDIG6_AFMT_ISRC1_4 … #define mmDIG6_AFMT_ISRC1_4_BASE_IDX … #define mmDIG6_AFMT_ISRC2_0 … #define mmDIG6_AFMT_ISRC2_0_BASE_IDX … #define mmDIG6_AFMT_ISRC2_1 … #define mmDIG6_AFMT_ISRC2_1_BASE_IDX … #define mmDIG6_AFMT_ISRC2_2 … #define mmDIG6_AFMT_ISRC2_2_BASE_IDX … #define mmDIG6_AFMT_ISRC2_3 … #define mmDIG6_AFMT_ISRC2_3_BASE_IDX … #define mmDIG6_AFMT_AVI_INFO0 … #define mmDIG6_AFMT_AVI_INFO0_BASE_IDX … #define mmDIG6_AFMT_AVI_INFO1 … #define mmDIG6_AFMT_AVI_INFO1_BASE_IDX … #define mmDIG6_AFMT_AVI_INFO2 … #define mmDIG6_AFMT_AVI_INFO2_BASE_IDX … #define mmDIG6_AFMT_AVI_INFO3 … #define mmDIG6_AFMT_AVI_INFO3_BASE_IDX … #define mmDIG6_AFMT_MPEG_INFO0 … #define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG6_AFMT_MPEG_INFO1 … #define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG6_AFMT_GENERIC_HDR … #define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG6_AFMT_GENERIC_0 … #define mmDIG6_AFMT_GENERIC_0_BASE_IDX … #define mmDIG6_AFMT_GENERIC_1 … #define mmDIG6_AFMT_GENERIC_1_BASE_IDX … #define mmDIG6_AFMT_GENERIC_2 … #define mmDIG6_AFMT_GENERIC_2_BASE_IDX … #define mmDIG6_AFMT_GENERIC_3 … #define mmDIG6_AFMT_GENERIC_3_BASE_IDX … #define mmDIG6_AFMT_GENERIC_4 … #define mmDIG6_AFMT_GENERIC_4_BASE_IDX … #define mmDIG6_AFMT_GENERIC_5 … #define mmDIG6_AFMT_GENERIC_5_BASE_IDX … #define mmDIG6_AFMT_GENERIC_6 … #define mmDIG6_AFMT_GENERIC_6_BASE_IDX … #define mmDIG6_AFMT_GENERIC_7 … #define mmDIG6_AFMT_GENERIC_7_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG6_HDMI_ACR_32_0 … #define mmDIG6_HDMI_ACR_32_0_BASE_IDX … #define mmDIG6_HDMI_ACR_32_1 … #define mmDIG6_HDMI_ACR_32_1_BASE_IDX … #define mmDIG6_HDMI_ACR_44_0 … #define mmDIG6_HDMI_ACR_44_0_BASE_IDX … #define mmDIG6_HDMI_ACR_44_1 … #define mmDIG6_HDMI_ACR_44_1_BASE_IDX … #define mmDIG6_HDMI_ACR_48_0 … #define mmDIG6_HDMI_ACR_48_0_BASE_IDX … #define mmDIG6_HDMI_ACR_48_1 … #define mmDIG6_HDMI_ACR_48_1_BASE_IDX … #define mmDIG6_HDMI_ACR_STATUS_0 … #define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG6_HDMI_ACR_STATUS_1 … #define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG6_AFMT_AUDIO_INFO0 … #define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG6_AFMT_AUDIO_INFO1 … #define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG6_AFMT_60958_0 … #define mmDIG6_AFMT_60958_0_BASE_IDX … #define mmDIG6_AFMT_60958_1 … #define mmDIG6_AFMT_60958_1_BASE_IDX … #define mmDIG6_AFMT_AUDIO_CRC_CONTROL … #define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL0 … #define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL1 … #define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL2 … #define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL3 … #define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG6_AFMT_60958_2 … #define mmDIG6_AFMT_60958_2_BASE_IDX … #define mmDIG6_AFMT_AUDIO_CRC_RESULT … #define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG6_AFMT_STATUS … #define mmDIG6_AFMT_STATUS_BASE_IDX … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG6_AFMT_VBI_PACKET_CONTROL … #define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG6_AFMT_INFOFRAME_CONTROL0 … #define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_AUDIO_SRC_CONTROL … #define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG6_DIG_BE_CNTL … #define mmDIG6_DIG_BE_CNTL_BASE_IDX … #define mmDIG6_DIG_BE_EN_CNTL … #define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG6_TMDS_CNTL … #define mmDIG6_TMDS_CNTL_BASE_IDX … #define mmDIG6_TMDS_CONTROL_CHAR … #define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG6_TMDS_CONTROL0_FEEDBACK … #define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG6_TMDS_CTL_BITS … #define mmDIG6_TMDS_CTL_BITS_BASE_IDX … #define mmDIG6_TMDS_DCBALANCER_CONTROL … #define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG6_TMDS_CTL0_1_GEN_CNTL … #define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG6_TMDS_CTL2_3_GEN_CNTL … #define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG6_DIG_VERSION … #define mmDIG6_DIG_VERSION_BASE_IDX … #define mmDIG6_DIG_LANE_ENABLE … #define mmDIG6_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG6_AFMT_CNTL … #define mmDIG6_AFMT_CNTL_BASE_IDX … // addressBlock: dce_dc_dp6_dispdec // base address: 0x1800 #define mmDP6_DP_LINK_CNTL … #define mmDP6_DP_LINK_CNTL_BASE_IDX … #define mmDP6_DP_PIXEL_FORMAT … #define mmDP6_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP6_DP_MSA_COLORIMETRY … #define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP6_DP_CONFIG … #define mmDP6_DP_CONFIG_BASE_IDX … #define mmDP6_DP_VID_STREAM_CNTL … #define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP6_DP_STEER_FIFO … #define mmDP6_DP_STEER_FIFO_BASE_IDX … #define mmDP6_DP_MSA_MISC … #define mmDP6_DP_MSA_MISC_BASE_IDX … #define mmDP6_DP_VID_TIMING … #define mmDP6_DP_VID_TIMING_BASE_IDX … #define mmDP6_DP_VID_N … #define mmDP6_DP_VID_N_BASE_IDX … #define mmDP6_DP_VID_M … #define mmDP6_DP_VID_M_BASE_IDX … #define mmDP6_DP_LINK_FRAMING_CNTL … #define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP6_DP_HBR2_EYE_PATTERN … #define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP6_DP_VID_MSA_VBID … #define mmDP6_DP_VID_MSA_VBID_BASE_IDX … #define mmDP6_DP_VID_INTERRUPT_CNTL … #define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CNTL … #define mmDP6_DP_DPHY_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP6_DP_DPHY_SYM0 … #define mmDP6_DP_DPHY_SYM0_BASE_IDX … #define mmDP6_DP_DPHY_SYM1 … #define mmDP6_DP_DPHY_SYM1_BASE_IDX … #define mmDP6_DP_DPHY_SYM2 … #define mmDP6_DP_DPHY_SYM2_BASE_IDX … #define mmDP6_DP_DPHY_8B10B_CNTL … #define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_PRBS_CNTL … #define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_SCRAM_CNTL … #define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_EN … #define mmDP6_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP6_DP_DPHY_CRC_CNTL … #define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_RESULT … #define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP6_DP_DPHY_CRC_MST_CNTL … #define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_MST_STATUS … #define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP6_DP_DPHY_FAST_TRAINING … #define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 … #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX … #define mmDP6_DP_SEC_CNTL … #define mmDP6_DP_SEC_CNTL_BASE_IDX … #define mmDP6_DP_SEC_CNTL1 … #define mmDP6_DP_SEC_CNTL1_BASE_IDX … #define mmDP6_DP_SEC_FRAMING1 … #define mmDP6_DP_SEC_FRAMING1_BASE_IDX … #define mmDP6_DP_SEC_FRAMING2 … #define mmDP6_DP_SEC_FRAMING2_BASE_IDX … #define mmDP6_DP_SEC_FRAMING3 … #define mmDP6_DP_SEC_FRAMING3_BASE_IDX … #define mmDP6_DP_SEC_FRAMING4 … #define mmDP6_DP_SEC_FRAMING4_BASE_IDX … #define mmDP6_DP_SEC_AUD_N … #define mmDP6_DP_SEC_AUD_N_BASE_IDX … #define mmDP6_DP_SEC_AUD_N_READBACK … #define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP6_DP_SEC_AUD_M … #define mmDP6_DP_SEC_AUD_M_BASE_IDX … #define mmDP6_DP_SEC_AUD_M_READBACK … #define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP6_DP_SEC_TIMESTAMP … #define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP6_DP_SEC_PACKET_CNTL … #define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP6_DP_MSE_RATE_CNTL … #define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP6_DP_MSE_RATE_UPDATE … #define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP6_DP_MSE_SAT0 … #define mmDP6_DP_MSE_SAT0_BASE_IDX … #define mmDP6_DP_MSE_SAT1 … #define mmDP6_DP_MSE_SAT1_BASE_IDX … #define mmDP6_DP_MSE_SAT2 … #define mmDP6_DP_MSE_SAT2_BASE_IDX … #define mmDP6_DP_MSE_SAT_UPDATE … #define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP6_DP_MSE_LINK_TIMING … #define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP6_DP_MSE_MISC_CNTL … #define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP6_DP_MSE_SAT0_STATUS … #define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP6_DP_MSE_SAT1_STATUS … #define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP6_DP_MSE_SAT2_STATUS … #define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy0_dispdec // base address: 0x0 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_VREG_CFG … #define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_DFT_OUT … #define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy1_dispdec // base address: 0x320 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs1_dispdec // base address: 0x320 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs1_dispdec // base address: 0x320 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs1_dispdec // base address: 0x320 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_VREG_CFG … #define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_DFT_OUT … #define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy2_dispdec // base address: 0x640 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs2_dispdec // base address: 0x640 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs2_dispdec // base address: 0x640 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs2_dispdec // base address: 0x640 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_VREG_CFG … #define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_DFT_OUT … #define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy3_dispdec // base address: 0x960 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs3_dispdec // base address: 0x960 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs3_dispdec // base address: 0x960 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs3_dispdec // base address: 0x960 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_VREG_CFG … #define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_DFT_OUT … #define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy4_dispdec // base address: 0xc80 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs4_dispdec // base address: 0xc80 #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs4_dispdec // base address: 0xc80 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs4_dispdec // base address: 0xc80 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_VREG_CFG … #define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS4_DFT_OUT … #define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy5_dispdec // base address: 0xfa0 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs5_dispdec // base address: 0xfa0 #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs5_dispdec // base address: 0xfa0 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs5_dispdec // base address: 0xfa0 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_VREG_CFG … #define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS5_DFT_OUT … #define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy6_dispdec // base address: 0x12c0 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs6_dispdec // base address: 0x12c0 #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs6_dispdec // base address: 0x12c0 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs6_dispdec // base address: 0x12c0 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_VREG_CFG … #define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS6_DFT_OUT … #define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dcio_uniphy8_dispdec // base address: 0x15e0 #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_dc_combophycmregs8_dispdec // base address: 0x15e0 #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_dc_combophytxregs8_dispdec // base address: 0x15e0 #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_dc_combophypllregs8_dispdec // base address: 0x15e0 #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_VREG_CFG … #define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS8_DFT_OUT … #define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX … // addressBlock: dce_dc_dsi0_dispdec // base address: 0x0 #define mmDSI0_DISP_DSI_CTRL … #define mmDSI0_DISP_DSI_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_STATUS … #define mmDSI0_DISP_DSI_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL … #define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE … #define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD … #define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD … #define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE … #define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE … #define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX … #define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL … #define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL … #define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL … #define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL … #define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_CMD_OFFSET … #define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_CMD_LENGTH … #define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 … #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 … #define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_DATA_PITCH … #define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_DATA_WIDTH … #define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT … #define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_FIFO_CTRL … #define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA … #define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX … #define mmDSI0_DISP_DSI_DENG_DATA_LENGTH … #define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX … #define mmDSI0_DISP_DSI_ACK_ERROR_REPORT … #define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATA0 … #define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATA1 … #define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATA2 … #define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATA3 … #define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATATYPE0 … #define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_DATATYPE1 … #define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX … #define mmDSI0_DISP_DSI_TRIG_CTRL … #define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_EXT_MUX … #define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX … #define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL … #define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER … #define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER … #define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER … #define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX … #define mmDSI0_DISP_DSI_RESET_SW_TRIGGER … #define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX … #define mmDSI0_DISP_DSI_EXT_RESET … #define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX … #define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE … #define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX … #define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE … #define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX … #define mmDSI0_DISP_DSI_LANE_CRC_CTRL … #define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL … #define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_LANE_CTRL … #define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_DLN0_PHY_ERROR … #define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX … #define mmDSI0_DISP_DSI_LP_TIMER_CTRL … #define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_HS_TIMER_CTRL … #define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_TIMEOUT_STATUS … #define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL … #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 … #define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX … #define mmDSI0_DISP_DSI_EOT_PACKET … #define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX … #define mmDSI0_DISP_DSI_EOT_PACKET_CTRL … #define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER … #define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_CTRL … #define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE … #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE … #define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG … #define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL … #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT … #define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_START … #define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX … #define mmDSI0_DISP_DSI_MIPI_BIST_STATUS … #define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK … #define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX … #define mmDSI0_DISP_DSI_INTERRUPT_CTRL … #define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_CLK_CTRL … #define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_CLK_STATUS … #define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_DENG_FIFO_STATUS … #define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_DENG_FIFO_CTRL … #define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_FIFO_DATA … #define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_FIFO_CTRL … #define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_TE_CTRL … #define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_LANE_STATUS … #define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX … #define mmDSI0_DISP_DSI_PERF_CTRL … #define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX … #define mmDSI0_DISP_DSI_HSYNC_LENGTH … #define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX … #define mmDSI0_DISP_DSI_RDBK_NUM … #define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX … #define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL … #define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dsi1_dispdec // base address: 0x400 #define mmDSI1_DISP_DSI_CTRL … #define mmDSI1_DISP_DSI_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_STATUS … #define mmDSI1_DISP_DSI_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL … #define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE … #define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD … #define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD … #define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE … #define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE … #define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX … #define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL … #define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL … #define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL … #define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL … #define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_CMD_OFFSET … #define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_CMD_LENGTH … #define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 … #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 … #define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_DATA_PITCH … #define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_DATA_WIDTH … #define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT … #define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_FIFO_CTRL … #define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA … #define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX … #define mmDSI1_DISP_DSI_DENG_DATA_LENGTH … #define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX … #define mmDSI1_DISP_DSI_ACK_ERROR_REPORT … #define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATA0 … #define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATA1 … #define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATA2 … #define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATA3 … #define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATATYPE0 … #define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_DATATYPE1 … #define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX … #define mmDSI1_DISP_DSI_TRIG_CTRL … #define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_EXT_MUX … #define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX … #define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL … #define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER … #define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER … #define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER … #define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX … #define mmDSI1_DISP_DSI_RESET_SW_TRIGGER … #define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX … #define mmDSI1_DISP_DSI_EXT_RESET … #define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX … #define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE … #define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX … #define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE … #define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX … #define mmDSI1_DISP_DSI_LANE_CRC_CTRL … #define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL … #define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_LANE_CTRL … #define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_DLN0_PHY_ERROR … #define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX … #define mmDSI1_DISP_DSI_LP_TIMER_CTRL … #define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_HS_TIMER_CTRL … #define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_TIMEOUT_STATUS … #define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL … #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 … #define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX … #define mmDSI1_DISP_DSI_EOT_PACKET … #define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX … #define mmDSI1_DISP_DSI_EOT_PACKET_CTRL … #define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER … #define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_CTRL … #define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE … #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE … #define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG … #define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL … #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT … #define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_START … #define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX … #define mmDSI1_DISP_DSI_MIPI_BIST_STATUS … #define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK … #define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX … #define mmDSI1_DISP_DSI_INTERRUPT_CTRL … #define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_CLK_CTRL … #define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_CLK_STATUS … #define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_DENG_FIFO_STATUS … #define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_DENG_FIFO_CTRL … #define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_FIFO_DATA … #define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_FIFO_CTRL … #define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_TE_CTRL … #define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_LANE_STATUS … #define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX … #define mmDSI1_DISP_DSI_PERF_CTRL … #define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX … #define mmDSI1_DISP_DSI_HSYNC_LENGTH … #define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX … #define mmDSI1_DISP_DSI_RDBK_NUM … #define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX … #define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL … #define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dprx_sd0_dispdec // base address: 0x0 #define mmDPRX_SD0_DPRX_SD_CONTROL … #define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE … #define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA0 … #define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA1 … #define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA2 … #define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA3 … #define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA4 … #define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA5 … #define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA6 … #define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA7 … #define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA8 … #define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_VBID … #define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_CURRENT_LINE … #define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT … #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE … #define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSE_SAT … #define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE … #define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE … #define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_V_PARAMETER … #define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT … #define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS … #define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED … #define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL … #define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR … #define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE … #define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR … #define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED … #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR … #define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR … #define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR … #define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH … #define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_STEER … #define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS … #define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_LEVEL … #define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_DATA … #define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_ERROR … #define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER … #define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR … #define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_SDP_CONTROL … #define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED … #define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED … #define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_BS_COUNTER … #define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX … #define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED … #define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX … // addressBlock: dce_dc_dprx_sd1_dispdec // base address: 0x180 #define mmDPRX_SD1_DPRX_SD_CONTROL … #define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE … #define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA0 … #define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA1 … #define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA2 … #define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA3 … #define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA4 … #define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA5 … #define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA6 … #define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA7 … #define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA8 … #define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_VBID … #define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_CURRENT_LINE … #define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT … #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE … #define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSE_SAT … #define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE … #define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE … #define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_V_PARAMETER … #define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT … #define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS … #define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED … #define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL … #define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR … #define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE … #define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR … #define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED … #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR … #define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR … #define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR … #define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH … #define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_STEER … #define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS … #define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_LEVEL … #define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_DATA … #define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_ERROR … #define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER … #define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR … #define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_SDP_CONTROL … #define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED … #define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED … #define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_BS_COUNTER … #define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX … #define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED … #define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX … // addressBlock: dce_dc_dc_perfmon10_dispdec // base address: 0xacf8 #define mmDC_PERFMON10_PERFCOUNTER_CNTL … #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON10_PERFCOUNTER_STATE … #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CNTL … #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CNTL2 … #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CVALUE_LOW … #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON10_PERFMON_HI … #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON10_PERFMON_LOW … #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dc_zcalregs_dispdec // base address: 0x0 #define mmCOMP_EN_CTL … #define mmCOMP_EN_CTL_BASE_IDX … #define mmCOMP_EN_DFX … #define mmCOMP_EN_DFX_BASE_IDX … #define mmZCAL_FUSES … #define mmZCAL_FUSES_BASE_IDX … // addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR // base address: 0x48 //#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012 // addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR // base address: 0x4c //#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014 // addressBlock: dce_dc_dispdec[948..986] // base address: 0x3b4 //#define mmVGA_CRTC8_IDX 0x002d //#define mmVGA_CRTC8_DATA 0x002d //#define mmVGA_GENFC_WT 0x002e //#define mmVGA_GENS1 0x002e //#define mmVGA_ATTRDW 0x0030 //#define mmVGA_ATTRX 0x0030 //#define mmVGA_ATTRDR 0x0030 //#define mmVGA_GENMO_WT 0x0030 //#define mmVGA_GENS0 0x0030 //#define mmVGA_GENENB 0x0030 //#define mmVGA_SEQ8_IDX 0x0031 //#define mmVGA_SEQ8_DATA 0x0031 //#define mmVGA_DAC_MASK 0x0031 //#define mmVGA_DAC_R_INDEX 0x0031 //#define mmVGA_DAC_W_INDEX 0x0032 //#define mmVGA_DAC_DATA 0x0032 //#define mmVGA_GENFC_RD 0x0032 //#define mmVGA_GENMO_RD 0x0033 //#define mmVGA_GRPH8_IDX 0x0033 //#define mmVGA_GRPH8_DATA 0x0033 //#define mmVGA_CRTC8_IDX_1 0x0035 //#define mmVGA_CRTC8_DATA_1 0x0035 //#define mmVGA_GENFC_WT_1 0x0036 //#define mmVGA_GENS1_1 0x0036 // addressBlock: dce_dc_azdec // base address: 0x0 #define mmCORB_WRITE_POINTER … #define mmCORB_WRITE_POINTER_BASE_IDX … #define mmCORB_READ_POINTER … #define mmCORB_READ_POINTER_BASE_IDX … #define mmCORB_CONTROL … #define mmCORB_CONTROL_BASE_IDX … #define mmCORB_STATUS … #define mmCORB_STATUS_BASE_IDX … #define mmCORB_SIZE … #define mmCORB_SIZE_BASE_IDX … #define mmRIRB_LOWER_BASE_ADDRESS … #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX … #define mmRIRB_UPPER_BASE_ADDRESS … #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX … #define mmRIRB_WRITE_POINTER … #define mmRIRB_WRITE_POINTER_BASE_IDX … #define mmRESPONSE_INTERRUPT_COUNT … #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX … #define mmRIRB_CONTROL … #define mmRIRB_CONTROL_BASE_IDX … #define mmRIRB_STATUS … #define mmRIRB_STATUS_BASE_IDX … #define mmRIRB_SIZE … #define mmRIRB_SIZE_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE … #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX … #define mmIMMEDIATE_COMMAND_STATUS … #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX … #define mmDMA_POSITION_LOWER_BASE_ADDRESS … #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX … #define mmDMA_POSITION_UPPER_BASE_ADDRESS … #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX … #define mmWALL_CLOCK_COUNTER_ALIAS … #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream0_azdec // base address: 0x0 #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream1_azdec // base address: 0x20 #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream2_azdec // base address: 0x40 #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream3_azdec // base address: 0x60 #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream4_azdec // base address: 0x80 #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream5_azdec // base address: 0xa0 #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream6_azdec // base address: 0xc0 #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_azstream7_azdec // base address: 0xe0 #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: azf0stream0_streamind // base address: 0x0 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream1_streamind // base address: 0x0 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream2_streamind // base address: 0x0 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream3_streamind // base address: 0x0 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream4_streamind // base address: 0x0 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream5_streamind // base address: 0x0 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream6_streamind // base address: 0x0 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream7_streamind // base address: 0x0 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream8_streamind // base address: 0x0 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream9_streamind // base address: 0x0 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream10_streamind // base address: 0x0 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream11_streamind // base address: 0x0 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream12_streamind // base address: 0x0 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream13_streamind // base address: 0x0 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream14_streamind // base address: 0x0 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream15_streamind // base address: 0x0 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0endpoint0_endpointind // base address: 0x0 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint1_endpointind // base address: 0x0 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint2_endpointind // base address: 0x0 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint3_endpointind // base address: 0x0 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint4_endpointind // base address: 0x0 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint5_endpointind // base address: 0x0 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint6_endpointind // base address: 0x0 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint7_endpointind // base address: 0x0 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0inputendpoint0_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint1_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint2_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint3_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint4_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint5_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint6_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint7_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 … #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC … #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … // addressBlock: descriptorind // base address: 0x0 #define ixAUDIO_DESCRIPTOR0 … #define ixAUDIO_DESCRIPTOR1 … #define ixAUDIO_DESCRIPTOR2 … #define ixAUDIO_DESCRIPTOR3 … #define ixAUDIO_DESCRIPTOR4 … #define ixAUDIO_DESCRIPTOR5 … #define ixAUDIO_DESCRIPTOR6 … #define ixAUDIO_DESCRIPTOR7 … #define ixAUDIO_DESCRIPTOR8 … #define ixAUDIO_DESCRIPTOR9 … #define ixAUDIO_DESCRIPTOR10 … #define ixAUDIO_DESCRIPTOR11 … #define ixAUDIO_DESCRIPTOR12 … #define ixAUDIO_DESCRIPTOR13 … // addressBlock: sinkinfoind // base address: 0x0 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 … #define ixSINK_DESCRIPTION0 … #define ixSINK_DESCRIPTION1 … #define ixSINK_DESCRIPTION2 … #define ixSINK_DESCRIPTION3 … #define ixSINK_DESCRIPTION4 … #define ixSINK_DESCRIPTION5 … #define ixSINK_DESCRIPTION6 … #define ixSINK_DESCRIPTION7 … #define ixSINK_DESCRIPTION8 … #define ixSINK_DESCRIPTION9 … #define ixSINK_DESCRIPTION10 … #define ixSINK_DESCRIPTION11 … #define ixSINK_DESCRIPTION12 … #define ixSINK_DESCRIPTION13 … #define ixSINK_DESCRIPTION14 … #define ixSINK_DESCRIPTION15 … #define ixSINK_DESCRIPTION16 … #define ixSINK_DESCRIPTION17 … // addressBlock: azinputcrc0resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC0_CHANNEL0 … #define ixAZALIA_INPUT_CRC0_CHANNEL1 … #define ixAZALIA_INPUT_CRC0_CHANNEL2 … #define ixAZALIA_INPUT_CRC0_CHANNEL3 … #define ixAZALIA_INPUT_CRC0_CHANNEL4 … #define ixAZALIA_INPUT_CRC0_CHANNEL5 … #define ixAZALIA_INPUT_CRC0_CHANNEL6 … #define ixAZALIA_INPUT_CRC0_CHANNEL7 … // addressBlock: azinputcrc1resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … #define ixAZALIA_INPUT_CRC1_CHANNEL1 … #define ixAZALIA_INPUT_CRC1_CHANNEL2 … #define ixAZALIA_INPUT_CRC1_CHANNEL3 … #define ixAZALIA_INPUT_CRC1_CHANNEL4 … #define ixAZALIA_INPUT_CRC1_CHANNEL5 … #define ixAZALIA_INPUT_CRC1_CHANNEL6 … #define ixAZALIA_INPUT_CRC1_CHANNEL7 … // addressBlock: azcrc0resultind // base address: 0x0 #define ixAZALIA_CRC0_CHANNEL0 … #define ixAZALIA_CRC0_CHANNEL1 … #define ixAZALIA_CRC0_CHANNEL2 … #define ixAZALIA_CRC0_CHANNEL3 … #define ixAZALIA_CRC0_CHANNEL4 … #define ixAZALIA_CRC0_CHANNEL5 … #define ixAZALIA_CRC0_CHANNEL6 … #define ixAZALIA_CRC0_CHANNEL7 … // addressBlock: azcrc1resultind // base address: 0x0 #define ixAZALIA_CRC1_CHANNEL0 … #define ixAZALIA_CRC1_CHANNEL1 … #define ixAZALIA_CRC1_CHANNEL2 … #define ixAZALIA_CRC1_CHANNEL3 … #define ixAZALIA_CRC1_CHANNEL4 … #define ixAZALIA_CRC1_CHANNEL5 … #define ixAZALIA_CRC1_CHANNEL6 … #define ixAZALIA_CRC1_CHANNEL7 … // addressBlock: vgaseqind // base address: 0x0 #define ixSEQ00 … #define ixSEQ01 … #define ixSEQ02 … #define ixSEQ03 … #define ixSEQ04 … // addressBlock: vgacrtind // base address: 0x0 #define ixCRT00 … #define ixCRT01 … #define ixCRT02 … #define ixCRT03 … #define ixCRT04 … #define ixCRT05 … #define ixCRT06 … #define ixCRT07 … #define ixCRT08 … #define ixCRT09 … #define ixCRT0A … #define ixCRT0B … #define ixCRT0C … #define ixCRT0D … #define ixCRT0E … #define ixCRT0F … #define ixCRT10 … #define ixCRT11 … #define ixCRT12 … #define ixCRT13 … #define ixCRT14 … #define ixCRT15 … #define ixCRT16 … #define ixCRT17 … #define ixCRT18 … #define ixCRT1E … #define ixCRT1F … #define ixCRT22 … // addressBlock: vgagrphind // base address: 0x0 #define ixGRA00 … #define ixGRA01 … #define ixGRA02 … #define ixGRA03 … #define ixGRA04 … #define ixGRA05 … #define ixGRA06 … #define ixGRA07 … #define ixGRA08 … // addressBlock: vgaattrind // base address: 0x0 #define ixATTR00 … #define ixATTR01 … #define ixATTR02 … #define ixATTR03 … #define ixATTR04 … #define ixATTR05 … #define ixATTR06 … #define ixATTR07 … #define ixATTR08 … #define ixATTR09 … #define ixATTR0A … #define ixATTR0B … #define ixATTR0C … #define ixATTR0D … #define ixATTR0E … #define ixATTR0F … #define ixATTR10 … #define ixATTR11 … #define ixATTR12 … #define ixATTR13 … #define ixATTR14 … #endif
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