/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/pci.h> #include <linux/slab.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_ih.h" #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "amdgpu_ucode.h" #include "atom.h" #include "amd_pcie.h" #include "gmc/gmc_8_1_d.h" #include "gmc/gmc_8_1_sh_mask.h" #include "oss/oss_3_0_d.h" #include "oss/oss_3_0_sh_mask.h" #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" #include "gca/gfx_8_0_d.h" #include "gca/gfx_8_0_sh_mask.h" #include "smu/smu_7_1_1_d.h" #include "smu/smu_7_1_1_sh_mask.h" #include "uvd/uvd_5_0_d.h" #include "uvd/uvd_5_0_sh_mask.h" #include "vce/vce_3_0_d.h" #include "vce/vce_3_0_sh_mask.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "vid.h" #include "vi.h" #include "gmc_v8_0.h" #include "gmc_v7_0.h" #include "gfx_v8_0.h" #include "sdma_v2_4.h" #include "sdma_v3_0.h" #include "dce_v10_0.h" #include "dce_v11_0.h" #include "iceland_ih.h" #include "tonga_ih.h" #include "cz_ih.h" #include "uvd_v5_0.h" #include "uvd_v6_0.h" #include "vce_v3_0.h" #if defined(CONFIG_DRM_AMD_ACP) #include "amdgpu_acp.h" #endif #include "amdgpu_vkms.h" #include "mxgpu_vi.h" #include "amdgpu_dm.h" #define ixPCIE_LC_L1_PM_SUBSTATE … #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK … #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK … #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK … #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK … #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK … #define ixPCIE_L1_PM_SUB_CNTL … #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK … #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK … #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK … #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK … #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK … #define LINK_CAP … #define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK … #define ixCPM_CONTROL … #define ixPCIE_LC_CNTL7 … #define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK … #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT … #define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT … #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK … #define PCIE_L1_PM_SUB_CNTL … #define ASIC_IS_P22(asic_type, rid) … /* Topaz */ static const struct amdgpu_video_codecs topaz_video_codecs_encode = …; /* Tonga, CZ, ST, Fiji */ static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] = …; static const struct amdgpu_video_codecs tonga_video_codecs_encode = …; /* Polaris */ static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] = …; static const struct amdgpu_video_codecs polaris_video_codecs_encode = …; /* Topaz */ static const struct amdgpu_video_codecs topaz_video_codecs_decode = …; /* Tonga */ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] = …; static const struct amdgpu_video_codecs tonga_video_codecs_decode = …; /* CZ, ST, Fiji, Polaris */ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] = …; static const struct amdgpu_video_codecs cz_video_codecs_decode = …; static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, const struct amdgpu_video_codecs **codecs) { … } /* * Indirect registers accessor */ static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) { … } static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) { … } static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } /* smu_8_0_d.h */ #define mmMP0PUB_IND_INDEX … #define mmMP0PUB_IND_DATA … static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) { … } static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) { … } static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) { … } static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) { … } static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { … } static const u32 tonga_mgcg_cgcg_init[] = …; static const u32 fiji_mgcg_cgcg_init[] = …; static const u32 iceland_mgcg_cgcg_init[] = …; static const u32 cz_mgcg_cgcg_init[] = …; static const u32 stoney_mgcg_cgcg_init[] = …; static void vi_init_golden_registers(struct amdgpu_device *adev) { … } /** * vi_get_xclk - get the xclk * * @adev: amdgpu_device pointer * * Returns the reference clock used by the gfx engine * (VI). */ static u32 vi_get_xclk(struct amdgpu_device *adev) { … } /** * vi_srbm_select - select specific register instances * * @adev: amdgpu_device pointer * @me: selected ME (micro engine) * @pipe: pipe * @queue: queue * @vmid: VMID * * Switches the currently active registers instances. Some * registers are instanced per VMID, others are instanced per * me/pipe/queue combination. */ void vi_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid) { … } static bool vi_read_disabled_bios(struct amdgpu_device *adev) { … } static bool vi_read_bios_from_rom(struct amdgpu_device *adev, u8 *bios, u32 length_bytes) { … } static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = …; static uint32_t vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) { … } static int vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) { … } /** * vi_asic_pci_config_reset - soft reset GPU * * @adev: amdgpu_device pointer * * Use PCI Config method to reset the GPU. * * Returns 0 for success. */ static int vi_asic_pci_config_reset(struct amdgpu_device *adev) { … } static int vi_asic_supports_baco(struct amdgpu_device *adev) { … } static enum amd_reset_method vi_asic_reset_method(struct amdgpu_device *adev) { … } /** * vi_asic_reset - soft reset GPU * * @adev: amdgpu_device pointer * * Look up which blocks are hung and attempt * to reset them. * Returns 0 for success. */ static int vi_asic_reset(struct amdgpu_device *adev) { … } static u32 vi_get_config_memsize(struct amdgpu_device *adev) { … } static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, u32 cntl_reg, u32 status_reg) { … } #define ixGNB_CLK1_DFS_CNTL … #define ixGNB_CLK1_STATUS … #define ixGNB_CLK2_DFS_CNTL … #define ixGNB_CLK2_STATUS … #define ixGNB_CLK3_DFS_CNTL … #define ixGNB_CLK3_STATUS … static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) { … } static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) { … } static void vi_enable_aspm(struct amdgpu_device *adev) { … } static void vi_program_aspm(struct amdgpu_device *adev) { … } static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { … } #define ATI_REV_ID_FUSE_MACRO__ADDRESS … #define ATI_REV_ID_FUSE_MACRO__SHIFT … #define ATI_REV_ID_FUSE_MACRO__MASK … static uint32_t vi_get_rev_id(struct amdgpu_device *adev) { … } static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { … } static void vi_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { … } static bool vi_need_full_reset(struct amdgpu_device *adev) { … } static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, uint64_t *count1) { … } static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) { … } static bool vi_need_reset_on_init(struct amdgpu_device *adev) { … } static void vi_pre_asic_init(struct amdgpu_device *adev) { … } static const struct amdgpu_asic_funcs vi_asic_funcs = …; #define CZ_REV_BRISTOL(rev) … static int vi_common_early_init(void *handle) { … } static int vi_common_late_init(void *handle) { … } static int vi_common_sw_init(void *handle) { … } static int vi_common_sw_fini(void *handle) { … } static int vi_common_hw_init(void *handle) { … } static int vi_common_hw_fini(void *handle) { … } static int vi_common_suspend(void *handle) { … } static int vi_common_resume(void *handle) { … } static bool vi_common_is_idle(void *handle) { … } static int vi_common_wait_for_idle(void *handle) { … } static int vi_common_soft_reset(void *handle) { … } static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void vi_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static int vi_common_set_clockgating_state_by_smu(void *handle, enum amd_clockgating_state state) { … } static int vi_common_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int vi_common_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void vi_common_get_clockgating_state(void *handle, u64 *flags) { … } static const struct amd_ip_funcs vi_common_ip_funcs = …; static const struct amdgpu_ip_block_version vi_common_ip_block = …; void vi_set_virt_ops(struct amdgpu_device *adev) { … } int vi_set_ip_blocks(struct amdgpu_device *adev) { … } void legacy_doorbell_index_init(struct amdgpu_device *adev) { … }
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