linux/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

/*
 * Copyright 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: [email protected]
 */

#include "amdgpu.h"
#include "vi.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "vid.h"
#include "gca/gfx_8_0_d.h"
#include "gca/gfx_8_0_sh_mask.h"
#include "gmc_v8_0.h"
#include "gfx_v8_0.h"
#include "sdma_v3_0.h"
#include "tonga_ih.h"
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
#include "smu/smu_7_1_3_d.h"
#include "mxgpu_vi.h"

#include "amdgpu_reset.h"

/* VI golden setting */
static const u32 xgpu_fiji_mgcg_cgcg_init[] = …;

static const u32 xgpu_fiji_golden_settings_a10[] = …;

static const u32 xgpu_fiji_golden_common_all[] = …;

static const u32 xgpu_tonga_mgcg_cgcg_init[] = …;

static const u32 xgpu_tonga_golden_settings_a11[] = …;

static const u32 xgpu_tonga_golden_common_all[] = …;

void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
{ … }

/*
 * Mailbox communication between GPU hypervisor and VFs
 */
static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
{ … }

static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
{ … }

static void xgpu_vi_mailbox_trans_msg(struct amdgpu_device *adev,
				      enum idh_request req)
{ … }

static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev,
				   enum idh_event event)
{ … }

static int xgpu_vi_poll_ack(struct amdgpu_device *adev)
{ … }

static int xgpu_vi_poll_msg(struct amdgpu_device *adev, enum idh_event event)
{ … }

static int xgpu_vi_send_access_requests(struct amdgpu_device *adev,
					enum idh_request request)
{ … }

static int xgpu_vi_request_reset(struct amdgpu_device *adev)
{ … }

static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev)
{ … }

static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
					   bool init)
{ … }

static int xgpu_vi_release_full_gpu_access(struct amdgpu_device *adev,
					   bool init)
{ … }

/* add support mailbox interrupts */
static int xgpu_vi_mailbox_ack_irq(struct amdgpu_device *adev,
				   struct amdgpu_irq_src *source,
				   struct amdgpu_iv_entry *entry)
{ … }

static int xgpu_vi_set_mailbox_ack_irq(struct amdgpu_device *adev,
				       struct amdgpu_irq_src *src,
				       unsigned type,
				       enum amdgpu_interrupt_state state)
{ … }

static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
{ … }

static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
				       struct amdgpu_irq_src *src,
				       unsigned type,
				       enum amdgpu_interrupt_state state)
{ … }

static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev,
				   struct amdgpu_irq_src *source,
				   struct amdgpu_iv_entry *entry)
{ … }

static const struct amdgpu_irq_src_funcs xgpu_vi_mailbox_ack_irq_funcs = …;

static const struct amdgpu_irq_src_funcs xgpu_vi_mailbox_rcv_irq_funcs = …;

void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev)
{ … }

int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
{ … }

int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev)
{ … }

void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev)
{ … }

const struct amdgpu_virt_ops xgpu_vi_virt_ops = …;