linux/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2023, Linaro Limited
 */

#ifndef _DPU_9_2_X1E80100_H
#define _DPU_9_2_X1E80100_H

static const struct dpu_caps x1e80100_dpu_caps = …;

static const struct dpu_mdp_cfg x1e80100_mdp = …;

/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg x1e80100_ctl[] = …;

static const struct dpu_sspp_cfg x1e80100_sspp[] = …;

static const struct dpu_lm_cfg x1e80100_lm[] = …;

static const struct dpu_dspp_cfg x1e80100_dspp[] = …;

static const struct dpu_pingpong_cfg x1e80100_pp[] = …;

static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = …;

/*
 * NOTE: Each display compression engine (DCE) contains dual hard
 * slice DSC encoders so both share same base address but with
 * its own different sub block address.
 */
static const struct dpu_dsc_cfg x1e80100_dsc[] = …;

static const struct dpu_wb_cfg x1e80100_wb[] = …;

/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
static const struct dpu_intf_cfg x1e80100_intf[] = …;

static const struct dpu_perf_cfg x1e80100_perf_data = …;

static const struct dpu_mdss_version x1e80100_mdss_ver = …;

const struct dpu_mdss_cfg dpu_x1e80100_cfg = …;

#endif