/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __ADRENO_GEN7_0_0_SNAPSHOT_H #define __ADRENO_GEN7_0_0_SNAPSHOT_H #include "a6xx_gpu_state.h" static const u32 gen7_0_0_debugbus_blocks[] = …; static struct gen7_shader_block gen7_0_0_shader_blocks[] = …; static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] = …; static_assert(…); static const u32 gen7_0_0_post_crashdumper_registers[] = …; static_assert(…); static const u32 gen7_0_0_gpu_registers[] = …; static_assert(…); static const u32 gen7_0_0_gmu_registers[] = …; static_assert(…); static const u32 gen7_0_0_gmugx_registers[] = …; static_assert(…); static const u32 gen7_0_0_noncontext_pipe_br_registers[] = …; static_assert(…); static const u32 gen7_0_0_noncontext_pipe_bv_registers[] = …; static_assert(…); static const u32 gen7_0_0_noncontext_pipe_lpac_registers[] = …; static_assert(…); static const u32 gen7_0_0_noncontext_rb_rac_pipe_br_registers[] = …; static_assert(…); static const u32 gen7_0_0_noncontext_rb_rbp_pipe_br_registers[] = …; static_assert(…); /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = …; static_assert(…); /* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = …; static_assert(…); /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = …; static_assert(…); /* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = …; static_assert(…); /* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = …; static_assert(…); /* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: SP_TOP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: uSPTP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: uSPTP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: SP_TOP */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: SP_TOP */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: uSPTP */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: uSPTP */ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = …; static_assert(…); /* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: SP_TOP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: uSPTP */ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] = …; static_assert(…); /* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] = …; static_assert(…); /* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = …; static_assert(…); /* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] = …; static_assert(…); /* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] = …; static_assert(…); /* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] = …; static_assert(…); /* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] = …; static_assert(…); /* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */ static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */ static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */ static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] = …; static_assert(…); /* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP */ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = …; static_assert(…); /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = …; static_assert(…); /* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = …; static_assert(…); static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = …; static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = …; static struct gen7_cluster_registers gen7_0_0_clusters[] = …; static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = …; static const u32 gen7_0_0_rscc_registers[] = …; static_assert(…); static const u32 gen7_0_0_cpr_registers[] = …; static_assert(…); static const u32 gen7_0_0_gpucc_registers[] = …; static_assert(…); static const u32 gen7_0_0_cx_misc_registers[] = …; static_assert(…); static const u32 gen7_0_0_dpm_registers[] = …; static_assert(…); static struct gen7_reg_list gen7_0_0_reg_list[] = …; static const u32 *gen7_0_0_external_core_regs[] = …; #endif /*_ADRENO_GEN7_0_0_SNAPSHOT_H */
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