linux/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */
#ifndef __ADRENO_GEN7_2_0_SNAPSHOT_H
#define __ADRENO_GEN7_2_0_SNAPSHOT_H

#include "a6xx_gpu_state.h"

static const u32 gen7_2_0_debugbus_blocks[] = …;

static struct gen7_shader_block gen7_2_0_shader_blocks[] = …;

static const u32 gen7_2_0_gpu_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_gmu_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_gmugx_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_noncontext_pipe_br_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_noncontext_pipe_bv_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_noncontext_rb_rac_pipe_br_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_noncontext_rb_rbp_pipe_br_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_gras_cluster_gras_pipe_br_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_gras_cluster_gras_pipe_bv_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_rb_rac_cluster_ps_pipe_br_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = …;
static_assert(…);

static const struct gen7_sel_reg  gen7_2_0_rb_rac_sel = …;

static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = …;

static struct gen7_cluster_registers gen7_2_0_clusters[] = …;

static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = …;

static const u32 gen7_2_0_dbgc_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_rscc_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_cpr_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_dpm_lkg_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_gpucc_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_cx_misc_registers[] = …;
static_assert(…);

static const u32 gen7_2_0_dpm_registers[] = …;
static_assert(…);

static struct gen7_reg_list gen7_2_0_reg_list[] = …;

static const u32 *gen7_2_0_external_core_regs[] = …;
#endif /*_ADRENO_GEN7_2_0_SNAPSHOT_H */