/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ /* * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. * * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #ifndef _LINUX_SERIAL_REG_H #define _LINUX_SERIAL_REG_H /* * DLAB=0 */ #define UART_RX … #define UART_TX … #define UART_IER … #define UART_IER_MSI … #define UART_IER_RLSI … #define UART_IER_THRI … #define UART_IER_RDI … /* * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 */ #define UART_IERX_SLEEP … #define UART_IIR … #define UART_IIR_NO_INT … #define UART_IIR_ID … #define UART_IIR_MSI … #define UART_IIR_THRI … #define UART_IIR_RDI … #define UART_IIR_RLSI … #define UART_IIR_BUSY … #define UART_IIR_RX_TIMEOUT … #define UART_IIR_XOFF … #define UART_IIR_CTS_RTS_DSR … #define UART_IIR_64BYTE_FIFO … #define UART_IIR_FIFO_ENABLED … #define UART_IIR_FIFO_ENABLED_8250 … #define UART_IIR_FIFO_ENABLED_16550 … #define UART_IIR_FIFO_ENABLED_16550A … #define UART_IIR_FIFO_ENABLED_16750 … #define UART_FCR … #define UART_FCR_ENABLE_FIFO … #define UART_FCR_CLEAR_RCVR … #define UART_FCR_CLEAR_XMIT … #define UART_FCR_DMA_SELECT … /* * Note: The FIFO trigger levels are chip specific: * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 * PC16550D: 1 4 8 14 xx xx xx xx * TI16C550A: 1 4 8 14 xx xx xx xx * TI16C550C: 1 4 8 14 xx xx xx xx * ST16C550: 1 4 8 14 xx xx xx xx * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 * NS16C552: 1 4 8 14 xx xx xx xx * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 * TI16C752: 8 16 56 60 8 16 32 56 * OX16C950: 16 32 112 120 16 32 64 112 PORT_16C950 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA */ #define UART_FCR_R_TRIG_00 … #define UART_FCR_R_TRIG_01 … #define UART_FCR_R_TRIG_10 … #define UART_FCR_R_TRIG_11 … #define UART_FCR_T_TRIG_00 … #define UART_FCR_T_TRIG_01 … #define UART_FCR_T_TRIG_10 … #define UART_FCR_T_TRIG_11 … #define UART_FCR_TRIGGER_MASK … #define UART_FCR_TRIGGER_1 … #define UART_FCR_TRIGGER_4 … #define UART_FCR_TRIGGER_8 … #define UART_FCR_TRIGGER_14 … /* 16650 definitions */ #define UART_FCR6_R_TRIGGER_8 … #define UART_FCR6_R_TRIGGER_16 … #define UART_FCR6_R_TRIGGER_24 … #define UART_FCR6_R_TRIGGER_28 … #define UART_FCR6_T_TRIGGER_16 … #define UART_FCR6_T_TRIGGER_8 … #define UART_FCR6_T_TRIGGER_24 … #define UART_FCR6_T_TRIGGER_30 … #define UART_FCR7_64BYTE … #define UART_FCR_R_TRIG_SHIFT … #define UART_FCR_R_TRIG_BITS(x) … #define UART_FCR_R_TRIG_MAX_STATE … #define UART_LCR … /* * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB … #define UART_LCR_SBC … #define UART_LCR_SPAR … #define UART_LCR_EPAR … #define UART_LCR_PARITY … #define UART_LCR_STOP … #define UART_LCR_WLEN5 … #define UART_LCR_WLEN6 … #define UART_LCR_WLEN7 … #define UART_LCR_WLEN8 … /* * Access to some registers depends on register access / configuration * mode. */ #define UART_LCR_CONF_MODE_A … #define UART_LCR_CONF_MODE_B … #define UART_MCR … #define UART_MCR_CLKSEL … #define UART_MCR_TCRTLR … #define UART_MCR_XONANY … #define UART_MCR_AFE … #define UART_MCR_LOOP … #define UART_MCR_OUT2 … #define UART_MCR_OUT1 … #define UART_MCR_RTS … #define UART_MCR_DTR … #define UART_LSR … #define UART_LSR_FIFOE … #define UART_LSR_TEMT … #define UART_LSR_THRE … #define UART_LSR_BI … #define UART_LSR_FE … #define UART_LSR_PE … #define UART_LSR_OE … #define UART_LSR_DR … #define UART_LSR_BRK_ERROR_BITS … #define UART_MSR … #define UART_MSR_DCD … #define UART_MSR_RI … #define UART_MSR_DSR … #define UART_MSR_CTS … #define UART_MSR_DDCD … #define UART_MSR_TERI … #define UART_MSR_DDSR … #define UART_MSR_DCTS … #define UART_MSR_ANY_DELTA … #define UART_SCR … /* * DLAB=1 */ #define UART_DLL … #define UART_DLM … #define UART_DIV_MAX … /* * LCR=0xBF (or DLAB=1 for 16C660) */ #define UART_EFR … #define UART_XR_EFR … #define UART_EFR_CTS … #define UART_EFR_RTS … #define UART_EFR_SCD … #define UART_EFR_ECB … /* * the low four bits control software flow control */ /* * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 */ #define UART_XON1 … #define UART_XON2 … #define UART_XOFF1 … #define UART_XOFF2 … /* * EFR[4]=1 MCR[6]=1, TI16C752 */ #define UART_TI752_TCR … #define UART_TI752_TLR … /* * LCR=0xBF, XR16C85x */ #define UART_TRG … /* * These are the definitions for the Programmable Trigger Register */ #define UART_TRG_1 … #define UART_TRG_4 … #define UART_TRG_8 … #define UART_TRG_16 … #define UART_TRG_32 … #define UART_TRG_64 … #define UART_TRG_96 … #define UART_TRG_120 … #define UART_TRG_128 … #define UART_FCTR … #define UART_FCTR_RTS_NODELAY … #define UART_FCTR_RTS_4DELAY … #define UART_FCTR_RTS_6DELAY … #define UART_FCTR_RTS_8DELAY … #define UART_FCTR_IRDA … #define UART_FCTR_TX_INT … #define UART_FCTR_TRGA … #define UART_FCTR_TRGB … #define UART_FCTR_TRGC … #define UART_FCTR_TRGD … #define UART_FCTR_SCR_SWAP … #define UART_FCTR_RX … #define UART_FCTR_TX … /* * LCR=0xBF, FCTR[6]=1 */ #define UART_EMSR … #define UART_EMSR_FIFO_COUNT … #define UART_EMSR_ALT_COUNT … /* * The Intel XScale on-chip UARTs define these bits */ #define UART_IER_DMAE … #define UART_IER_UUE … #define UART_IER_NRZE … #define UART_IER_RTOIE … #define UART_IIR_TOD … #define UART_FCR_PXAR1 … #define UART_FCR_PXAR8 … #define UART_FCR_PXAR16 … #define UART_FCR_PXAR32 … /* * These register definitions are for the 16C950 */ #define UART_ASR … #define UART_RFL … #define UART_TFL … #define UART_ICR … /* The 16950 ICR registers */ #define UART_ACR … #define UART_CPR … #define UART_TCR … #define UART_CKS … #define UART_TTL … #define UART_RTL … #define UART_FCL … #define UART_FCH … #define UART_ID1 … #define UART_ID2 … #define UART_ID3 … #define UART_REV … #define UART_CSR … #define UART_NMR … #define UART_CTR … /* * The 16C950 Additional Control Register */ #define UART_ACR_RXDIS … #define UART_ACR_TXDIS … #define UART_ACR_DSRFC … #define UART_ACR_TLENB … #define UART_ACR_ICRRD … #define UART_ACR_ASREN … /* * These definitions are for the RSA-DV II/S card, from * * Kiyokazu SUTO <[email protected]> */ #define UART_RSA_BASE … #define UART_RSA_MSR … #define UART_RSA_MSR_SWAP … #define UART_RSA_MSR_FIFO … #define UART_RSA_MSR_FLOW … #define UART_RSA_MSR_ITYP … #define UART_RSA_IER … #define UART_RSA_IER_Rx_FIFO_H … #define UART_RSA_IER_Tx_FIFO_H … #define UART_RSA_IER_Tx_FIFO_E … #define UART_RSA_IER_Rx_TOUT … #define UART_RSA_IER_TIMER … #define UART_RSA_SRR … #define UART_RSA_SRR_Tx_FIFO_NEMP … #define UART_RSA_SRR_Tx_FIFO_NHFL … #define UART_RSA_SRR_Tx_FIFO_NFUL … #define UART_RSA_SRR_Rx_FIFO_NEMP … #define UART_RSA_SRR_Rx_FIFO_NHFL … #define UART_RSA_SRR_Rx_FIFO_NFUL … #define UART_RSA_SRR_Rx_TOUT … #define UART_RSA_SRR_TIMER … #define UART_RSA_FRR … #define UART_RSA_TIVSR … #define UART_RSA_TCR … #define UART_RSA_TCR_SWITCH … /* * The RSA DSV/II board has two fixed clock frequencies. One is the * standard rate, and the other is 8 times faster. */ #define SERIAL_RSA_BAUD_BASE … #define SERIAL_RSA_BAUD_BASE_LO … /* Extra registers for TI DA8xx/66AK2x */ #define UART_DA830_PWREMU_MGMT … /* PWREMU_MGMT register bits */ #define UART_DA830_PWREMU_MGMT_FREE … #define UART_DA830_PWREMU_MGMT_URRST … #define UART_DA830_PWREMU_MGMT_UTRST … /* * Extra serial register definitions for the internal UARTs * in TI OMAP processors. */ #define OMAP1_UART1_BASE … #define OMAP1_UART2_BASE … #define OMAP1_UART3_BASE … #define UART_OMAP_MDR1 … #define UART_OMAP_MDR2 … #define UART_OMAP_SCR … #define UART_OMAP_SSR … #define UART_OMAP_EBLR … #define UART_OMAP_OSC_12M_SEL … #define UART_OMAP_MVER … #define UART_OMAP_SYSC … #define UART_OMAP_SYSS … #define UART_OMAP_WER … #define UART_OMAP_TX_LVL … /* * These are the definitions for the MDR1 register */ #define UART_OMAP_MDR1_16X_MODE … #define UART_OMAP_MDR1_SIR_MODE … #define UART_OMAP_MDR1_16X_ABAUD_MODE … #define UART_OMAP_MDR1_13X_MODE … #define UART_OMAP_MDR1_MIR_MODE … #define UART_OMAP_MDR1_FIR_MODE … #define UART_OMAP_MDR1_CIR_MODE … #define UART_OMAP_MDR1_DISABLE … /* * These are definitions for the Altera ALTR_16550_F32/F64/F128 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). */ #define UART_ALTR_AFR … #define UART_ALTR_EN_TXFIFO_LW … #define UART_ALTR_TX_LOW … #endif /* _LINUX_SERIAL_REG_H */
Codebase Browser
linux