// SPDX-License-Identifier: GPL-2.0+ /* * drivers/net/phy/at803x.c * * Driver for Qualcomm Atheros AR803x PHY * * Author: Matus Ujhelyi <[email protected]> */ #include <linux/phy.h> #include <linux/module.h> #include <linux/string.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/ethtool_netlink.h> #include <linux/bitfield.h> #include <linux/regulator/of_regulator.h> #include <linux/regulator/driver.h> #include <linux/regulator/consumer.h> #include <linux/of.h> #include <linux/phylink.h> #include <linux/sfp.h> #include <dt-bindings/net/qca-ar803x.h> #include "qcom.h" #define AT803X_LED_CONTROL … #define AT803X_PHY_MMD3_WOL_CTRL … #define AT803X_WOL_EN … #define AT803X_REG_CHIP_CONFIG … #define AT803X_BT_BX_REG_SEL … #define AT803X_MODE_CFG_MASK … #define AT803X_MODE_CFG_BASET_RGMII … #define AT803X_MODE_CFG_BASET_SGMII … #define AT803X_MODE_CFG_BX1000_RGMII_50OHM … #define AT803X_MODE_CFG_BX1000_RGMII_75OHM … #define AT803X_MODE_CFG_BX1000_CONV_50OHM … #define AT803X_MODE_CFG_BX1000_CONV_75OHM … #define AT803X_MODE_CFG_FX100_RGMII_50OHM … #define AT803X_MODE_CFG_FX100_CONV_50OHM … #define AT803X_MODE_CFG_RGMII_AUTO_MDET … #define AT803X_MODE_CFG_FX100_RGMII_75OHM … #define AT803X_MODE_CFG_FX100_CONV_75OHM … #define AT803X_PSSR … #define AT803X_PSSR_MR_AN_COMPLETE … #define AT803X_DEBUG_REG_1F … #define AT803X_DEBUG_PLL_ON … #define AT803X_DEBUG_RGMII_1V8 … /* AT803x supports either the XTAL input pad, an internal PLL or the * DSP as clock reference for the clock output pad. The XTAL reference * is only used for 25 MHz output, all other frequencies need the PLL. * The DSP as a clock reference is used in synchronous ethernet * applications. * * By default the PLL is only enabled if there is a link. Otherwise * the PHY will go into low power state and disabled the PLL. You can * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always * enabled. */ #define AT803X_MMD7_CLK25M … #define AT803X_CLK_OUT_MASK … #define AT803X_CLK_OUT_25MHZ_XTAL … #define AT803X_CLK_OUT_25MHZ_DSP … #define AT803X_CLK_OUT_50MHZ_PLL … #define AT803X_CLK_OUT_50MHZ_DSP … #define AT803X_CLK_OUT_62_5MHZ_PLL … #define AT803X_CLK_OUT_62_5MHZ_DSP … #define AT803X_CLK_OUT_125MHZ_PLL … #define AT803X_CLK_OUT_125MHZ_DSP … /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask * but doesn't support choosing between XTAL/PLL and DSP. */ #define AT8035_CLK_OUT_MASK … #define AT803X_CLK_OUT_STRENGTH_MASK … #define AT803X_CLK_OUT_STRENGTH_FULL … #define AT803X_CLK_OUT_STRENGTH_HALF … #define AT803X_CLK_OUT_STRENGTH_QUARTER … #define AT803X_MMD3_SMARTEEE_CTL1 … #define AT803X_MMD3_SMARTEEE_CTL2 … #define AT803X_MMD3_SMARTEEE_CTL3 … #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN … #define ATH9331_PHY_ID … #define ATH8030_PHY_ID … #define ATH8031_PHY_ID … #define ATH8032_PHY_ID … #define ATH8035_PHY_ID … #define AT8030_PHY_ID_MASK … #define QCA9561_PHY_ID … #define AT803X_PAGE_FIBER … #define AT803X_PAGE_COPPER … /* don't turn off internal PLL */ #define AT803X_KEEP_PLL_ENABLED … #define AT803X_DISABLE_SMARTEEE … /* disable hibernation mode */ #define AT803X_DISABLE_HIBERNATION_MODE … MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; struct at803x_priv { … }; struct at803x_context { … }; static int at803x_write_page(struct phy_device *phydev, int page) { … } static int at803x_read_page(struct phy_device *phydev) { … } static int at803x_enable_rx_delay(struct phy_device *phydev) { … } static int at803x_enable_tx_delay(struct phy_device *phydev) { … } static int at803x_disable_rx_delay(struct phy_device *phydev) { … } static int at803x_disable_tx_delay(struct phy_device *phydev) { … } /* save relevant PHY registers to private copy */ static void at803x_context_save(struct phy_device *phydev, struct at803x_context *context) { … } /* restore relevant PHY registers from private copy */ static void at803x_context_restore(struct phy_device *phydev, const struct at803x_context *context) { … } static int at803x_suspend(struct phy_device *phydev) { … } static int at803x_resume(struct phy_device *phydev) { … } static int at803x_parse_dt(struct phy_device *phydev) { … } static int at803x_probe(struct phy_device *phydev) { … } static int at803x_get_features(struct phy_device *phydev) { … } static int at803x_smarteee_config(struct phy_device *phydev) { … } static int at803x_clk_out_config(struct phy_device *phydev) { … } static int at8031_pll_config(struct phy_device *phydev) { … } static int at803x_hibernation_mode_config(struct phy_device *phydev) { … } static int at803x_config_init(struct phy_device *phydev) { … } static void at803x_link_change_notify(struct phy_device *phydev) { … } static int at803x_config_aneg(struct phy_device *phydev) { … } static int at803x_cable_test_result_trans(u16 status) { … } static bool at803x_cdt_test_failed(u16 status) { … } static bool at803x_cdt_fault_length_valid(u16 status) { … } static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) { … } static int at803x_cable_test_get_status(struct phy_device *phydev, bool *finished, unsigned long pair_mask) { … } static void at803x_cable_test_autoneg(struct phy_device *phydev) { … } static int at803x_cable_test_start(struct phy_device *phydev) { … } static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) { … } static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) { … } static const struct regulator_ops vddio_regulator_ops = …; static const unsigned int vddio_voltage_table[] = …; static const struct regulator_desc vddio_desc = …; static const struct regulator_ops vddh_regulator_ops = …; static const struct regulator_desc vddh_desc = …; static int at8031_register_regulators(struct phy_device *phydev) { … } static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) { … } static const struct sfp_upstream_ops at8031_sfp_ops = …; static int at8031_parse_dt(struct phy_device *phydev) { … } static int at8031_probe(struct phy_device *phydev) { … } static int at8031_config_init(struct phy_device *phydev) { … } static int at8031_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static int at8031_config_intr(struct phy_device *phydev) { … } /* AR8031 and AR8033 share the same read status logic */ static int at8031_read_status(struct phy_device *phydev) { … } /* AR8031 and AR8035 share the same cable test get status reg */ static int at8031_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } /* AR8031 and AR8035 share the same cable test start logic */ static int at8031_cable_test_start(struct phy_device *phydev) { … } /* AR8032, AR9331 and QCA9561 share the same cable test get status reg */ static int at8032_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } static int at8035_parse_dt(struct phy_device *phydev) { … } /* AR8030 and AR8035 shared the same special mask for clk_25m */ static int at8035_probe(struct phy_device *phydev) { … } static struct phy_driver at803x_driver[] = …; module_phy_driver(at803x_driver); static struct mdio_device_id __maybe_unused atheros_tbl[] = …; MODULE_DEVICE_TABLE(mdio, atheros_tbl);
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