/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * HPE UV MMR definitions * * (C) Copyright 2020 Hewlett Packard Enterprise Development LP * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_X86_UV_UV_MMRS_H #define _ASM_X86_UV_UV_MMRS_H /* * This file contains MMR definitions for all UV hubs types. * * To minimize coding differences between hub types, the symbols are * grouped by architecture types. * * UVH - definitions common to all UV hub types. * UVXH - definitions common to UVX class (2, 3, 4). * UVYH - definitions common to UVY class (5). * UV5H - definitions specific to UV type 5 hub. * UV4AH - definitions specific to UV type 4A hub. * UV4H - definitions specific to UV type 4 hub. * UV3H - definitions specific to UV type 3 hub. * UV2H - definitions specific to UV type 2 hub. * * If the MMR exists on all hub types but have different addresses, * use a conditional operator to define the value at runtime. Any * that are not defined are blank. * (UV4A variations only generated if different from uv4) * #define UVHxxx ( * is_uv(UV5) ? UV5Hxxx value : * is_uv(UV4A) ? UV4AHxxx value : * is_uv(UV4) ? UV4Hxxx value : * is_uv(UV3) ? UV3Hxxx value : * is_uv(UV2) ? UV2Hxxx value : * <ucv> or <undef value>) * * Class UVX has UVs (2|3|4|4A). * Class UVY has UVs (5). * * union uvh_xxx { * unsigned long v; * struct uvh_xxx_s { # Common fields only * } s; * struct uv5h_xxx_s { # Full UV5 definition (*) * } s5; * struct uv4ah_xxx_s { # Full UV4A definition (*) * } s4a; * struct uv4h_xxx_s { # Full UV4 definition (*) * } s4; * struct uv3h_xxx_s { # Full UV3 definition (*) * } s3; * struct uv2h_xxx_s { # Full UV2 definition (*) * } s2; * }; * (* - if present and different than the common struct) * * Only essential differences are enumerated. For example, if the address is * the same for all UV's, only a single #define is generated. Likewise, * if the contents is the same for all hubs, only the "s" structure is * generated. * * (GEN Flags: undefs=function) */ /* UV bit masks */ #define UV2 … #define UV3 … #define UV4 … #define UV4A … #define UV5 … #define UVX … #define UVY … #define UV_ANY … #define UV_MMR_ENABLE … #define UV1_HUB_PART_NUMBER … #define UV2_HUB_PART_NUMBER … #define UV2_HUB_PART_NUMBER_X … #define UV3_HUB_PART_NUMBER … #define UV3_HUB_PART_NUMBER_X … #define UV4_HUB_PART_NUMBER … #define UV5_HUB_PART_NUMBER … /* Error function to catch undefined references */ extern unsigned long uv_undefined(char *str); /* ========================================================================= */ /* UVH_EVENT_OCCURRED0 */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED0 … /* UVH common defines*/ #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT … #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK … /* UVXH common defines */ #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT … #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK … #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK … #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT … #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK … /* UVYH common defines */ #define UVYH_EVENT_OCCURRED0_KT_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_KT_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_RH0_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_RH0_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_RH1_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_RH1_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_LH0_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_LH0_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_LH1_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_LH1_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_LH2_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_LH2_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_LH3_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_LH3_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_XB_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_XB_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_RDM_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_RDM_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_NI0_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_NI0_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_NI1_HCERR_SHFT … #define UVYH_EVENT_OCCURRED0_NI1_HCERR_MASK … #define UVYH_EVENT_OCCURRED0_LB_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_LB_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_KT_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_KT_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_RH0_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_RH0_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_RH1_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_RH1_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_LH0_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_LH0_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_LH1_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_LH1_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_LH2_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_LH2_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_LH3_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_LH3_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_XB_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_XB_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_RDM_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_RDM_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_RT0_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_RT0_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_RT1_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_RT1_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_NI0_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_NI0_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_NI1_AOERR0_SHFT … #define UVYH_EVENT_OCCURRED0_NI1_AOERR0_MASK … #define UVYH_EVENT_OCCURRED0_LB_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_LB_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_KT_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_KT_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_RH0_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_RH0_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_RH1_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_RH1_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_LH0_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_LH0_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_LH1_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_LH1_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_LH2_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_LH2_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_LH3_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_LH3_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_XB_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_XB_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_RDM_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_RDM_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_RT0_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_RT0_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_RT1_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_RT1_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_NI0_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_NI0_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_NI1_AOERR1_SHFT … #define UVYH_EVENT_OCCURRED0_NI1_AOERR1_MASK … #define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT … #define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT … #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK … #define UVYH_EVENT_OCCURRED0_L1_NMI_INT_SHFT … #define UVYH_EVENT_OCCURRED0_L1_NMI_INT_MASK … #define UVYH_EVENT_OCCURRED0_STOP_CLOCK_SHFT … #define UVYH_EVENT_OCCURRED0_STOP_CLOCK_MASK … #define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT … #define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_MASK … #define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT … #define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_MASK … #define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT … #define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK … /* UV4 unique defines */ #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT … #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK … #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT … #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK … #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT … #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK … #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT … #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT … #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK … #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT … #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK … #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT … #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK … #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT … #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK … #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT … #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK … #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT … #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK … #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT … #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK … #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT … #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK … #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT … #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK … #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT … #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK … #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT … #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK … /* UV3 unique defines */ #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT … #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK … #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT … #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK … #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT … #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK … #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT … #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK … #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT … #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK … #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT … #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK … #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT … #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT … #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK … #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT … #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK … #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT … #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK … #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT … #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK … #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT … #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK … #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT … #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK … #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT … #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK … #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT … #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK … #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT … #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK … #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT … #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK … #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT … #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK … #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT … #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK … /* UV2 unique defines */ #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT … #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK … #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT … #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK … #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT … #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK … #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT … #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK … #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT … #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK … #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT … #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK … #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT … #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT … #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK … #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT … #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK … #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT … #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK … #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT … #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK … #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT … #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK … #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT … #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK … #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT … #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK … #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT … #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK … #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT … #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK … #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT … #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK … #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT … #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK … #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT … #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK … #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK … #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT … uvh_event_occurred0_u; /* ========================================================================= */ /* UVH_EVENT_OCCURRED0_ALIAS */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED0_ALIAS … /* ========================================================================= */ /* UVH_EVENT_OCCURRED1 */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED1 … /* UVYH common defines */ #define UVYH_EVENT_OCCURRED1_IPI_INT_SHFT … #define UVYH_EVENT_OCCURRED1_IPI_INT_MASK … #define UVYH_EVENT_OCCURRED1_EXTIO_INT0_SHFT … #define UVYH_EVENT_OCCURRED1_EXTIO_INT0_MASK … #define UVYH_EVENT_OCCURRED1_EXTIO_INT1_SHFT … #define UVYH_EVENT_OCCURRED1_EXTIO_INT1_MASK … #define UVYH_EVENT_OCCURRED1_EXTIO_INT2_SHFT … #define UVYH_EVENT_OCCURRED1_EXTIO_INT2_MASK … #define UVYH_EVENT_OCCURRED1_EXTIO_INT3_SHFT … #define UVYH_EVENT_OCCURRED1_EXTIO_INT3_MASK … #define UVYH_EVENT_OCCURRED1_PROFILE_INT_SHFT … #define UVYH_EVENT_OCCURRED1_PROFILE_INT_MASK … #define UVYH_EVENT_OCCURRED1_BAU_DATA_SHFT … #define UVYH_EVENT_OCCURRED1_BAU_DATA_MASK … #define UVYH_EVENT_OCCURRED1_PROC_GENERAL_SHFT … #define UVYH_EVENT_OCCURRED1_PROC_GENERAL_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_MASK … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_SHFT … #define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_MASK … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_SHFT … #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_MASK … /* UV4 unique defines */ #define UV4H_EVENT_OCCURRED1_PROFILE_INT_SHFT … #define UV4H_EVENT_OCCURRED1_PROFILE_INT_MASK … #define UV4H_EVENT_OCCURRED1_BAU_DATA_SHFT … #define UV4H_EVENT_OCCURRED1_BAU_DATA_MASK … #define UV4H_EVENT_OCCURRED1_PROC_GENERAL_SHFT … #define UV4H_EVENT_OCCURRED1_PROC_GENERAL_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_MASK … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_SHFT … #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_MASK … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_SHFT … #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_MASK … /* UV3 unique defines */ #define UV3H_EVENT_OCCURRED1_BAU_DATA_SHFT … #define UV3H_EVENT_OCCURRED1_BAU_DATA_MASK … #define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT … #define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT … #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT … #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT … #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK … #define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT … #define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK … #define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT … #define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK … /* UV2 unique defines */ #define UV2H_EVENT_OCCURRED1_BAU_DATA_SHFT … #define UV2H_EVENT_OCCURRED1_BAU_DATA_MASK … #define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT … #define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT … #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT … #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT … #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK … #define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT … #define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK … #define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT … #define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK … #define UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK … #define UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT … uvyh_event_occurred1_u; /* ========================================================================= */ /* UVH_EVENT_OCCURRED1_ALIAS */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED1_ALIAS … /* ========================================================================= */ /* UVH_EVENT_OCCURRED2 */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED2 … /* UVYH common defines */ #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK … #define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT … #define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK … #define UVYH_EVENT_OCCURRED2_RTC_0_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_0_MASK … #define UVYH_EVENT_OCCURRED2_RTC_1_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_1_MASK … #define UVYH_EVENT_OCCURRED2_RTC_2_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_2_MASK … #define UVYH_EVENT_OCCURRED2_RTC_3_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_3_MASK … #define UVYH_EVENT_OCCURRED2_RTC_4_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_4_MASK … #define UVYH_EVENT_OCCURRED2_RTC_5_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_5_MASK … #define UVYH_EVENT_OCCURRED2_RTC_6_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_6_MASK … #define UVYH_EVENT_OCCURRED2_RTC_7_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_7_MASK … #define UVYH_EVENT_OCCURRED2_RTC_8_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_8_MASK … #define UVYH_EVENT_OCCURRED2_RTC_9_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_9_MASK … #define UVYH_EVENT_OCCURRED2_RTC_10_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_10_MASK … #define UVYH_EVENT_OCCURRED2_RTC_11_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_11_MASK … #define UVYH_EVENT_OCCURRED2_RTC_12_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_12_MASK … #define UVYH_EVENT_OCCURRED2_RTC_13_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_13_MASK … #define UVYH_EVENT_OCCURRED2_RTC_14_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_14_MASK … #define UVYH_EVENT_OCCURRED2_RTC_15_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_15_MASK … #define UVYH_EVENT_OCCURRED2_RTC_16_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_16_MASK … #define UVYH_EVENT_OCCURRED2_RTC_17_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_17_MASK … #define UVYH_EVENT_OCCURRED2_RTC_18_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_18_MASK … #define UVYH_EVENT_OCCURRED2_RTC_19_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_19_MASK … #define UVYH_EVENT_OCCURRED2_RTC_20_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_20_MASK … #define UVYH_EVENT_OCCURRED2_RTC_21_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_21_MASK … #define UVYH_EVENT_OCCURRED2_RTC_22_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_22_MASK … #define UVYH_EVENT_OCCURRED2_RTC_23_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_23_MASK … #define UVYH_EVENT_OCCURRED2_RTC_24_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_24_MASK … #define UVYH_EVENT_OCCURRED2_RTC_25_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_25_MASK … #define UVYH_EVENT_OCCURRED2_RTC_26_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_26_MASK … #define UVYH_EVENT_OCCURRED2_RTC_27_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_27_MASK … #define UVYH_EVENT_OCCURRED2_RTC_28_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_28_MASK … #define UVYH_EVENT_OCCURRED2_RTC_29_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_29_MASK … #define UVYH_EVENT_OCCURRED2_RTC_30_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_30_MASK … #define UVYH_EVENT_OCCURRED2_RTC_31_SHFT … #define UVYH_EVENT_OCCURRED2_RTC_31_MASK … /* UV4 unique defines */ #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT … #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK … #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK … #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT … #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK … #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_0_MASK … #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_1_MASK … #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_2_MASK … #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_3_MASK … #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_4_MASK … #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_5_MASK … #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_6_MASK … #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_7_MASK … #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_8_MASK … #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_9_MASK … #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_10_MASK … #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_11_MASK … #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_12_MASK … #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_13_MASK … #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_14_MASK … #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_15_MASK … #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_16_MASK … #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_17_MASK … #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_18_MASK … #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_19_MASK … #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_20_MASK … #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_21_MASK … #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_22_MASK … #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_23_MASK … #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_24_MASK … #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_25_MASK … #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_26_MASK … #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_27_MASK … #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_28_MASK … #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_29_MASK … #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_30_MASK … #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT … #define UV4H_EVENT_OCCURRED2_RTC_31_MASK … /* UV3 unique defines */ #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_0_MASK … #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_1_MASK … #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_2_MASK … #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_3_MASK … #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_4_MASK … #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_5_MASK … #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_6_MASK … #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_7_MASK … #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_8_MASK … #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_9_MASK … #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_10_MASK … #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_11_MASK … #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_12_MASK … #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_13_MASK … #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_14_MASK … #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_15_MASK … #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_16_MASK … #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_17_MASK … #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_18_MASK … #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_19_MASK … #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_20_MASK … #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_21_MASK … #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_22_MASK … #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_23_MASK … #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_24_MASK … #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_25_MASK … #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_26_MASK … #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_27_MASK … #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_28_MASK … #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_29_MASK … #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_30_MASK … #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT … #define UV3H_EVENT_OCCURRED2_RTC_31_MASK … /* UV2 unique defines */ #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_0_MASK … #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_1_MASK … #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_2_MASK … #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_3_MASK … #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_4_MASK … #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_5_MASK … #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_6_MASK … #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_7_MASK … #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_8_MASK … #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_9_MASK … #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_10_MASK … #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_11_MASK … #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_12_MASK … #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_13_MASK … #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_14_MASK … #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_15_MASK … #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_16_MASK … #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_17_MASK … #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_18_MASK … #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_19_MASK … #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_20_MASK … #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_21_MASK … #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_22_MASK … #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_23_MASK … #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_24_MASK … #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_25_MASK … #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_26_MASK … #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_27_MASK … #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_28_MASK … #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_29_MASK … #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_30_MASK … #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT … #define UV2H_EVENT_OCCURRED2_RTC_31_MASK … #define UVH_EVENT_OCCURRED2_RTC_1_MASK … #define UVH_EVENT_OCCURRED2_RTC_1_SHFT … uvyh_event_occurred2_u; /* ========================================================================= */ /* UVH_EVENT_OCCURRED2_ALIAS */ /* ========================================================================= */ #define UVH_EVENT_OCCURRED2_ALIAS … /* ========================================================================= */ /* UVH_EXTIO_INT0_BROADCAST */ /* ========================================================================= */ #define UVH_EXTIO_INT0_BROADCAST … /* UVH common defines*/ #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT … #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK … uvh_extio_int0_broadcast_u; /* ========================================================================= */ /* UVH_GR0_GAM_GR_CONFIG */ /* ========================================================================= */ #define UVH_GR0_GAM_GR_CONFIG … /* UVYH common defines */ #define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT … #define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_MASK … /* UV4 unique defines */ #define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT … #define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK … /* UV3 unique defines */ #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT … #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK … #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT … #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK … /* UV2 unique defines */ #define UV2H_GR0_GAM_GR_CONFIG_N_GR_SHFT … #define UV2H_GR0_GAM_GR_CONFIG_N_GR_MASK … uvyh_gr0_gam_gr_config_u; /* ========================================================================= */ /* UVH_GR0_TLB_INT0_CONFIG */ /* ========================================================================= */ #define UVH_GR0_TLB_INT0_CONFIG … /* UVXH common defines */ #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_P_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_T_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_M_MASK … #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT … #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK … uvh_gr0_tlb_int0_config_u; /* ========================================================================= */ /* UVH_GR0_TLB_INT1_CONFIG */ /* ========================================================================= */ #define UVH_GR0_TLB_INT1_CONFIG … /* UVXH common defines */ #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_P_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_T_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_M_MASK … #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT … #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK … uvh_gr0_tlb_int1_config_u; /* ========================================================================= */ /* UVH_GR1_TLB_INT0_CONFIG */ /* ========================================================================= */ #define UVH_GR1_TLB_INT0_CONFIG … /* UVXH common defines */ #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_P_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_T_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_M_MASK … #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT … #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK … uvh_gr1_tlb_int0_config_u; /* ========================================================================= */ /* UVH_GR1_TLB_INT1_CONFIG */ /* ========================================================================= */ #define UVH_GR1_TLB_INT1_CONFIG … /* UVXH common defines */ #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_P_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_T_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_M_MASK … #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT … #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK … uvh_gr1_tlb_int1_config_u; /* ========================================================================= */ /* UVH_INT_CMPB */ /* ========================================================================= */ #define UVH_INT_CMPB … /* UVH common defines*/ #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT … #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK … uvh_int_cmpb_u; /* ========================================================================= */ /* UVH_IPI_INT */ /* ========================================================================= */ #define UVH_IPI_INT … /* UVH common defines*/ #define UVH_IPI_INT_VECTOR_SHFT … #define UVH_IPI_INT_VECTOR_MASK … #define UVH_IPI_INT_DELIVERY_MODE_SHFT … #define UVH_IPI_INT_DELIVERY_MODE_MASK … #define UVH_IPI_INT_DESTMODE_SHFT … #define UVH_IPI_INT_DESTMODE_MASK … #define UVH_IPI_INT_APIC_ID_SHFT … #define UVH_IPI_INT_APIC_ID_MASK … #define UVH_IPI_INT_SEND_SHFT … #define UVH_IPI_INT_SEND_MASK … uvh_ipi_int_u; /* ========================================================================= */ /* UVH_NODE_ID */ /* ========================================================================= */ #define UVH_NODE_ID … /* UVH common defines*/ #define UVH_NODE_ID_FORCE1_SHFT … #define UVH_NODE_ID_FORCE1_MASK … #define UVH_NODE_ID_MANUFACTURER_SHFT … #define UVH_NODE_ID_MANUFACTURER_MASK … #define UVH_NODE_ID_PART_NUMBER_SHFT … #define UVH_NODE_ID_PART_NUMBER_MASK … #define UVH_NODE_ID_REVISION_SHFT … #define UVH_NODE_ID_REVISION_MASK … #define UVH_NODE_ID_NODE_ID_SHFT … #define UVH_NODE_ID_NI_PORT_SHFT … /* UVXH common defines */ #define UVXH_NODE_ID_NODE_ID_MASK … #define UVXH_NODE_ID_NODES_PER_BIT_SHFT … #define UVXH_NODE_ID_NODES_PER_BIT_MASK … #define UVXH_NODE_ID_NI_PORT_MASK … /* UVYH common defines */ #define UVYH_NODE_ID_NODE_ID_MASK … #define UVYH_NODE_ID_NI_PORT_MASK … /* UV4 unique defines */ #define UV4H_NODE_ID_ROUTER_SELECT_SHFT … #define UV4H_NODE_ID_ROUTER_SELECT_MASK … #define UV4H_NODE_ID_RESERVED_2_SHFT … #define UV4H_NODE_ID_RESERVED_2_MASK … /* UV3 unique defines */ #define UV3H_NODE_ID_ROUTER_SELECT_SHFT … #define UV3H_NODE_ID_ROUTER_SELECT_MASK … #define UV3H_NODE_ID_RESERVED_2_SHFT … #define UV3H_NODE_ID_RESERVED_2_MASK … uvh_node_id_u; /* ========================================================================= */ /* UVH_NODE_PRESENT_0 */ /* ========================================================================= */ #define UVH_NODE_PRESENT_0 … /* UVYH common defines */ #define UVYH_NODE_PRESENT_0_NODES_SHFT … #define UVYH_NODE_PRESENT_0_NODES_MASK … uvh_node_present_0_u; /* ========================================================================= */ /* UVH_NODE_PRESENT_1 */ /* ========================================================================= */ #define UVH_NODE_PRESENT_1 … /* UVYH common defines */ #define UVYH_NODE_PRESENT_1_NODES_SHFT … #define UVYH_NODE_PRESENT_1_NODES_MASK … uvh_node_present_1_u; /* ========================================================================= */ /* UVH_NODE_PRESENT_TABLE */ /* ========================================================================= */ #define UVH_NODE_PRESENT_TABLE … #define UVH_NODE_PRESENT_TABLE_DEPTH … /* UVXH common defines */ #define UVXH_NODE_PRESENT_TABLE_NODES_SHFT … #define UVXH_NODE_PRESENT_TABLE_NODES_MASK … uvh_node_present_table_u; /* ========================================================================= */ /* UVH_RH10_GAM_ADDR_MAP_CONFIG */ /* ========================================================================= */ #define UVH_RH10_GAM_ADDR_MAP_CONFIG … /* UVYH common defines */ #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT … #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_MASK … #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_SHFT … #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_MASK … #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_SHFT … #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_MASK … uvh_rh10_gam_addr_map_config_u; /* ========================================================================= */ /* UVH_RH10_GAM_GRU_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG … /* UVYH common defines */ #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT … #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK … #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT … #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK … #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … uvh_rh10_gam_gru_overlay_config_u; /* ========================================================================= */ /* UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0 */ /* ========================================================================= */ #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0 … /* UVYH common defines */ #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK … #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … uvh_rh10_gam_mmioh_overlay_config0_u; /* ========================================================================= */ /* UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1 */ /* ========================================================================= */ #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1 … /* UVYH common defines */ #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT … #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK … #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … uvh_rh10_gam_mmioh_overlay_config1_u; /* ========================================================================= */ /* UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0 */ /* ========================================================================= */ #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0 … #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH … /* UVYH common defines */ #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT … #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK … uvh_rh10_gam_mmioh_redirect_config0_u; /* ========================================================================= */ /* UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1 */ /* ========================================================================= */ #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1 … #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH … /* UVYH common defines */ #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT … #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK … uvh_rh10_gam_mmioh_redirect_config1_u; /* ========================================================================= */ /* UVH_RH10_GAM_MMR_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG … /* UVYH common defines */ #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT … #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK … #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT … #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK … #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT … uvh_rh10_gam_mmr_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ADDR_MAP_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ADDR_MAP_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT … #define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT … #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK … /* UV2 unique defines */ #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT … #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK … uvh_rh_gam_addr_map_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_MASK … #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_SHFT … #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_MASK … #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_SHFT … #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_MASK … uvh_rh_gam_alias_0_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_MASK … uvh_rh_gam_alias_0_redirect_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_MASK … #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_SHFT … #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_MASK … #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_SHFT … #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_MASK … uvh_rh_gam_alias_1_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_MASK … uvh_rh_gam_alias_1_redirect_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_MASK … #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_SHFT … #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_MASK … #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_SHFT … #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_MASK … uvh_rh_gam_alias_2_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_SHFT … #define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_MASK … uvh_rh_gam_alias_2_redirect_config_u; /* ========================================================================= */ /* UVH_RH_GAM_GRU_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_GRU_OVERLAY_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT … #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK … #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT … #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK … /* UV4A unique defines */ #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … /* UV4 unique defines */ #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_SHFT … #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_MASK … /* UV2 unique defines */ #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … uvh_rh_gam_gru_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG … /* UV2 unique defines */ #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_MASK … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_SHFT … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_MASK … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_SHFT … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_MASK … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_SHFT … #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_MASK … #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT … uvh_rh_gam_mmioh_overlay_config_u; /* ========================================================================= */ /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0 */ /* ========================================================================= */ #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0 … /* UV4A unique defines */ #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK … /* UV4 unique defines */ #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK … #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK … #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT … uvh_rh_gam_mmioh_overlay_config0_u; /* ========================================================================= */ /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1 */ /* ========================================================================= */ #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1 … /* UV4A unique defines */ #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT … #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK … /* UV4 unique defines */ #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT … #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT … #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK … #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK … #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT … uvh_rh_gam_mmioh_overlay_config1_u; /* ========================================================================= */ /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0 */ /* ========================================================================= */ #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0 … #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH … /* UV4A unique defines */ #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT … #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK … /* UV4 unique defines */ #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT … #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT … #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK … /* UVH common defines */ #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK … uvh_rh_gam_mmioh_redirect_config0_u; /* ========================================================================= */ /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1 */ /* ========================================================================= */ #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1 … #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH … /* UV4A unique defines */ #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT … #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK … /* UV4 unique defines */ #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT … #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK … /* UV3 unique defines */ #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT … #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK … /* UVH common defines */ #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK … uvh_rh_gam_mmioh_redirect_config1_u; /* ========================================================================= */ /* UVH_RH_GAM_MMR_OVERLAY_CONFIG */ /* ========================================================================= */ #define UVH_RH_GAM_MMR_OVERLAY_CONFIG … /* UVXH common defines */ #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT … #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK … #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT … #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK … /* UV4A unique defines */ #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT … #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK … #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT … uvh_rh_gam_mmr_overlay_config_u; /* ========================================================================= */ /* UVH_RTC */ /* ========================================================================= */ #define UVH_RTC … /* UVH common defines*/ #define UVH_RTC_REAL_TIME_CLOCK_SHFT … #define UVH_RTC_REAL_TIME_CLOCK_MASK … uvh_rtc_u; /* ========================================================================= */ /* UVH_RTC1_INT_CONFIG */ /* ========================================================================= */ #define UVH_RTC1_INT_CONFIG … /* UVH common defines*/ #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT … #define UVH_RTC1_INT_CONFIG_VECTOR_MASK … #define UVH_RTC1_INT_CONFIG_DM_SHFT … #define UVH_RTC1_INT_CONFIG_DM_MASK … #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT … #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK … #define UVH_RTC1_INT_CONFIG_STATUS_SHFT … #define UVH_RTC1_INT_CONFIG_STATUS_MASK … #define UVH_RTC1_INT_CONFIG_P_SHFT … #define UVH_RTC1_INT_CONFIG_P_MASK … #define UVH_RTC1_INT_CONFIG_T_SHFT … #define UVH_RTC1_INT_CONFIG_T_MASK … #define UVH_RTC1_INT_CONFIG_M_SHFT … #define UVH_RTC1_INT_CONFIG_M_MASK … #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT … #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK … uvh_rtc1_int_config_u; /* ========================================================================= */ /* UVH_SCRATCH5 */ /* ========================================================================= */ #define UVH_SCRATCH5 … #define UV5H_SCRATCH5 … #define UV4H_SCRATCH5 … #define UV3H_SCRATCH5 … #define UV2H_SCRATCH5 … /* UVH common defines*/ #define UVH_SCRATCH5_SCRATCH5_SHFT … #define UVH_SCRATCH5_SCRATCH5_MASK … /* UVXH common defines */ #define UVXH_SCRATCH5_SCRATCH5_SHFT … #define UVXH_SCRATCH5_SCRATCH5_MASK … /* UVYH common defines */ #define UVYH_SCRATCH5_SCRATCH5_SHFT … #define UVYH_SCRATCH5_SCRATCH5_MASK … /* UV5 unique defines */ #define UV5H_SCRATCH5_SCRATCH5_SHFT … #define UV5H_SCRATCH5_SCRATCH5_MASK … /* UV4 unique defines */ #define UV4H_SCRATCH5_SCRATCH5_SHFT … #define UV4H_SCRATCH5_SCRATCH5_MASK … /* UV3 unique defines */ #define UV3H_SCRATCH5_SCRATCH5_SHFT … #define UV3H_SCRATCH5_SCRATCH5_MASK … /* UV2 unique defines */ #define UV2H_SCRATCH5_SCRATCH5_SHFT … #define UV2H_SCRATCH5_SCRATCH5_MASK … uvh_scratch5_u; /* ========================================================================= */ /* UVH_SCRATCH5_ALIAS */ /* ========================================================================= */ #define UVH_SCRATCH5_ALIAS … #define UV5H_SCRATCH5_ALIAS … #define UV4H_SCRATCH5_ALIAS … #define UV3H_SCRATCH5_ALIAS … #define UV2H_SCRATCH5_ALIAS … /* ========================================================================= */ /* UVH_SCRATCH5_ALIAS_2 */ /* ========================================================================= */ #define UVH_SCRATCH5_ALIAS_2 … #define UV5H_SCRATCH5_ALIAS_2 … #define UV4H_SCRATCH5_ALIAS_2 … #define UV3H_SCRATCH5_ALIAS_2 … #define UV2H_SCRATCH5_ALIAS_2 … #endif /* _ASM_X86_UV_UV_MMRS_H */
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