/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM * Copyright Torsten Duwe <[email protected]> 1993 * derived from Data Sheet, Copyright Motorola 1984 (!). * It was written to be part of the Linux operating system. */ /* permission is hereby granted to copy, modify and redistribute this code * in terms of the GNU Library General Public License, Version 2 or later, * at your option. */ #ifndef _MC146818RTC_H #define _MC146818RTC_H #include <asm/io.h> #include <linux/rtc.h> /* get the user-level API */ #include <asm/mc146818rtc.h> /* register access macros */ #include <linux/bcd.h> #include <linux/delay.h> #include <linux/pm-trace.h> #ifdef __KERNEL__ #include <linux/spinlock.h> /* spinlock_t */ extern spinlock_t rtc_lock; /* serialize CMOS RAM access */ /* Some RTCs extend the mc146818 register set to support alarms of more * than 24 hours in the future; or dates that include a century code. * This platform_data structure can pass this information to the driver. * * Also, some platforms need suspend()/resume() hooks to kick in special * handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up * a separate wakeup alarm used by some almost-clone chips. */ struct cmos_rtc_board_info { … }; #endif /********************************************************************** * register summary **********************************************************************/ #define RTC_SECONDS … #define RTC_SECONDS_ALARM … #define RTC_MINUTES … #define RTC_MINUTES_ALARM … #define RTC_HOURS … #define RTC_HOURS_ALARM … /* RTC_*_alarm is always true if 2 MSBs are set */ #define RTC_ALARM_DONT_CARE … #define RTC_DAY_OF_WEEK … #define RTC_DAY_OF_MONTH … #define RTC_MONTH … #define RTC_YEAR … /* control registers - Moto names */ #define RTC_REG_A … #define RTC_REG_B … #define RTC_REG_C … #define RTC_REG_D … /********************************************************************** * register details **********************************************************************/ #define RTC_FREQ_SELECT … /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, * totalling to a max high interval of 2.228 ms. */ #define RTC_UIP … #define RTC_DIV_CTL … /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ #define RTC_REF_CLCK_4MHZ … #define RTC_REF_CLCK_1MHZ … #define RTC_REF_CLCK_32KHZ … /* 2 values for divider stage reset, others for "testing purposes only" */ #define RTC_DIV_RESET1 … #define RTC_DIV_RESET2 … /* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */ #define RTC_AMD_BANK_SELECT … /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ #define RTC_RATE_SELECT … /**********************************************************************/ #define RTC_CONTROL … #define RTC_SET … #define RTC_PIE … #define RTC_AIE … #define RTC_UIE … #define RTC_SQWE … #define RTC_DM_BINARY … #define RTC_24H … #define RTC_DST_EN … /**********************************************************************/ #define RTC_INTR_FLAGS … /* caution - cleared by read */ #define RTC_IRQF … #define RTC_PF … #define RTC_AF … #define RTC_UF … /**********************************************************************/ #define RTC_VALID … #define RTC_VRT … /**********************************************************************/ #ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */ #define RTC_IO_EXTENT … #define RTC_IO_EXTENT_USED … #define RTC_IOMAPPED … #else #define RTC_IO_EXTENT_USED … #endif /* ARCH_RTC_LOCATION */ bool mc146818_does_rtc_work(void); int mc146818_get_time(struct rtc_time *time, int timeout); int mc146818_set_time(struct rtc_time *time); bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), int timeout, void *param); #endif /* _MC146818RTC_H */
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