/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell Octeon EP (EndPoint) VF Ethernet Driver * * Copyright (C) 2020 Marvell. * */ #ifndef _OCTEP_VF_MAIN_H_ #define _OCTEP_VF_MAIN_H_ #include "octep_vf_tx.h" #include "octep_vf_rx.h" #include "octep_vf_mbox.h" #define OCTEP_VF_DRV_NAME … #define OCTEP_VF_DRV_STRING … #define OCTEP_PCI_DEVICE_ID_CN93_VF … #define OCTEP_PCI_DEVICE_ID_CNF95N_VF … #define OCTEP_PCI_DEVICE_ID_CN98_VF … #define OCTEP_PCI_DEVICE_ID_CN10KA_VF … #define OCTEP_PCI_DEVICE_ID_CNF10KA_VF … #define OCTEP_PCI_DEVICE_ID_CNF10KB_VF … #define OCTEP_PCI_DEVICE_ID_CN10KB_VF … #define OCTEP_VF_MAX_QUEUES … #define OCTEP_VF_MAX_IQ … #define OCTEP_VF_MAX_OQ … #define OCTEP_VF_MAX_MSIX_VECTORS … #define OCTEP_VF_IQ_INTR_RESEND_BIT … #define OCTEP_VF_OQ_INTR_RESEND_BIT … #define IQ_INSTR_PENDING(iq) … #define IQ_INSTR_SPACE(iq) … /* PCI address space mapping information. * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of * Octeon gets mapped to different physical address spaces in * the kernel. */ struct octep_vf_mmio { … }; struct octep_vf_hw_ops { … }; /* Octeon mailbox data */ struct octep_vf_mbox_data { … }; /* wrappers around work structs */ struct octep_vf_mbox_wk { … }; /* Octeon device mailbox */ struct octep_vf_mbox { … }; /* Tx/Rx queue vector per interrupt. */ struct octep_vf_ioq_vector { … }; /* Octeon hardware/firmware offload capability flags. */ #define OCTEP_VF_CAP_TX_CHECKSUM … #define OCTEP_VF_CAP_RX_CHECKSUM … #define OCTEP_VF_CAP_TSO … /* Link modes */ enum octep_vf_link_mode_bit_indices { … }; /* Hardware interface link state information. */ struct octep_vf_iface_link_info { … }; /* Hardware interface stats information. */ struct octep_vf_iface_rxtx_stats { … }; struct octep_vf_fw_info { … }; /* The Octeon device specific private data structure. * Each Octeon device has this structure to represent all its components. */ struct octep_vf_device { … }; static inline u16 OCTEP_VF_MAJOR_REV(struct octep_vf_device *oct) { … } static inline u16 OCTEP_VF_MINOR_REV(struct octep_vf_device *oct) { … } /* Octeon CSR read/write access APIs */ #define octep_vf_write_csr(octep_vf_dev, reg_off, value) … #define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) … #define octep_vf_read_csr(octep_vf_dev, reg_off) … #define octep_vf_read_csr64(octep_vf_dev, reg_off) … extern struct workqueue_struct *octep_vf_wq; int octep_vf_device_setup(struct octep_vf_device *oct); int octep_vf_setup_iqs(struct octep_vf_device *oct); void octep_vf_free_iqs(struct octep_vf_device *oct); void octep_vf_clean_iqs(struct octep_vf_device *oct); int octep_vf_setup_oqs(struct octep_vf_device *oct); void octep_vf_free_oqs(struct octep_vf_device *oct); void octep_vf_oq_dbell_init(struct octep_vf_device *oct); void octep_vf_device_setup_cn93(struct octep_vf_device *oct); void octep_vf_device_setup_cnxk(struct octep_vf_device *oct); int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget); int octep_vf_oq_process_rx(struct octep_vf_oq *oq, int budget); void octep_vf_set_ethtool_ops(struct net_device *netdev); int octep_vf_get_link_info(struct octep_vf_device *oct); int octep_vf_get_if_stats(struct octep_vf_device *oct); void octep_vf_mbox_work(struct work_struct *work); #endif /* _OCTEP_VF_MAIN_H_ */
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