/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell Octeon EP (EndPoint) VF Ethernet Driver * * Copyright (C) 2020 Marvell. * */ #ifndef _OCTEP_VF_REGS_CN9K_H_ #define _OCTEP_VF_REGS_CN9K_H_ /*############################ RST #########################*/ #define CN93_VF_CONFIG_XPANSION_BAR … #define CN93_VF_CONFIG_PCIE_CAP … #define CN93_VF_CONFIG_PCIE_DEVCAP … #define CN93_VF_CONFIG_PCIE_DEVCTL … #define CN93_VF_CONFIG_PCIE_LINKCAP … #define CN93_VF_CONFIG_PCIE_LINKCTL … #define CN93_VF_CONFIG_PCIE_SLOTCAP … #define CN93_VF_CONFIG_PCIE_SLOTCTL … #define CN93_VF_RING_OFFSET … /*###################### RING IN REGISTERS #########################*/ #define CN93_VF_SDP_R_IN_CONTROL_START … #define CN93_VF_SDP_R_IN_ENABLE_START … #define CN93_VF_SDP_R_IN_INSTR_BADDR_START … #define CN93_VF_SDP_R_IN_INSTR_RSIZE_START … #define CN93_VF_SDP_R_IN_INSTR_DBELL_START … #define CN93_VF_SDP_R_IN_CNTS_START … #define CN93_VF_SDP_R_IN_INT_LEVELS_START … #define CN93_VF_SDP_R_IN_PKT_CNT_START … #define CN93_VF_SDP_R_IN_BYTE_CNT_START … #define CN93_VF_SDP_R_IN_CONTROL(ring) … #define CN93_VF_SDP_R_IN_ENABLE(ring) … #define CN93_VF_SDP_R_IN_INSTR_BADDR(ring) … #define CN93_VF_SDP_R_IN_INSTR_RSIZE(ring) … #define CN93_VF_SDP_R_IN_INSTR_DBELL(ring) … #define CN93_VF_SDP_R_IN_CNTS(ring) … #define CN93_VF_SDP_R_IN_INT_LEVELS(ring) … #define CN93_VF_SDP_R_IN_PKT_CNT(ring) … #define CN93_VF_SDP_R_IN_BYTE_CNT(ring) … /*------------------ R_IN Masks ----------------*/ /** Rings per Virtual Function **/ #define CN93_VF_R_IN_CTL_RPVF_MASK … #define CN93_VF_R_IN_CTL_RPVF_POS … /* Number of instructions to be read in one MAC read request. * setting to Max value(4) **/ #define CN93_VF_R_IN_CTL_IDLE … #define CN93_VF_R_IN_CTL_RDSIZE … #define CN93_VF_R_IN_CTL_IS_64B … #define CN93_VF_R_IN_CTL_D_NSR … #define CN93_VF_R_IN_CTL_D_ESR … #define CN93_VF_R_IN_CTL_D_ROR … #define CN93_VF_R_IN_CTL_NSR … #define CN93_VF_R_IN_CTL_ESR … #define CN93_VF_R_IN_CTL_ROR … #define CN93_VF_R_IN_CTL_MASK … /*###################### RING OUT REGISTERS #########################*/ #define CN93_VF_SDP_R_OUT_CNTS_START … #define CN93_VF_SDP_R_OUT_INT_LEVELS_START … #define CN93_VF_SDP_R_OUT_SLIST_BADDR_START … #define CN93_VF_SDP_R_OUT_SLIST_RSIZE_START … #define CN93_VF_SDP_R_OUT_SLIST_DBELL_START … #define CN93_VF_SDP_R_OUT_CONTROL_START … #define CN93_VF_SDP_R_OUT_ENABLE_START … #define CN93_VF_SDP_R_OUT_PKT_CNT_START … #define CN93_VF_SDP_R_OUT_BYTE_CNT_START … #define CN93_VF_SDP_R_OUT_CONTROL(ring) … #define CN93_VF_SDP_R_OUT_ENABLE(ring) … #define CN93_VF_SDP_R_OUT_SLIST_BADDR(ring) … #define CN93_VF_SDP_R_OUT_SLIST_RSIZE(ring) … #define CN93_VF_SDP_R_OUT_SLIST_DBELL(ring) … #define CN93_VF_SDP_R_OUT_CNTS(ring) … #define CN93_VF_SDP_R_OUT_INT_LEVELS(ring) … #define CN93_VF_SDP_R_OUT_PKT_CNT(ring) … #define CN93_VF_SDP_R_OUT_BYTE_CNT(ring) … /*------------------ R_OUT Masks ----------------*/ #define CN93_VF_R_OUT_INT_LEVELS_BMODE … #define CN93_VF_R_OUT_INT_LEVELS_TIMET … #define CN93_VF_R_OUT_CTL_IDLE … #define CN93_VF_R_OUT_CTL_ES_I … #define CN93_VF_R_OUT_CTL_NSR_I … #define CN93_VF_R_OUT_CTL_ROR_I … #define CN93_VF_R_OUT_CTL_ES_D … #define CN93_VF_R_OUT_CTL_NSR_D … #define CN93_VF_R_OUT_CTL_ROR_D … #define CN93_VF_R_OUT_CTL_ES_P … #define CN93_VF_R_OUT_CTL_NSR_P … #define CN93_VF_R_OUT_CTL_ROR_P … #define CN93_VF_R_OUT_CTL_IMODE … /* ##################### Mail Box Registers ########################## */ /* SDP PF to VF Mailbox Data Register */ #define CN93_VF_SDP_R_MBOX_PF_VF_DATA_START … /* SDP Packet PF to VF Mailbox Interrupt Register */ #define CN93_VF_SDP_R_MBOX_PF_VF_INT_START … /* SDP VF to PF Mailbox Data Register */ #define CN93_VF_SDP_R_MBOX_VF_PF_DATA_START … #define CN93_VF_SDP_R_MBOX_PF_VF_INT_ENAB … #define CN93_VF_SDP_R_MBOX_PF_VF_INT_STATUS … #define CN93_VF_SDP_R_MBOX_PF_VF_DATA(ring) … #define CN93_VF_SDP_R_MBOX_PF_VF_INT(ring) … #define CN93_VF_SDP_R_MBOX_VF_PF_DATA(ring) … #endif /* _OCTEP_VF_REGS_CN9K_H_ */
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