linux/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c

// SPDX-License-Identifier: GPL-2.0
/* Marvell Octeon EP (EndPoint) VF Ethernet Driver
 *
 * Copyright (C) 2020 Marvell.
 *
 */

#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>

#include "octep_vf_config.h"
#include "octep_vf_main.h"
#include "octep_vf_regs_cn9k.h"

/* Dump useful hardware IQ/OQ CSRs for debug purpose */
static void cn93_vf_dump_q_regs(struct octep_vf_device *oct, int qno)
{ … }

/* Reset Hardware Tx queue */
static void cn93_vf_reset_iq(struct octep_vf_device *oct, int q_no)
{ … }

/* Reset Hardware Rx queue */
static void cn93_vf_reset_oq(struct octep_vf_device *oct, int q_no)
{ … }

/* Reset all hardware Tx/Rx queues */
static void octep_vf_reset_io_queues_cn93(struct octep_vf_device *oct)
{ … }

/* Initialize configuration limits and initial active config */
static void octep_vf_init_config_cn93_vf(struct octep_vf_device *oct)
{ … }

/* Setup registers for a hardware Tx Queue  */
static void octep_vf_setup_iq_regs_cn93(struct octep_vf_device *oct, int iq_no)
{ … }

/* Setup registers for a hardware Rx Queue  */
static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq_no)
{ … }

/* Setup registers for a VF mailbox */
static void octep_vf_setup_mbox_regs_cn93(struct octep_vf_device *oct, int q_no)
{ … }

/* Mailbox Interrupt handler */
static void cn93_handle_vf_mbox_intr(struct octep_vf_device *oct)
{ … }

/* Tx/Rx queue interrupt handler */
static irqreturn_t octep_vf_ioq_intr_handler_cn93(void *data)
{ … }

/* Re-initialize Octeon hardware registers */
static void octep_vf_reinit_regs_cn93(struct octep_vf_device *oct)
{ … }

/* Enable all interrupts */
static void octep_vf_enable_interrupts_cn93(struct octep_vf_device *oct)
{ … }

/* Disable all interrupts */
static void octep_vf_disable_interrupts_cn93(struct octep_vf_device *oct)
{ … }

/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
static u32 octep_vf_update_iq_read_index_cn93(struct octep_vf_iq *iq)
{ … }

/* Enable a hardware Tx Queue */
static void octep_vf_enable_iq_cn93(struct octep_vf_device *oct, int iq_no)
{ … }

/* Enable a hardware Rx Queue */
static void octep_vf_enable_oq_cn93(struct octep_vf_device *oct, int oq_no)
{ … }

/* Enable all hardware Tx/Rx Queues assigned to VF */
static void octep_vf_enable_io_queues_cn93(struct octep_vf_device *oct)
{ … }

/* Disable a hardware Tx Queue assigned to VF */
static void octep_vf_disable_iq_cn93(struct octep_vf_device *oct, int iq_no)
{ … }

/* Disable a hardware Rx Queue assigned to VF */
static void octep_vf_disable_oq_cn93(struct octep_vf_device *oct, int oq_no)
{ … }

/* Disable all hardware Tx/Rx Queues assigned to VF */
static void octep_vf_disable_io_queues_cn93(struct octep_vf_device *oct)
{ … }

/* Dump hardware registers (including Tx/Rx queues) for debugging. */
static void octep_vf_dump_registers_cn93(struct octep_vf_device *oct)
{ … }

/**
 * octep_vf_device_setup_cn93() - Setup Octeon device.
 *
 * @oct: Octeon device private data structure.
 *
 * - initialize hardware operations.
 * - get target side pcie port number for the device.
 * - set initial configuration and max limits.
 */
void octep_vf_device_setup_cn93(struct octep_vf_device *oct)
{ … }