/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * SGI UV architectural definitions * * (C) Copyright 2020 Hewlett Packard Enterprise Development LP * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_X86_UV_UV_HUB_H #define _ASM_X86_UV_UV_HUB_H #ifdef CONFIG_X86_64 #include <linux/numa.h> #include <linux/percpu.h> #include <linux/timer.h> #include <linux/io.h> #include <linux/topology.h> #include <asm/types.h> #include <asm/percpu.h> #include <asm/uv/uv.h> #include <asm/uv/uv_mmrs.h> #include <asm/uv/bios.h> #include <asm/irq_vectors.h> #include <asm/io_apic.h> /* * Addressing Terminology * * M - The low M bits of a physical address represent the offset * into the blade local memory. RAM memory on a blade is physically * contiguous (although various IO spaces may punch holes in * it).. * * N - Number of bits in the node portion of a socket physical * address. * * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of * routers always have low bit of 1, C/MBricks have low bit * equal to 0. Most addressing macros that target UV hub chips * right shift the NASID by 1 to exclude the always-zero bit. * NASIDs contain up to 15 bits. * * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead * of nasids. * * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant * of the nasid for socket usage. * * GPA - (global physical address) a socket physical address converted * so that it can be used by the GRU as a global address. Socket * physical addresses 1) need additional NASID (node) bits added * to the high end of the address, and 2) unaliased if the * partition does not have a physical address 0. In addition, on * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. * * * NumaLink Global Physical Address Format: * +--------------------------------+---------------------+ * |00..000| GNODE | NodeOffset | * +--------------------------------+---------------------+ * |<-------53 - M bits --->|<--------M bits -----> * * M - number of node offset bits (35 .. 40) * * * Memory/UV-HUB Processor Socket Address Format: * +----------------+---------------+---------------------+ * |00..000000000000| PNODE | NodeOffset | * +----------------+---------------+---------------------+ * <--- N bits --->|<--------M bits -----> * * M - number of node offset bits (35 .. 40) * N - number of PNODE bits (0 .. 10) * * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). * The actual values are configuration dependent and are set at * boot time. M & N values are set by the hardware/BIOS at boot. * * * APICID format * NOTE!!!!!! This is the current format of the APICID. However, code * should assume that this will change in the future. Use functions * in this file for all APICID bit manipulations and conversion. * * 1111110000000000 * 5432109876543210 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) * pppppppppppcccch SandyBridge (15 bits in hdw reg) * sssssssssss * * p = pnode bits * l = socket number on board * c = core * h = hyperthread * s = bits that are in the SOCKET_ID CSR * * Note: Processor may support fewer bits in the APICID register. The ACPI * tables hold all 16 bits. Software needs to be aware of this. * * Unless otherwise specified, all references to APICID refer to * the FULL value contained in ACPI tables, not the subset in the * processor APICID register. */ /* * Maximum number of bricks in all partitions and in all coherency domains. * This is the total number of bricks accessible in the numalink fabric. It * includes all C & M bricks. Routers are NOT included. * * This value is also the value of the maximum number of non-router NASIDs * in the numalink fabric. * * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. */ #define UV_MAX_NUMALINK_BLADES … /* * Maximum number of C/Mbricks within a software SSI (hardware may support * more). */ #define UV_MAX_SSI_BLADES … /* * The largest possible NASID of a C or M brick (+ 2) */ #define UV_MAX_NASID_VALUE … /* GAM (globally addressed memory) range table */ struct uv_gam_range_s { … }; /* * The following defines attributes of the HUB chip. These attributes are * frequently referenced and are kept in a common per hub struct. * After setup, the struct is read only, so it should be readily * available in the L3 cache on the cpu socket for the node. */ struct uv_hub_info_s { … }; /* CPU specific info with a pointer to the hub common info struct */ struct uv_cpu_info_s { … }; DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); #define uv_cpu_info … #define uv_cpu_info_per(cpu) … /* Node specific hub common info struct */ extern void **__uv_hub_info_list; static inline struct uv_hub_info_s *uv_hub_info_list(int node) { … } static inline struct uv_hub_info_s *_uv_hub_info(void) { … } #define uv_hub_info … static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) { … } static inline int uv_hub_type(void) { … } static inline __init void uv_hub_type_set(int uvmask) { … } /* * HUB revision ranges for each UV HUB architecture. * This is a software convention - NOT the hardware revision numbers in * the hub chip. */ #define UV2_HUB_REVISION_BASE … #define UV3_HUB_REVISION_BASE … #define UV4_HUB_REVISION_BASE … #define UV4A_HUB_REVISION_BASE … #define UV5_HUB_REVISION_BASE … static inline int is_uv(int uvmask) { … } static inline int is_uv1_hub(void) { … } static inline int is_uv2_hub(void) { … } static inline int is_uv3_hub(void) { … } static inline int is_uv4a_hub(void) { … } static inline int is_uv4_hub(void) { … } static inline int is_uv5_hub(void) { … } /* * UV4A is a revision of UV4. So on UV4A, both is_uv4_hub() and * is_uv4a_hub() return true, While on UV4, only is_uv4_hub() * returns true. So to get true results, first test if is UV4A, * then test if is UV4. */ /* UVX class: UV2,3,4 */ static inline int is_uvx_hub(void) { … } /* UVY class: UV5,..? */ static inline int is_uvy_hub(void) { … } /* Any UV Hubbed System */ static inline int is_uv_hub(void) { … } uvh_apicid; /* * Local & Global MMR space macros. * Note: macros are intended to be used ONLY by inline functions * in this file - not by other kernel code. * n - NASID (full 15-bit global nasid) * g - GNODE (full 15-bit global nasid, right shifted 1) * p - PNODE (local part of nsids, right shifted 1) */ #define UV_NASID_TO_PNODE(n) … #define UV_PNODE_TO_GNODE(p) … #define UV_PNODE_TO_NASID(p) … #define UV2_LOCAL_MMR_BASE … #define UV2_GLOBAL_MMR32_BASE … #define UV2_LOCAL_MMR_SIZE … #define UV2_GLOBAL_MMR32_SIZE … #define UV3_LOCAL_MMR_BASE … #define UV3_GLOBAL_MMR32_BASE … #define UV3_LOCAL_MMR_SIZE … #define UV3_GLOBAL_MMR32_SIZE … #define UV4_LOCAL_MMR_BASE … #define UV4_GLOBAL_MMR32_BASE … #define UV4_LOCAL_MMR_SIZE … #define UV4_GLOBAL_MMR32_SIZE … #define UV5_LOCAL_MMR_BASE … #define UV5_GLOBAL_MMR32_BASE … #define UV5_LOCAL_MMR_SIZE … #define UV5_GLOBAL_MMR32_SIZE … #define UV_LOCAL_MMR_BASE … #define UV_GLOBAL_MMR32_BASE … #define UV_LOCAL_MMR_SIZE … #define UV_GLOBAL_MMR32_SIZE … #define UV_GLOBAL_MMR64_BASE … #define UV_GLOBAL_GRU_MMR_BASE … #define UV_GLOBAL_MMR32_PNODE_SHIFT … #define _UV_GLOBAL_MMR64_PNODE_SHIFT … #define UV_GLOBAL_MMR64_PNODE_SHIFT … #define UV_GLOBAL_MMR32_PNODE_BITS(p) … #define UV_GLOBAL_MMR64_PNODE_BITS(p) … #define UVH_APICID … #define UV_APIC_PNODE_SHIFT … /* Local Bus from cpu's perspective */ #define LOCAL_BUS_BASE … #define LOCAL_BUS_SIZE … /* * System Controller Interface Reg * * Note there are NO leds on a UV system. This register is only * used by the system controller to monitor system-wide operation. * There are 64 regs per node. With Nehalem cpus (2 cores per node, * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on * a node. * * The window is located at top of ACPI MMR space */ #define SCIR_WINDOW_COUNT … #define SCIR_LOCAL_MMR_BASE … #define SCIR_CPU_HEARTBEAT … #define SCIR_CPU_ACTIVITY … #define SCIR_CPU_HB_INTERVAL … /* Loop through all installed blades */ #define for_each_possible_blade(bid) … /* * Macros for converting between kernel virtual addresses, socket local physical * addresses, and UV global physical addresses. * Note: use the standard __pa() & __va() macros for converting * between socket virtual and socket physical addresses. */ /* global bits offset - number of local address bits in gpa for this UV arch */ static inline unsigned int uv_gpa_shift(void) { … } #define _uv_gpa_shift /* Find node that has the address range that contains global address */ static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) { … } /* Return base address of node that contains global address */ static inline unsigned long uv_gam_range_base(unsigned long pa) { … } /* socket phys RAM --> UV global NASID (UV4+) */ static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) { … } #define _uv_soc_phys_ram_to_nasid /* socket virtual --> UV global NASID (UV4+) */ static inline unsigned long uv_gpa_nasid(void *v) { … } /* socket phys RAM --> UV global physical address */ static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) { … } /* socket virtual --> UV global physical address */ static inline unsigned long uv_gpa(void *v) { … } /* Top two bits indicate the requested address is in MMR space. */ static inline int uv_gpa_in_mmr_space(unsigned long gpa) { … } /* UV global physical address --> socket phys RAM */ static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) { … } /* gpa -> gnode */ static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) { … } /* gpa -> pnode */ static inline int uv_gpa_to_pnode(unsigned long gpa) { … } /* gpa -> node offset */ static inline unsigned long uv_gpa_to_offset(unsigned long gpa) { … } /* Convert socket to node */ static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) { … } static inline int uv_socket_to_node(int socket) { … } static inline int uv_pnode_to_socket(int pnode) { … } /* pnode, offset --> socket virtual */ static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) { … } /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ static inline int uv_apicid_to_pnode(int apicid) { … } /* * Access global MMRs using the low memory MMR32 space. This region supports * faster MMR access but not all MMRs are accessible in this space. */ static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) { … } static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) { … } static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) { … } /* * Access Global MMR space using the MMR space located at the top of physical * memory. */ static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) { … } static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) { … } static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) { … } static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) { … } static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) { … } /* * Access hub local MMRs. Faster than using global space but only local MMRs * are accessible. */ static inline unsigned long *uv_local_mmr_address(unsigned long offset) { … } static inline unsigned long uv_read_local_mmr(unsigned long offset) { … } static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) { … } static inline unsigned char uv_read_local_mmr8(unsigned long offset) { … } static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) { … } /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ static inline int uv_blade_processor_id(void) { … } /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ static inline int uv_cpu_blade_processor_id(int cpu) { … } /* Blade number to Node number (UV2..UV4 is 1:1) */ static inline int uv_blade_to_node(int blade) { … } /* Blade number of current cpu. Numbered 0 .. <#blades -1> */ static inline int uv_numa_blade_id(void) { … } /* * Convert linux node number to the UV blade number. * .. Currently for UV2 thru UV4 the node and the blade are identical. * .. UV5 needs conversion when sub-numa clustering is enabled. */ static inline int uv_node_to_blade_id(int nid) { … } /* Convert a CPU number to the UV blade number */ static inline int uv_cpu_to_blade_id(int cpu) { … } /* Convert a blade id to the PNODE of the blade */ static inline int uv_blade_to_pnode(int bid) { … } /* Nid of memory node on blade. -1 if no blade-local memory */ static inline int uv_blade_to_memory_nid(int bid) { … } /* Determine the number of possible cpus on a blade */ static inline int uv_blade_nr_possible_cpus(int bid) { … } /* Determine the number of online cpus on a blade */ static inline int uv_blade_nr_online_cpus(int bid) { … } /* Convert a cpu id to the PNODE of the blade containing the cpu */ static inline int uv_cpu_to_pnode(int cpu) { … } /* Convert a linux node number to the PNODE of the blade */ static inline int uv_node_to_pnode(int nid) { … } /* Maximum possible number of blades */ extern short uv_possible_blades; static inline int uv_num_possible_blades(void) { … } /* Per Hub NMI support */ extern void uv_nmi_setup(void); extern void uv_nmi_setup_hubless(void); /* BIOS/Kernel flags exchange MMR */ #define UVH_BIOS_KERNEL_MMR … #define UVH_BIOS_KERNEL_MMR_ALIAS … #define UVH_BIOS_KERNEL_MMR_ALIAS_2 … /* TSC sync valid, set by BIOS */ #define UVH_TSC_SYNC_MMR … #define UVH_TSC_SYNC_SHIFT … #define UVH_TSC_SYNC_SHIFT_UV2K … #define UVH_TSC_SYNC_MASK … #define UVH_TSC_SYNC_VALID … #define UVH_TSC_SYNC_UNKNOWN … /* BMC sets a bit this MMR non-zero before sending an NMI */ #define UVH_NMI_MMR … #define UVH_NMI_MMR_CLEAR … #define UVH_NMI_MMR_SHIFT … #define UVH_NMI_MMR_TYPE … struct uv_hub_nmi_s { … }; struct uv_cpu_nmi_s { … }; DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); #define uv_hub_nmi … #define uv_cpu_nmi_per(cpu) … #define uv_hub_nmi_per(cpu) … /* uv_cpu_nmi_states */ #define UV_NMI_STATE_OUT … #define UV_NMI_STATE_IN … #define UV_NMI_STATE_DUMP … #define UV_NMI_STATE_DUMP_DONE … /* * Get the minimum revision number of the hub chips within the partition. * (See UVx_HUB_REVISION_BASE above for specific values.) */ static inline int uv_get_min_hub_revision_id(void) { … } #endif /* CONFIG_X86_64 */ #endif /* _ASM_X86_UV_UV_HUB_H */
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