// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved */ #include <linux/sizes.h> #include <linux/vfio_pci_core.h> /* * The device memory usable to the workloads running in the VM is cached * and showcased as a 64b device BAR (comprising of BAR4 and BAR5 region) * to the VM and is represented as usemem. * Moreover, the VM GPU device driver needs a non-cacheable region to * support the MIG feature. This region is also exposed as a 64b BAR * (comprising of BAR2 and BAR3 region) and represented as resmem. */ #define RESMEM_REGION_INDEX … #define USEMEM_REGION_INDEX … /* Memory size expected as non cached and reserved by the VM driver */ #define RESMEM_SIZE … /* A hardwired and constant ABI value between the GPU FW and VFIO driver. */ #define MEMBLK_SIZE … /* * The state of the two device memory region - resmem and usemem - is * saved as struct mem_region. */ struct mem_region { … }; struct nvgrace_gpu_pci_core_device { … }; static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev) { … } /* Choose the structure corresponding to the fake BAR with a given index. */ static struct mem_region * nvgrace_gpu_memregion(int index, struct nvgrace_gpu_pci_core_device *nvdev) { … } static int nvgrace_gpu_open_device(struct vfio_device *core_vdev) { … } static void nvgrace_gpu_close_device(struct vfio_device *core_vdev) { … } static int nvgrace_gpu_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma) { … } static long nvgrace_gpu_ioctl_get_region_info(struct vfio_device *core_vdev, unsigned long arg) { … } static long nvgrace_gpu_ioctl(struct vfio_device *core_vdev, unsigned int cmd, unsigned long arg) { … } static __le64 nvgrace_gpu_get_read_value(size_t bar_size, u64 flags, __le64 val64) { … } /* * Both the usable (usemem) and the reserved (resmem) device memory region * are exposed as a 64b fake device BARs in the VM. These fake BARs must * respond to the accesses on their respective PCI config space offsets. * * resmem BAR owns PCI_BASE_ADDRESS_2 & PCI_BASE_ADDRESS_3. * usemem BAR owns PCI_BASE_ADDRESS_4 & PCI_BASE_ADDRESS_5. */ static ssize_t nvgrace_gpu_read_config_emu(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) { … } static ssize_t nvgrace_gpu_write_config_emu(struct vfio_device *core_vdev, const char __user *buf, size_t count, loff_t *ppos) { … } /* * Ad hoc map the device memory in the module kernel VA space. Primarily needed * as vfio does not require the userspace driver to only perform accesses through * mmaps of the vfio-pci BAR regions and such accesses should be supported using * vfio_device_ops read/write implementations. * * The usemem region is cacheable memory and hence is memremaped. * The resmem region is non-cached and is mapped using ioremap_wc (NORMAL_NC). */ static int nvgrace_gpu_map_device_mem(int index, struct nvgrace_gpu_pci_core_device *nvdev) { … } /* * Read the data from the device memory (mapped either through ioremap * or memremap) into the user buffer. */ static int nvgrace_gpu_map_and_read(struct nvgrace_gpu_pci_core_device *nvdev, char __user *buf, size_t mem_count, loff_t *ppos) { … } /* * Read count bytes from the device memory at an offset. The actual device * memory size (available) may not be a power-of-2. So the driver fakes * the size to a power-of-2 (reported) when exposing to a user space driver. * * Reads starting beyond the reported size generate -EINVAL; reads extending * beyond the actual device size is filled with ~0; reads extending beyond * the reported size are truncated. */ static ssize_t nvgrace_gpu_read_mem(struct nvgrace_gpu_pci_core_device *nvdev, char __user *buf, size_t count, loff_t *ppos) { … } static ssize_t nvgrace_gpu_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) { … } /* * Write the data to the device memory (mapped either through ioremap * or memremap) from the user buffer. */ static int nvgrace_gpu_map_and_write(struct nvgrace_gpu_pci_core_device *nvdev, const char __user *buf, size_t mem_count, loff_t *ppos) { … } /* * Write count bytes to the device memory at a given offset. The actual device * memory size (available) may not be a power-of-2. So the driver fakes the * size to a power-of-2 (reported) when exposing to a user space driver. * * Writes extending beyond the reported size are truncated; writes starting * beyond the reported size generate -EINVAL. */ static ssize_t nvgrace_gpu_write_mem(struct nvgrace_gpu_pci_core_device *nvdev, size_t count, loff_t *ppos, const char __user *buf) { … } static ssize_t nvgrace_gpu_write(struct vfio_device *core_vdev, const char __user *buf, size_t count, loff_t *ppos) { … } static const struct vfio_device_ops nvgrace_gpu_pci_ops = …; static const struct vfio_device_ops nvgrace_gpu_pci_core_ops = …; static int nvgrace_gpu_fetch_memory_property(struct pci_dev *pdev, u64 *pmemphys, u64 *pmemlength) { … } static int nvgrace_gpu_init_nvdev_struct(struct pci_dev *pdev, struct nvgrace_gpu_pci_core_device *nvdev, u64 memphys, u64 memlength) { … } static int nvgrace_gpu_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static void nvgrace_gpu_remove(struct pci_dev *pdev) { … } static const struct pci_device_id nvgrace_gpu_vfio_pci_table[] = …; MODULE_DEVICE_TABLE(pci, nvgrace_gpu_vfio_pci_table); static struct pci_driver nvgrace_gpu_vfio_pci_driver = …; module_pci_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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