/* SPDX-License-Identifier: GPL-2.0 */ /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ /* true: device connected */ #define PORT_CONNECT … /* true: port enabled */ #define PORT_PE … /* bit 2 reserved and zeroed */ /* true: port has an over-current condition */ #define PORT_OC … /* true: port reset signaling asserted */ #define PORT_RESET … /* Port Link State - bits 5:8 * A read gives the current link PM state of the port, * a write with Link State Write Strobe set sets the link state. */ #define PORT_PLS_MASK … #define XDEV_U0 … #define XDEV_U1 … #define XDEV_U2 … #define XDEV_U3 … #define XDEV_DISABLED … #define XDEV_RXDETECT … #define XDEV_INACTIVE … #define XDEV_POLLING … #define XDEV_RECOVERY … #define XDEV_HOT_RESET … #define XDEV_COMP_MODE … #define XDEV_TEST_MODE … #define XDEV_RESUME … /* true: port has power (see HCC_PPC) */ #define PORT_POWER … /* bits 10:13 indicate device speed: * 0 - undefined speed - port hasn't be initialized by a reset yet * 1 - full speed * 2 - low speed * 3 - high speed * 4 - super speed * 5-15 reserved */ #define DEV_SPEED_MASK … #define XDEV_FS … #define XDEV_LS … #define XDEV_HS … #define XDEV_SS … #define XDEV_SSP … #define DEV_UNDEFSPEED(p) … #define DEV_FULLSPEED(p) … #define DEV_LOWSPEED(p) … #define DEV_HIGHSPEED(p) … #define DEV_SUPERSPEED(p) … #define DEV_SUPERSPEEDPLUS(p) … #define DEV_SUPERSPEED_ANY(p) … #define DEV_PORT_SPEED(p) … /* Bits 20:23 in the Slot Context are the speed for the device */ #define SLOT_SPEED_FS … #define SLOT_SPEED_LS … #define SLOT_SPEED_HS … #define SLOT_SPEED_SS … #define SLOT_SPEED_SSP … /* Port Indicator Control */ #define PORT_LED_OFF … #define PORT_LED_AMBER … #define PORT_LED_GREEN … #define PORT_LED_MASK … /* Port Link State Write Strobe - set this when changing link state */ #define PORT_LINK_STROBE … /* true: connect status change */ #define PORT_CSC … /* true: port enable change */ #define PORT_PEC … /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port * into an enabled state, and the device into the default state. A "warm" reset * also resets the link, forcing the device through the link training sequence. * SW can also look at the Port Reset register to see when warm reset is done. */ #define PORT_WRC … /* true: over-current change */ #define PORT_OCC … /* true: reset change - 1 to 0 transition of PORT_RESET */ #define PORT_RC … /* port link status change - set on some port link state transitions: * Transition Reason * ------------------------------------------------------------------------------ * - U3 to Resume Wakeup signaling from a device * - Resume to Recovery to U0 USB 3.0 device resume * - Resume to U0 USB 2.0 device resume * - U3 to Recovery to U0 Software resume of USB 3.0 device complete * - U3 to U0 Software resume of USB 2.0 device complete * - U2 to U0 L1 resume of USB 2.1 device complete * - U0 to U0 (???) L1 entry rejection by USB 2.1 device * - U0 to disabled L1 entry error with USB 2.1 device * - Any state to inactive Error on USB 3.0 port */ #define PORT_PLC … /* port configure error change - port failed to configure its link partner */ #define PORT_CEC … #define PORT_CHANGE_MASK … /* Cold Attach Status - xHC can set this bit to report device attached during * Sx state. Warm port reset should be perfomed to clear this bit and move port * to connected state. */ #define PORT_CAS … /* wake on connect (enable) */ #define PORT_WKCONN_E … /* wake on disconnect (enable) */ #define PORT_WKDISC_E … /* wake on over-current (enable) */ #define PORT_WKOC_E … /* bits 28:29 reserved */ /* true: device is non-removable - for USB 3.0 roothub emulation */ #define PORT_DEV_REMOVE … /* Initiate a warm port reset - complete when PORT_WRC is '1' */ #define PORT_WR … /* We mark duplicate entries with -1 */ #define DUPLICATE_ENTRY … /* Port Power Management Status and Control - port_power_base bitmasks */ /* Inactivity timer value for transitions into U1, in microseconds. * Timeout can be up to 127us. 0xFF means an infinite timeout. */ #define PORT_U1_TIMEOUT(p) … #define PORT_U1_TIMEOUT_MASK … /* Inactivity timer value for transitions into U2 */ #define PORT_U2_TIMEOUT(p) … #define PORT_U2_TIMEOUT_MASK … /* Bits 24:31 for port testing */ /* USB2 Protocol PORTSPMSC */ #define PORT_L1S_MASK … #define PORT_L1S_SUCCESS … #define PORT_RWE … #define PORT_HIRD(p) … #define PORT_HIRD_MASK … #define PORT_L1DS_MASK … #define PORT_L1DS(p) … #define PORT_HLE … #define PORT_TEST_MODE_SHIFT … /* USB3 Protocol PORTLI Port Link Information */ #define PORT_RX_LANES(p) … #define PORT_TX_LANES(p) … /* USB2 Protocol PORTHLPMC */ #define PORT_HIRDM(p) … #define PORT_L1_TIMEOUT(p) … #define PORT_BESLD(p) … /* use 512 microseconds as USB2 LPM L1 default timeout. */ #define XHCI_L1_TIMEOUT … /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. * Safe to use with mixed HIRD and BESL systems (host and device) and is used * by other operating systems. * * XHCI 1.0 errata 8/14/12 Table 13 notes: * "Software should choose xHC BESL/BESLD field values that do not violate a * device's resume latency requirements, * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, * or not program values < '4' if BLC = '0' and a BESL device is attached. */ #define XHCI_DEFAULT_BESL … /* * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports * to complete link training. usually link trainig completes much faster * so check status 10 times with 36ms sleep in places we need to wait for * polling to complete. */ #define XHCI_PORT_POLLING_LFPS_TIME …
Codebase Browser
linux