/* SPDX-License-Identifier: GPL-2.0 */ /* hc_capbase bitmasks */ /* bits 7:0 - how long is the Capabilities register */ #define HC_LENGTH(p) … /* bits 31:16 */ #define HC_VERSION(p) … /* HCSPARAMS1 - hcs_params1 - bitmasks */ /* bits 0:7, Max Device Slots */ #define HCS_MAX_SLOTS(p) … #define HCS_SLOTS_MASK … /* bits 8:18, Max Interrupters */ #define HCS_MAX_INTRS(p) … /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ #define HCS_MAX_PORTS(p) … /* HCSPARAMS2 - hcs_params2 - bitmasks */ /* bits 0:3, frames or uframes that SW needs to queue transactions * ahead of the HW to meet periodic deadlines */ #define HCS_IST(p) … /* bits 4:7, max number of Event Ring segments */ #define HCS_ERST_MAX(p) … /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ #define HCS_MAX_SCRATCHPAD(p) … /* HCSPARAMS3 - hcs_params3 - bitmasks */ /* bits 0:7, Max U1 to U0 latency for the roothub ports */ #define HCS_U1_LATENCY(p) … /* bits 16:31, Max U2 to U0 latency for the roothub ports */ #define HCS_U2_LATENCY(p) … /* HCCPARAMS - hcc_params - bitmasks */ /* true: HC can use 64-bit address pointers */ #define HCC_64BIT_ADDR(p) … /* true: HC can do bandwidth negotiation */ #define HCC_BANDWIDTH_NEG(p) … /* true: HC uses 64-byte Device Context structures * FIXME 64-byte context structures aren't supported yet. */ #define HCC_64BYTE_CONTEXT(p) … /* true: HC has port power switches */ #define HCC_PPC(p) … /* true: HC has port indicators */ #define HCS_INDICATOR(p) … /* true: HC has Light HC Reset Capability */ #define HCC_LIGHT_RESET(p) … /* true: HC supports latency tolerance messaging */ #define HCC_LTC(p) … /* true: no secondary Stream ID Support */ #define HCC_NSS(p) … /* true: HC supports Stopped - Short Packet */ #define HCC_SPC(p) … /* true: HC has Contiguous Frame ID Capability */ #define HCC_CFC(p) … /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ #define HCC_MAX_PSA(p) … /* Extended Capabilities pointer from PCI base - section 5.3.6 */ #define HCC_EXT_CAPS(p) … #define CTX_SIZE(_hcc) … /* db_off bitmask - bits 0:1 reserved */ #define DBOFF_MASK … /* run_regs_off bitmask - bits 0:4 reserved */ #define RTSOFF_MASK … /* HCCPARAMS2 - hcc_params2 - bitmasks */ /* true: HC supports U3 entry Capability */ #define HCC2_U3C(p) … /* true: HC supports Configure endpoint command Max exit latency too large */ #define HCC2_CMC(p) … /* true: HC supports Force Save context Capability */ #define HCC2_FSC(p) … /* true: HC supports Compliance Transition Capability */ #define HCC2_CTC(p) … /* true: HC support Large ESIT payload Capability > 48k */ #define HCC2_LEC(p) … /* true: HC support Configuration Information Capability */ #define HCC2_CIC(p) … /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ #define HCC2_ETC(p) …
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