/* * Copyright (C) 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _mmhub_9_4_1_OFFSET_HEADER #define _mmhub_9_4_1_OFFSET_HEADER // addressBlock: mmhub_dagb_dagbdec0 // base address: 0x68000 #define mmDAGB0_RDCLI0 … #define mmDAGB0_RDCLI0_BASE_IDX … #define mmDAGB0_RDCLI1 … #define mmDAGB0_RDCLI1_BASE_IDX … #define mmDAGB0_RDCLI2 … #define mmDAGB0_RDCLI2_BASE_IDX … #define mmDAGB0_RDCLI3 … #define mmDAGB0_RDCLI3_BASE_IDX … #define mmDAGB0_RDCLI4 … #define mmDAGB0_RDCLI4_BASE_IDX … #define mmDAGB0_RDCLI5 … #define mmDAGB0_RDCLI5_BASE_IDX … #define mmDAGB0_RDCLI6 … #define mmDAGB0_RDCLI6_BASE_IDX … #define mmDAGB0_RDCLI7 … #define mmDAGB0_RDCLI7_BASE_IDX … #define mmDAGB0_RDCLI8 … #define mmDAGB0_RDCLI8_BASE_IDX … #define mmDAGB0_RDCLI9 … #define mmDAGB0_RDCLI9_BASE_IDX … #define mmDAGB0_RDCLI10 … #define mmDAGB0_RDCLI10_BASE_IDX … #define mmDAGB0_RDCLI11 … #define mmDAGB0_RDCLI11_BASE_IDX … #define mmDAGB0_RDCLI12 … #define mmDAGB0_RDCLI12_BASE_IDX … #define mmDAGB0_RDCLI13 … #define mmDAGB0_RDCLI13_BASE_IDX … #define mmDAGB0_RDCLI14 … #define mmDAGB0_RDCLI14_BASE_IDX … #define mmDAGB0_RDCLI15 … #define mmDAGB0_RDCLI15_BASE_IDX … #define mmDAGB0_RD_CNTL … #define mmDAGB0_RD_CNTL_BASE_IDX … #define mmDAGB0_RD_GMI_CNTL … #define mmDAGB0_RD_GMI_CNTL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB … #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_RD_CGTT_CLK_CTRL … #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_RD_VC0_CNTL … #define mmDAGB0_RD_VC0_CNTL_BASE_IDX … #define mmDAGB0_RD_VC1_CNTL … #define mmDAGB0_RD_VC1_CNTL_BASE_IDX … #define mmDAGB0_RD_VC2_CNTL … #define mmDAGB0_RD_VC2_CNTL_BASE_IDX … #define mmDAGB0_RD_VC3_CNTL … #define mmDAGB0_RD_VC3_CNTL_BASE_IDX … #define mmDAGB0_RD_VC4_CNTL … #define mmDAGB0_RD_VC4_CNTL_BASE_IDX … #define mmDAGB0_RD_VC5_CNTL … #define mmDAGB0_RD_VC5_CNTL_BASE_IDX … #define mmDAGB0_RD_VC6_CNTL … #define mmDAGB0_RD_VC6_CNTL_BASE_IDX … #define mmDAGB0_RD_VC7_CNTL … #define mmDAGB0_RD_VC7_CNTL_BASE_IDX … #define mmDAGB0_RD_CNTL_MISC … #define mmDAGB0_RD_CNTL_MISC_BASE_IDX … #define mmDAGB0_RD_TLB_CREDIT … #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB0_RDCLI_ASK_PENDING … #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GO_PENDING … #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GBLSEND_PENDING … #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_TLB_PENDING … #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OARB_PENDING … #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OSD_PENDING … #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI0 … #define mmDAGB0_WRCLI0_BASE_IDX … #define mmDAGB0_WRCLI1 … #define mmDAGB0_WRCLI1_BASE_IDX … #define mmDAGB0_WRCLI2 … #define mmDAGB0_WRCLI2_BASE_IDX … #define mmDAGB0_WRCLI3 … #define mmDAGB0_WRCLI3_BASE_IDX … #define mmDAGB0_WRCLI4 … #define mmDAGB0_WRCLI4_BASE_IDX … #define mmDAGB0_WRCLI5 … #define mmDAGB0_WRCLI5_BASE_IDX … #define mmDAGB0_WRCLI6 … #define mmDAGB0_WRCLI6_BASE_IDX … #define mmDAGB0_WRCLI7 … #define mmDAGB0_WRCLI7_BASE_IDX … #define mmDAGB0_WRCLI8 … #define mmDAGB0_WRCLI8_BASE_IDX … #define mmDAGB0_WRCLI9 … #define mmDAGB0_WRCLI9_BASE_IDX … #define mmDAGB0_WRCLI10 … #define mmDAGB0_WRCLI10_BASE_IDX … #define mmDAGB0_WRCLI11 … #define mmDAGB0_WRCLI11_BASE_IDX … #define mmDAGB0_WRCLI12 … #define mmDAGB0_WRCLI12_BASE_IDX … #define mmDAGB0_WRCLI13 … #define mmDAGB0_WRCLI13_BASE_IDX … #define mmDAGB0_WRCLI14 … #define mmDAGB0_WRCLI14_BASE_IDX … #define mmDAGB0_WRCLI15 … #define mmDAGB0_WRCLI15_BASE_IDX … #define mmDAGB0_WR_CNTL … #define mmDAGB0_WR_CNTL_BASE_IDX … #define mmDAGB0_WR_GMI_CNTL … #define mmDAGB0_WR_GMI_CNTL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB … #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_WR_CGTT_CLK_CTRL … #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB … #define mmDAGB0_WR_DATA_DAGB_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_VC0_CNTL … #define mmDAGB0_WR_VC0_CNTL_BASE_IDX … #define mmDAGB0_WR_VC1_CNTL … #define mmDAGB0_WR_VC1_CNTL_BASE_IDX … #define mmDAGB0_WR_VC2_CNTL … #define mmDAGB0_WR_VC2_CNTL_BASE_IDX … #define mmDAGB0_WR_VC3_CNTL … #define mmDAGB0_WR_VC3_CNTL_BASE_IDX … #define mmDAGB0_WR_VC4_CNTL … #define mmDAGB0_WR_VC4_CNTL_BASE_IDX … #define mmDAGB0_WR_VC5_CNTL … #define mmDAGB0_WR_VC5_CNTL_BASE_IDX … #define mmDAGB0_WR_VC6_CNTL … #define mmDAGB0_WR_VC6_CNTL_BASE_IDX … #define mmDAGB0_WR_VC7_CNTL … #define mmDAGB0_WR_VC7_CNTL_BASE_IDX … #define mmDAGB0_WR_CNTL_MISC … #define mmDAGB0_WR_CNTL_MISC_BASE_IDX … #define mmDAGB0_WR_TLB_CREDIT … #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB0_WR_DATA_CREDIT … #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB0_WR_MISC_CREDIT … #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB0_WRCLI_ASK_PENDING … #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GO_PENDING … #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GBLSEND_PENDING … #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_TLB_PENDING … #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OARB_PENDING … #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OSD_PENDING … #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_GO_PENDING … #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB0_DAGB_DLY … #define mmDAGB0_DAGB_DLY_BASE_IDX … #define mmDAGB0_CNTL_MISC … #define mmDAGB0_CNTL_MISC_BASE_IDX … #define mmDAGB0_CNTL_MISC2 … #define mmDAGB0_CNTL_MISC2_BASE_IDX … #define mmDAGB0_FIFO_EMPTY … #define mmDAGB0_FIFO_EMPTY_BASE_IDX … #define mmDAGB0_FIFO_FULL … #define mmDAGB0_FIFO_FULL_BASE_IDX … #define mmDAGB0_WR_CREDITS_FULL … #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB0_RD_CREDITS_FULL … #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB0_PERFCOUNTER_LO … #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB0_PERFCOUNTER_HI … #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB0_PERFCOUNTER0_CFG … #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER1_CFG … #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER2_CFG … #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB0_RESERVE0 … #define mmDAGB0_RESERVE0_BASE_IDX … #define mmDAGB0_RESERVE1 … #define mmDAGB0_RESERVE1_BASE_IDX … #define mmDAGB0_RESERVE2 … #define mmDAGB0_RESERVE2_BASE_IDX … #define mmDAGB0_RESERVE3 … #define mmDAGB0_RESERVE3_BASE_IDX … #define mmDAGB0_RESERVE4 … #define mmDAGB0_RESERVE4_BASE_IDX … #define mmDAGB0_RESERVE5 … #define mmDAGB0_RESERVE5_BASE_IDX … #define mmDAGB0_RESERVE6 … #define mmDAGB0_RESERVE6_BASE_IDX … #define mmDAGB0_RESERVE7 … #define mmDAGB0_RESERVE7_BASE_IDX … #define mmDAGB0_RESERVE8 … #define mmDAGB0_RESERVE8_BASE_IDX … #define mmDAGB0_RESERVE9 … #define mmDAGB0_RESERVE9_BASE_IDX … #define mmDAGB0_RESERVE10 … #define mmDAGB0_RESERVE10_BASE_IDX … #define mmDAGB0_RESERVE11 … #define mmDAGB0_RESERVE11_BASE_IDX … #define mmDAGB0_RESERVE12 … #define mmDAGB0_RESERVE12_BASE_IDX … #define mmDAGB0_RESERVE13 … #define mmDAGB0_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec1 // base address: 0x68200 #define mmDAGB1_RDCLI0 … #define mmDAGB1_RDCLI0_BASE_IDX … #define mmDAGB1_RDCLI1 … #define mmDAGB1_RDCLI1_BASE_IDX … #define mmDAGB1_RDCLI2 … #define mmDAGB1_RDCLI2_BASE_IDX … #define mmDAGB1_RDCLI3 … #define mmDAGB1_RDCLI3_BASE_IDX … #define mmDAGB1_RDCLI4 … #define mmDAGB1_RDCLI4_BASE_IDX … #define mmDAGB1_RDCLI5 … #define mmDAGB1_RDCLI5_BASE_IDX … #define mmDAGB1_RDCLI6 … #define mmDAGB1_RDCLI6_BASE_IDX … #define mmDAGB1_RDCLI7 … #define mmDAGB1_RDCLI7_BASE_IDX … #define mmDAGB1_RDCLI8 … #define mmDAGB1_RDCLI8_BASE_IDX … #define mmDAGB1_RDCLI9 … #define mmDAGB1_RDCLI9_BASE_IDX … #define mmDAGB1_RDCLI10 … #define mmDAGB1_RDCLI10_BASE_IDX … #define mmDAGB1_RDCLI11 … #define mmDAGB1_RDCLI11_BASE_IDX … #define mmDAGB1_RDCLI12 … #define mmDAGB1_RDCLI12_BASE_IDX … #define mmDAGB1_RDCLI13 … #define mmDAGB1_RDCLI13_BASE_IDX … #define mmDAGB1_RDCLI14 … #define mmDAGB1_RDCLI14_BASE_IDX … #define mmDAGB1_RDCLI15 … #define mmDAGB1_RDCLI15_BASE_IDX … #define mmDAGB1_RD_CNTL … #define mmDAGB1_RD_CNTL_BASE_IDX … #define mmDAGB1_RD_GMI_CNTL … #define mmDAGB1_RD_GMI_CNTL_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB … #define mmDAGB1_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB1_RD_CGTT_CLK_CTRL … #define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_RD_VC0_CNTL … #define mmDAGB1_RD_VC0_CNTL_BASE_IDX … #define mmDAGB1_RD_VC1_CNTL … #define mmDAGB1_RD_VC1_CNTL_BASE_IDX … #define mmDAGB1_RD_VC2_CNTL … #define mmDAGB1_RD_VC2_CNTL_BASE_IDX … #define mmDAGB1_RD_VC3_CNTL … #define mmDAGB1_RD_VC3_CNTL_BASE_IDX … #define mmDAGB1_RD_VC4_CNTL … #define mmDAGB1_RD_VC4_CNTL_BASE_IDX … #define mmDAGB1_RD_VC5_CNTL … #define mmDAGB1_RD_VC5_CNTL_BASE_IDX … #define mmDAGB1_RD_VC6_CNTL … #define mmDAGB1_RD_VC6_CNTL_BASE_IDX … #define mmDAGB1_RD_VC7_CNTL … #define mmDAGB1_RD_VC7_CNTL_BASE_IDX … #define mmDAGB1_RD_CNTL_MISC … #define mmDAGB1_RD_CNTL_MISC_BASE_IDX … #define mmDAGB1_RD_TLB_CREDIT … #define mmDAGB1_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB1_RDCLI_ASK_PENDING … #define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_GO_PENDING … #define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_GBLSEND_PENDING … #define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_TLB_PENDING … #define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_OARB_PENDING … #define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB1_RDCLI_OSD_PENDING … #define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB1_WRCLI0 … #define mmDAGB1_WRCLI0_BASE_IDX … #define mmDAGB1_WRCLI1 … #define mmDAGB1_WRCLI1_BASE_IDX … #define mmDAGB1_WRCLI2 … #define mmDAGB1_WRCLI2_BASE_IDX … #define mmDAGB1_WRCLI3 … #define mmDAGB1_WRCLI3_BASE_IDX … #define mmDAGB1_WRCLI4 … #define mmDAGB1_WRCLI4_BASE_IDX … #define mmDAGB1_WRCLI5 … #define mmDAGB1_WRCLI5_BASE_IDX … #define mmDAGB1_WRCLI6 … #define mmDAGB1_WRCLI6_BASE_IDX … #define mmDAGB1_WRCLI7 … #define mmDAGB1_WRCLI7_BASE_IDX … #define mmDAGB1_WRCLI8 … #define mmDAGB1_WRCLI8_BASE_IDX … #define mmDAGB1_WRCLI9 … #define mmDAGB1_WRCLI9_BASE_IDX … #define mmDAGB1_WRCLI10 … #define mmDAGB1_WRCLI10_BASE_IDX … #define mmDAGB1_WRCLI11 … #define mmDAGB1_WRCLI11_BASE_IDX … #define mmDAGB1_WRCLI12 … #define mmDAGB1_WRCLI12_BASE_IDX … #define mmDAGB1_WRCLI13 … #define mmDAGB1_WRCLI13_BASE_IDX … #define mmDAGB1_WRCLI14 … #define mmDAGB1_WRCLI14_BASE_IDX … #define mmDAGB1_WRCLI15 … #define mmDAGB1_WRCLI15_BASE_IDX … #define mmDAGB1_WR_CNTL … #define mmDAGB1_WR_CNTL_BASE_IDX … #define mmDAGB1_WR_GMI_CNTL … #define mmDAGB1_WR_GMI_CNTL_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB … #define mmDAGB1_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB1_WR_CGTT_CLK_CTRL … #define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB … #define mmDAGB1_WR_DATA_DAGB_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB1_WR_VC0_CNTL … #define mmDAGB1_WR_VC0_CNTL_BASE_IDX … #define mmDAGB1_WR_VC1_CNTL … #define mmDAGB1_WR_VC1_CNTL_BASE_IDX … #define mmDAGB1_WR_VC2_CNTL … #define mmDAGB1_WR_VC2_CNTL_BASE_IDX … #define mmDAGB1_WR_VC3_CNTL … #define mmDAGB1_WR_VC3_CNTL_BASE_IDX … #define mmDAGB1_WR_VC4_CNTL … #define mmDAGB1_WR_VC4_CNTL_BASE_IDX … #define mmDAGB1_WR_VC5_CNTL … #define mmDAGB1_WR_VC5_CNTL_BASE_IDX … #define mmDAGB1_WR_VC6_CNTL … #define mmDAGB1_WR_VC6_CNTL_BASE_IDX … #define mmDAGB1_WR_VC7_CNTL … #define mmDAGB1_WR_VC7_CNTL_BASE_IDX … #define mmDAGB1_WR_CNTL_MISC … #define mmDAGB1_WR_CNTL_MISC_BASE_IDX … #define mmDAGB1_WR_TLB_CREDIT … #define mmDAGB1_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB1_WR_DATA_CREDIT … #define mmDAGB1_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB1_WR_MISC_CREDIT … #define mmDAGB1_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB1_WRCLI_ASK_PENDING … #define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_GO_PENDING … #define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_GBLSEND_PENDING … #define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_TLB_PENDING … #define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_OARB_PENDING … #define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_OSD_PENDING … #define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_DBUS_ASK_PENDING … #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB1_WRCLI_DBUS_GO_PENDING … #define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB1_DAGB_DLY … #define mmDAGB1_DAGB_DLY_BASE_IDX … #define mmDAGB1_CNTL_MISC … #define mmDAGB1_CNTL_MISC_BASE_IDX … #define mmDAGB1_CNTL_MISC2 … #define mmDAGB1_CNTL_MISC2_BASE_IDX … #define mmDAGB1_FIFO_EMPTY … #define mmDAGB1_FIFO_EMPTY_BASE_IDX … #define mmDAGB1_FIFO_FULL … #define mmDAGB1_FIFO_FULL_BASE_IDX … #define mmDAGB1_WR_CREDITS_FULL … #define mmDAGB1_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB1_RD_CREDITS_FULL … #define mmDAGB1_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB1_PERFCOUNTER_LO … #define mmDAGB1_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB1_PERFCOUNTER_HI … #define mmDAGB1_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB1_PERFCOUNTER0_CFG … #define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER1_CFG … #define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER2_CFG … #define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB1_PERFCOUNTER_RSLT_CNTL … #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB1_RESERVE0 … #define mmDAGB1_RESERVE0_BASE_IDX … #define mmDAGB1_RESERVE1 … #define mmDAGB1_RESERVE1_BASE_IDX … #define mmDAGB1_RESERVE2 … #define mmDAGB1_RESERVE2_BASE_IDX … #define mmDAGB1_RESERVE3 … #define mmDAGB1_RESERVE3_BASE_IDX … #define mmDAGB1_RESERVE4 … #define mmDAGB1_RESERVE4_BASE_IDX … #define mmDAGB1_RESERVE5 … #define mmDAGB1_RESERVE5_BASE_IDX … #define mmDAGB1_RESERVE6 … #define mmDAGB1_RESERVE6_BASE_IDX … #define mmDAGB1_RESERVE7 … #define mmDAGB1_RESERVE7_BASE_IDX … #define mmDAGB1_RESERVE8 … #define mmDAGB1_RESERVE8_BASE_IDX … #define mmDAGB1_RESERVE9 … #define mmDAGB1_RESERVE9_BASE_IDX … #define mmDAGB1_RESERVE10 … #define mmDAGB1_RESERVE10_BASE_IDX … #define mmDAGB1_RESERVE11 … #define mmDAGB1_RESERVE11_BASE_IDX … #define mmDAGB1_RESERVE12 … #define mmDAGB1_RESERVE12_BASE_IDX … #define mmDAGB1_RESERVE13 … #define mmDAGB1_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec2 // base address: 0x68400 #define mmDAGB2_RDCLI0 … #define mmDAGB2_RDCLI0_BASE_IDX … #define mmDAGB2_RDCLI1 … #define mmDAGB2_RDCLI1_BASE_IDX … #define mmDAGB2_RDCLI2 … #define mmDAGB2_RDCLI2_BASE_IDX … #define mmDAGB2_RDCLI3 … #define mmDAGB2_RDCLI3_BASE_IDX … #define mmDAGB2_RDCLI4 … #define mmDAGB2_RDCLI4_BASE_IDX … #define mmDAGB2_RDCLI5 … #define mmDAGB2_RDCLI5_BASE_IDX … #define mmDAGB2_RDCLI6 … #define mmDAGB2_RDCLI6_BASE_IDX … #define mmDAGB2_RDCLI7 … #define mmDAGB2_RDCLI7_BASE_IDX … #define mmDAGB2_RDCLI8 … #define mmDAGB2_RDCLI8_BASE_IDX … #define mmDAGB2_RDCLI9 … #define mmDAGB2_RDCLI9_BASE_IDX … #define mmDAGB2_RDCLI10 … #define mmDAGB2_RDCLI10_BASE_IDX … #define mmDAGB2_RDCLI11 … #define mmDAGB2_RDCLI11_BASE_IDX … #define mmDAGB2_RDCLI12 … #define mmDAGB2_RDCLI12_BASE_IDX … #define mmDAGB2_RDCLI13 … #define mmDAGB2_RDCLI13_BASE_IDX … #define mmDAGB2_RDCLI14 … #define mmDAGB2_RDCLI14_BASE_IDX … #define mmDAGB2_RDCLI15 … #define mmDAGB2_RDCLI15_BASE_IDX … #define mmDAGB2_RD_CNTL … #define mmDAGB2_RD_CNTL_BASE_IDX … #define mmDAGB2_RD_GMI_CNTL … #define mmDAGB2_RD_GMI_CNTL_BASE_IDX … #define mmDAGB2_RD_ADDR_DAGB … #define mmDAGB2_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB2_RD_CGTT_CLK_CTRL … #define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB2_RD_VC0_CNTL … #define mmDAGB2_RD_VC0_CNTL_BASE_IDX … #define mmDAGB2_RD_VC1_CNTL … #define mmDAGB2_RD_VC1_CNTL_BASE_IDX … #define mmDAGB2_RD_VC2_CNTL … #define mmDAGB2_RD_VC2_CNTL_BASE_IDX … #define mmDAGB2_RD_VC3_CNTL … #define mmDAGB2_RD_VC3_CNTL_BASE_IDX … #define mmDAGB2_RD_VC4_CNTL … #define mmDAGB2_RD_VC4_CNTL_BASE_IDX … #define mmDAGB2_RD_VC5_CNTL … #define mmDAGB2_RD_VC5_CNTL_BASE_IDX … #define mmDAGB2_RD_VC6_CNTL … #define mmDAGB2_RD_VC6_CNTL_BASE_IDX … #define mmDAGB2_RD_VC7_CNTL … #define mmDAGB2_RD_VC7_CNTL_BASE_IDX … #define mmDAGB2_RD_CNTL_MISC … #define mmDAGB2_RD_CNTL_MISC_BASE_IDX … #define mmDAGB2_RD_TLB_CREDIT … #define mmDAGB2_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB2_RDCLI_ASK_PENDING … #define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB2_RDCLI_GO_PENDING … #define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB2_RDCLI_GBLSEND_PENDING … #define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB2_RDCLI_TLB_PENDING … #define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB2_RDCLI_OARB_PENDING … #define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB2_RDCLI_OSD_PENDING … #define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB2_WRCLI0 … #define mmDAGB2_WRCLI0_BASE_IDX … #define mmDAGB2_WRCLI1 … #define mmDAGB2_WRCLI1_BASE_IDX … #define mmDAGB2_WRCLI2 … #define mmDAGB2_WRCLI2_BASE_IDX … #define mmDAGB2_WRCLI3 … #define mmDAGB2_WRCLI3_BASE_IDX … #define mmDAGB2_WRCLI4 … #define mmDAGB2_WRCLI4_BASE_IDX … #define mmDAGB2_WRCLI5 … #define mmDAGB2_WRCLI5_BASE_IDX … #define mmDAGB2_WRCLI6 … #define mmDAGB2_WRCLI6_BASE_IDX … #define mmDAGB2_WRCLI7 … #define mmDAGB2_WRCLI7_BASE_IDX … #define mmDAGB2_WRCLI8 … #define mmDAGB2_WRCLI8_BASE_IDX … #define mmDAGB2_WRCLI9 … #define mmDAGB2_WRCLI9_BASE_IDX … #define mmDAGB2_WRCLI10 … #define mmDAGB2_WRCLI10_BASE_IDX … #define mmDAGB2_WRCLI11 … #define mmDAGB2_WRCLI11_BASE_IDX … #define mmDAGB2_WRCLI12 … #define mmDAGB2_WRCLI12_BASE_IDX … #define mmDAGB2_WRCLI13 … #define mmDAGB2_WRCLI13_BASE_IDX … #define mmDAGB2_WRCLI14 … #define mmDAGB2_WRCLI14_BASE_IDX … #define mmDAGB2_WRCLI15 … #define mmDAGB2_WRCLI15_BASE_IDX … #define mmDAGB2_WR_CNTL … #define mmDAGB2_WR_CNTL_BASE_IDX … #define mmDAGB2_WR_GMI_CNTL … #define mmDAGB2_WR_GMI_CNTL_BASE_IDX … #define mmDAGB2_WR_ADDR_DAGB … #define mmDAGB2_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB2_WR_CGTT_CLK_CTRL … #define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB2_WR_DATA_DAGB … #define mmDAGB2_WR_DATA_DAGB_BASE_IDX … #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB2_WR_VC0_CNTL … #define mmDAGB2_WR_VC0_CNTL_BASE_IDX … #define mmDAGB2_WR_VC1_CNTL … #define mmDAGB2_WR_VC1_CNTL_BASE_IDX … #define mmDAGB2_WR_VC2_CNTL … #define mmDAGB2_WR_VC2_CNTL_BASE_IDX … #define mmDAGB2_WR_VC3_CNTL … #define mmDAGB2_WR_VC3_CNTL_BASE_IDX … #define mmDAGB2_WR_VC4_CNTL … #define mmDAGB2_WR_VC4_CNTL_BASE_IDX … #define mmDAGB2_WR_VC5_CNTL … #define mmDAGB2_WR_VC5_CNTL_BASE_IDX … #define mmDAGB2_WR_VC6_CNTL … #define mmDAGB2_WR_VC6_CNTL_BASE_IDX … #define mmDAGB2_WR_VC7_CNTL … #define mmDAGB2_WR_VC7_CNTL_BASE_IDX … #define mmDAGB2_WR_CNTL_MISC … #define mmDAGB2_WR_CNTL_MISC_BASE_IDX … #define mmDAGB2_WR_TLB_CREDIT … #define mmDAGB2_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB2_WR_DATA_CREDIT … #define mmDAGB2_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB2_WR_MISC_CREDIT … #define mmDAGB2_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB2_WRCLI_ASK_PENDING … #define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_GO_PENDING … #define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_GBLSEND_PENDING … #define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_TLB_PENDING … #define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_OARB_PENDING … #define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_OSD_PENDING … #define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_DBUS_ASK_PENDING … #define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB2_WRCLI_DBUS_GO_PENDING … #define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB2_DAGB_DLY … #define mmDAGB2_DAGB_DLY_BASE_IDX … #define mmDAGB2_CNTL_MISC … #define mmDAGB2_CNTL_MISC_BASE_IDX … #define mmDAGB2_CNTL_MISC2 … #define mmDAGB2_CNTL_MISC2_BASE_IDX … #define mmDAGB2_FIFO_EMPTY … #define mmDAGB2_FIFO_EMPTY_BASE_IDX … #define mmDAGB2_FIFO_FULL … #define mmDAGB2_FIFO_FULL_BASE_IDX … #define mmDAGB2_WR_CREDITS_FULL … #define mmDAGB2_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB2_RD_CREDITS_FULL … #define mmDAGB2_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB2_PERFCOUNTER_LO … #define mmDAGB2_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB2_PERFCOUNTER_HI … #define mmDAGB2_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB2_PERFCOUNTER0_CFG … #define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB2_PERFCOUNTER1_CFG … #define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB2_PERFCOUNTER2_CFG … #define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB2_PERFCOUNTER_RSLT_CNTL … #define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB2_RESERVE0 … #define mmDAGB2_RESERVE0_BASE_IDX … #define mmDAGB2_RESERVE1 … #define mmDAGB2_RESERVE1_BASE_IDX … #define mmDAGB2_RESERVE2 … #define mmDAGB2_RESERVE2_BASE_IDX … #define mmDAGB2_RESERVE3 … #define mmDAGB2_RESERVE3_BASE_IDX … #define mmDAGB2_RESERVE4 … #define mmDAGB2_RESERVE4_BASE_IDX … #define mmDAGB2_RESERVE5 … #define mmDAGB2_RESERVE5_BASE_IDX … #define mmDAGB2_RESERVE6 … #define mmDAGB2_RESERVE6_BASE_IDX … #define mmDAGB2_RESERVE7 … #define mmDAGB2_RESERVE7_BASE_IDX … #define mmDAGB2_RESERVE8 … #define mmDAGB2_RESERVE8_BASE_IDX … #define mmDAGB2_RESERVE9 … #define mmDAGB2_RESERVE9_BASE_IDX … #define mmDAGB2_RESERVE10 … #define mmDAGB2_RESERVE10_BASE_IDX … #define mmDAGB2_RESERVE11 … #define mmDAGB2_RESERVE11_BASE_IDX … #define mmDAGB2_RESERVE12 … #define mmDAGB2_RESERVE12_BASE_IDX … #define mmDAGB2_RESERVE13 … #define mmDAGB2_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec3 // base address: 0x68600 #define mmDAGB3_RDCLI0 … #define mmDAGB3_RDCLI0_BASE_IDX … #define mmDAGB3_RDCLI1 … #define mmDAGB3_RDCLI1_BASE_IDX … #define mmDAGB3_RDCLI2 … #define mmDAGB3_RDCLI2_BASE_IDX … #define mmDAGB3_RDCLI3 … #define mmDAGB3_RDCLI3_BASE_IDX … #define mmDAGB3_RDCLI4 … #define mmDAGB3_RDCLI4_BASE_IDX … #define mmDAGB3_RDCLI5 … #define mmDAGB3_RDCLI5_BASE_IDX … #define mmDAGB3_RDCLI6 … #define mmDAGB3_RDCLI6_BASE_IDX … #define mmDAGB3_RDCLI7 … #define mmDAGB3_RDCLI7_BASE_IDX … #define mmDAGB3_RDCLI8 … #define mmDAGB3_RDCLI8_BASE_IDX … #define mmDAGB3_RDCLI9 … #define mmDAGB3_RDCLI9_BASE_IDX … #define mmDAGB3_RDCLI10 … #define mmDAGB3_RDCLI10_BASE_IDX … #define mmDAGB3_RDCLI11 … #define mmDAGB3_RDCLI11_BASE_IDX … #define mmDAGB3_RDCLI12 … #define mmDAGB3_RDCLI12_BASE_IDX … #define mmDAGB3_RDCLI13 … #define mmDAGB3_RDCLI13_BASE_IDX … #define mmDAGB3_RDCLI14 … #define mmDAGB3_RDCLI14_BASE_IDX … #define mmDAGB3_RDCLI15 … #define mmDAGB3_RDCLI15_BASE_IDX … #define mmDAGB3_RD_CNTL … #define mmDAGB3_RD_CNTL_BASE_IDX … #define mmDAGB3_RD_GMI_CNTL … #define mmDAGB3_RD_GMI_CNTL_BASE_IDX … #define mmDAGB3_RD_ADDR_DAGB … #define mmDAGB3_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB3_RD_CGTT_CLK_CTRL … #define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB3_RD_VC0_CNTL … #define mmDAGB3_RD_VC0_CNTL_BASE_IDX … #define mmDAGB3_RD_VC1_CNTL … #define mmDAGB3_RD_VC1_CNTL_BASE_IDX … #define mmDAGB3_RD_VC2_CNTL … #define mmDAGB3_RD_VC2_CNTL_BASE_IDX … #define mmDAGB3_RD_VC3_CNTL … #define mmDAGB3_RD_VC3_CNTL_BASE_IDX … #define mmDAGB3_RD_VC4_CNTL … #define mmDAGB3_RD_VC4_CNTL_BASE_IDX … #define mmDAGB3_RD_VC5_CNTL … #define mmDAGB3_RD_VC5_CNTL_BASE_IDX … #define mmDAGB3_RD_VC6_CNTL … #define mmDAGB3_RD_VC6_CNTL_BASE_IDX … #define mmDAGB3_RD_VC7_CNTL … #define mmDAGB3_RD_VC7_CNTL_BASE_IDX … #define mmDAGB3_RD_CNTL_MISC … #define mmDAGB3_RD_CNTL_MISC_BASE_IDX … #define mmDAGB3_RD_TLB_CREDIT … #define mmDAGB3_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB3_RDCLI_ASK_PENDING … #define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB3_RDCLI_GO_PENDING … #define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB3_RDCLI_GBLSEND_PENDING … #define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB3_RDCLI_TLB_PENDING … #define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB3_RDCLI_OARB_PENDING … #define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB3_RDCLI_OSD_PENDING … #define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB3_WRCLI0 … #define mmDAGB3_WRCLI0_BASE_IDX … #define mmDAGB3_WRCLI1 … #define mmDAGB3_WRCLI1_BASE_IDX … #define mmDAGB3_WRCLI2 … #define mmDAGB3_WRCLI2_BASE_IDX … #define mmDAGB3_WRCLI3 … #define mmDAGB3_WRCLI3_BASE_IDX … #define mmDAGB3_WRCLI4 … #define mmDAGB3_WRCLI4_BASE_IDX … #define mmDAGB3_WRCLI5 … #define mmDAGB3_WRCLI5_BASE_IDX … #define mmDAGB3_WRCLI6 … #define mmDAGB3_WRCLI6_BASE_IDX … #define mmDAGB3_WRCLI7 … #define mmDAGB3_WRCLI7_BASE_IDX … #define mmDAGB3_WRCLI8 … #define mmDAGB3_WRCLI8_BASE_IDX … #define mmDAGB3_WRCLI9 … #define mmDAGB3_WRCLI9_BASE_IDX … #define mmDAGB3_WRCLI10 … #define mmDAGB3_WRCLI10_BASE_IDX … #define mmDAGB3_WRCLI11 … #define mmDAGB3_WRCLI11_BASE_IDX … #define mmDAGB3_WRCLI12 … #define mmDAGB3_WRCLI12_BASE_IDX … #define mmDAGB3_WRCLI13 … #define mmDAGB3_WRCLI13_BASE_IDX … #define mmDAGB3_WRCLI14 … #define mmDAGB3_WRCLI14_BASE_IDX … #define mmDAGB3_WRCLI15 … #define mmDAGB3_WRCLI15_BASE_IDX … #define mmDAGB3_WR_CNTL … #define mmDAGB3_WR_CNTL_BASE_IDX … #define mmDAGB3_WR_GMI_CNTL … #define mmDAGB3_WR_GMI_CNTL_BASE_IDX … #define mmDAGB3_WR_ADDR_DAGB … #define mmDAGB3_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB3_WR_CGTT_CLK_CTRL … #define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB3_WR_DATA_DAGB … #define mmDAGB3_WR_DATA_DAGB_BASE_IDX … #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB3_WR_VC0_CNTL … #define mmDAGB3_WR_VC0_CNTL_BASE_IDX … #define mmDAGB3_WR_VC1_CNTL … #define mmDAGB3_WR_VC1_CNTL_BASE_IDX … #define mmDAGB3_WR_VC2_CNTL … #define mmDAGB3_WR_VC2_CNTL_BASE_IDX … #define mmDAGB3_WR_VC3_CNTL … #define mmDAGB3_WR_VC3_CNTL_BASE_IDX … #define mmDAGB3_WR_VC4_CNTL … #define mmDAGB3_WR_VC4_CNTL_BASE_IDX … #define mmDAGB3_WR_VC5_CNTL … #define mmDAGB3_WR_VC5_CNTL_BASE_IDX … #define mmDAGB3_WR_VC6_CNTL … #define mmDAGB3_WR_VC6_CNTL_BASE_IDX … #define mmDAGB3_WR_VC7_CNTL … #define mmDAGB3_WR_VC7_CNTL_BASE_IDX … #define mmDAGB3_WR_CNTL_MISC … #define mmDAGB3_WR_CNTL_MISC_BASE_IDX … #define mmDAGB3_WR_TLB_CREDIT … #define mmDAGB3_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB3_WR_DATA_CREDIT … #define mmDAGB3_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB3_WR_MISC_CREDIT … #define mmDAGB3_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB3_WRCLI_ASK_PENDING … #define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_GO_PENDING … #define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_GBLSEND_PENDING … #define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_TLB_PENDING … #define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_OARB_PENDING … #define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_OSD_PENDING … #define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_DBUS_ASK_PENDING … #define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB3_WRCLI_DBUS_GO_PENDING … #define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB3_DAGB_DLY … #define mmDAGB3_DAGB_DLY_BASE_IDX … #define mmDAGB3_CNTL_MISC … #define mmDAGB3_CNTL_MISC_BASE_IDX … #define mmDAGB3_CNTL_MISC2 … #define mmDAGB3_CNTL_MISC2_BASE_IDX … #define mmDAGB3_FIFO_EMPTY … #define mmDAGB3_FIFO_EMPTY_BASE_IDX … #define mmDAGB3_FIFO_FULL … #define mmDAGB3_FIFO_FULL_BASE_IDX … #define mmDAGB3_WR_CREDITS_FULL … #define mmDAGB3_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB3_RD_CREDITS_FULL … #define mmDAGB3_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB3_PERFCOUNTER_LO … #define mmDAGB3_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB3_PERFCOUNTER_HI … #define mmDAGB3_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB3_PERFCOUNTER0_CFG … #define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB3_PERFCOUNTER1_CFG … #define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB3_PERFCOUNTER2_CFG … #define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB3_PERFCOUNTER_RSLT_CNTL … #define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB3_RESERVE0 … #define mmDAGB3_RESERVE0_BASE_IDX … #define mmDAGB3_RESERVE1 … #define mmDAGB3_RESERVE1_BASE_IDX … #define mmDAGB3_RESERVE2 … #define mmDAGB3_RESERVE2_BASE_IDX … #define mmDAGB3_RESERVE3 … #define mmDAGB3_RESERVE3_BASE_IDX … #define mmDAGB3_RESERVE4 … #define mmDAGB3_RESERVE4_BASE_IDX … #define mmDAGB3_RESERVE5 … #define mmDAGB3_RESERVE5_BASE_IDX … #define mmDAGB3_RESERVE6 … #define mmDAGB3_RESERVE6_BASE_IDX … #define mmDAGB3_RESERVE7 … #define mmDAGB3_RESERVE7_BASE_IDX … #define mmDAGB3_RESERVE8 … #define mmDAGB3_RESERVE8_BASE_IDX … #define mmDAGB3_RESERVE9 … #define mmDAGB3_RESERVE9_BASE_IDX … #define mmDAGB3_RESERVE10 … #define mmDAGB3_RESERVE10_BASE_IDX … #define mmDAGB3_RESERVE11 … #define mmDAGB3_RESERVE11_BASE_IDX … #define mmDAGB3_RESERVE12 … #define mmDAGB3_RESERVE12_BASE_IDX … #define mmDAGB3_RESERVE13 … #define mmDAGB3_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec4 // base address: 0x68800 #define mmDAGB4_RDCLI0 … #define mmDAGB4_RDCLI0_BASE_IDX … #define mmDAGB4_RDCLI1 … #define mmDAGB4_RDCLI1_BASE_IDX … #define mmDAGB4_RDCLI2 … #define mmDAGB4_RDCLI2_BASE_IDX … #define mmDAGB4_RDCLI3 … #define mmDAGB4_RDCLI3_BASE_IDX … #define mmDAGB4_RDCLI4 … #define mmDAGB4_RDCLI4_BASE_IDX … #define mmDAGB4_RDCLI5 … #define mmDAGB4_RDCLI5_BASE_IDX … #define mmDAGB4_RDCLI6 … #define mmDAGB4_RDCLI6_BASE_IDX … #define mmDAGB4_RDCLI7 … #define mmDAGB4_RDCLI7_BASE_IDX … #define mmDAGB4_RDCLI8 … #define mmDAGB4_RDCLI8_BASE_IDX … #define mmDAGB4_RDCLI9 … #define mmDAGB4_RDCLI9_BASE_IDX … #define mmDAGB4_RDCLI10 … #define mmDAGB4_RDCLI10_BASE_IDX … #define mmDAGB4_RDCLI11 … #define mmDAGB4_RDCLI11_BASE_IDX … #define mmDAGB4_RDCLI12 … #define mmDAGB4_RDCLI12_BASE_IDX … #define mmDAGB4_RDCLI13 … #define mmDAGB4_RDCLI13_BASE_IDX … #define mmDAGB4_RDCLI14 … #define mmDAGB4_RDCLI14_BASE_IDX … #define mmDAGB4_RDCLI15 … #define mmDAGB4_RDCLI15_BASE_IDX … #define mmDAGB4_RD_CNTL … #define mmDAGB4_RD_CNTL_BASE_IDX … #define mmDAGB4_RD_GMI_CNTL … #define mmDAGB4_RD_GMI_CNTL_BASE_IDX … #define mmDAGB4_RD_ADDR_DAGB … #define mmDAGB4_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB4_RD_CGTT_CLK_CTRL … #define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB4_RD_VC0_CNTL … #define mmDAGB4_RD_VC0_CNTL_BASE_IDX … #define mmDAGB4_RD_VC1_CNTL … #define mmDAGB4_RD_VC1_CNTL_BASE_IDX … #define mmDAGB4_RD_VC2_CNTL … #define mmDAGB4_RD_VC2_CNTL_BASE_IDX … #define mmDAGB4_RD_VC3_CNTL … #define mmDAGB4_RD_VC3_CNTL_BASE_IDX … #define mmDAGB4_RD_VC4_CNTL … #define mmDAGB4_RD_VC4_CNTL_BASE_IDX … #define mmDAGB4_RD_VC5_CNTL … #define mmDAGB4_RD_VC5_CNTL_BASE_IDX … #define mmDAGB4_RD_VC6_CNTL … #define mmDAGB4_RD_VC6_CNTL_BASE_IDX … #define mmDAGB4_RD_VC7_CNTL … #define mmDAGB4_RD_VC7_CNTL_BASE_IDX … #define mmDAGB4_RD_CNTL_MISC … #define mmDAGB4_RD_CNTL_MISC_BASE_IDX … #define mmDAGB4_RD_TLB_CREDIT … #define mmDAGB4_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB4_RDCLI_ASK_PENDING … #define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB4_RDCLI_GO_PENDING … #define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB4_RDCLI_GBLSEND_PENDING … #define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB4_RDCLI_TLB_PENDING … #define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB4_RDCLI_OARB_PENDING … #define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB4_RDCLI_OSD_PENDING … #define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB4_WRCLI0 … #define mmDAGB4_WRCLI0_BASE_IDX … #define mmDAGB4_WRCLI1 … #define mmDAGB4_WRCLI1_BASE_IDX … #define mmDAGB4_WRCLI2 … #define mmDAGB4_WRCLI2_BASE_IDX … #define mmDAGB4_WRCLI3 … #define mmDAGB4_WRCLI3_BASE_IDX … #define mmDAGB4_WRCLI4 … #define mmDAGB4_WRCLI4_BASE_IDX … #define mmDAGB4_WRCLI5 … #define mmDAGB4_WRCLI5_BASE_IDX … #define mmDAGB4_WRCLI6 … #define mmDAGB4_WRCLI6_BASE_IDX … #define mmDAGB4_WRCLI7 … #define mmDAGB4_WRCLI7_BASE_IDX … #define mmDAGB4_WRCLI8 … #define mmDAGB4_WRCLI8_BASE_IDX … #define mmDAGB4_WRCLI9 … #define mmDAGB4_WRCLI9_BASE_IDX … #define mmDAGB4_WRCLI10 … #define mmDAGB4_WRCLI10_BASE_IDX … #define mmDAGB4_WRCLI11 … #define mmDAGB4_WRCLI11_BASE_IDX … #define mmDAGB4_WRCLI12 … #define mmDAGB4_WRCLI12_BASE_IDX … #define mmDAGB4_WRCLI13 … #define mmDAGB4_WRCLI13_BASE_IDX … #define mmDAGB4_WRCLI14 … #define mmDAGB4_WRCLI14_BASE_IDX … #define mmDAGB4_WRCLI15 … #define mmDAGB4_WRCLI15_BASE_IDX … #define mmDAGB4_WR_CNTL … #define mmDAGB4_WR_CNTL_BASE_IDX … #define mmDAGB4_WR_GMI_CNTL … #define mmDAGB4_WR_GMI_CNTL_BASE_IDX … #define mmDAGB4_WR_ADDR_DAGB … #define mmDAGB4_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB4_WR_CGTT_CLK_CTRL … #define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB4_WR_DATA_DAGB … #define mmDAGB4_WR_DATA_DAGB_BASE_IDX … #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB4_WR_VC0_CNTL … #define mmDAGB4_WR_VC0_CNTL_BASE_IDX … #define mmDAGB4_WR_VC1_CNTL … #define mmDAGB4_WR_VC1_CNTL_BASE_IDX … #define mmDAGB4_WR_VC2_CNTL … #define mmDAGB4_WR_VC2_CNTL_BASE_IDX … #define mmDAGB4_WR_VC3_CNTL … #define mmDAGB4_WR_VC3_CNTL_BASE_IDX … #define mmDAGB4_WR_VC4_CNTL … #define mmDAGB4_WR_VC4_CNTL_BASE_IDX … #define mmDAGB4_WR_VC5_CNTL … #define mmDAGB4_WR_VC5_CNTL_BASE_IDX … #define mmDAGB4_WR_VC6_CNTL … #define mmDAGB4_WR_VC6_CNTL_BASE_IDX … #define mmDAGB4_WR_VC7_CNTL … #define mmDAGB4_WR_VC7_CNTL_BASE_IDX … #define mmDAGB4_WR_CNTL_MISC … #define mmDAGB4_WR_CNTL_MISC_BASE_IDX … #define mmDAGB4_WR_TLB_CREDIT … #define mmDAGB4_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB4_WR_DATA_CREDIT … #define mmDAGB4_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB4_WR_MISC_CREDIT … #define mmDAGB4_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB4_WRCLI_ASK_PENDING … #define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_GO_PENDING … #define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_GBLSEND_PENDING … #define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_TLB_PENDING … #define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_OARB_PENDING … #define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_OSD_PENDING … #define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_DBUS_ASK_PENDING … #define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB4_WRCLI_DBUS_GO_PENDING … #define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB4_DAGB_DLY … #define mmDAGB4_DAGB_DLY_BASE_IDX … #define mmDAGB4_CNTL_MISC … #define mmDAGB4_CNTL_MISC_BASE_IDX … #define mmDAGB4_CNTL_MISC2 … #define mmDAGB4_CNTL_MISC2_BASE_IDX … #define mmDAGB4_FIFO_EMPTY … #define mmDAGB4_FIFO_EMPTY_BASE_IDX … #define mmDAGB4_FIFO_FULL … #define mmDAGB4_FIFO_FULL_BASE_IDX … #define mmDAGB4_WR_CREDITS_FULL … #define mmDAGB4_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB4_RD_CREDITS_FULL … #define mmDAGB4_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB4_PERFCOUNTER_LO … #define mmDAGB4_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB4_PERFCOUNTER_HI … #define mmDAGB4_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB4_PERFCOUNTER0_CFG … #define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB4_PERFCOUNTER1_CFG … #define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB4_PERFCOUNTER2_CFG … #define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB4_PERFCOUNTER_RSLT_CNTL … #define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB4_RESERVE0 … #define mmDAGB4_RESERVE0_BASE_IDX … #define mmDAGB4_RESERVE1 … #define mmDAGB4_RESERVE1_BASE_IDX … #define mmDAGB4_RESERVE2 … #define mmDAGB4_RESERVE2_BASE_IDX … #define mmDAGB4_RESERVE3 … #define mmDAGB4_RESERVE3_BASE_IDX … #define mmDAGB4_RESERVE4 … #define mmDAGB4_RESERVE4_BASE_IDX … #define mmDAGB4_RESERVE5 … #define mmDAGB4_RESERVE5_BASE_IDX … #define mmDAGB4_RESERVE6 … #define mmDAGB4_RESERVE6_BASE_IDX … #define mmDAGB4_RESERVE7 … #define mmDAGB4_RESERVE7_BASE_IDX … #define mmDAGB4_RESERVE8 … #define mmDAGB4_RESERVE8_BASE_IDX … #define mmDAGB4_RESERVE9 … #define mmDAGB4_RESERVE9_BASE_IDX … #define mmDAGB4_RESERVE10 … #define mmDAGB4_RESERVE10_BASE_IDX … #define mmDAGB4_RESERVE11 … #define mmDAGB4_RESERVE11_BASE_IDX … #define mmDAGB4_RESERVE12 … #define mmDAGB4_RESERVE12_BASE_IDX … #define mmDAGB4_RESERVE13 … #define mmDAGB4_RESERVE13_BASE_IDX … // addressBlock: mmhub_ea_mmeadec0 // base address: 0x68a00 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_RD_GRP2VC_MAP … #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_WR_GRP2VC_MAP … #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_RD_LAZY … #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA0_DRAM_WR_LAZY … #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA0_DRAM_RD_CAM_CNTL … #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_WR_CAM_CNTL … #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_PAGE_BURST … #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_AGE … #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_AGE … #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUEUING … #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUEUING … #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_FIXED … #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_FIXED … #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_URGENCY … #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_URGENCY … #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_GMI_RD_GRP2VC_MAP … #define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_GMI_WR_GRP2VC_MAP … #define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_GMI_RD_LAZY … #define mmMMEA0_GMI_RD_LAZY_BASE_IDX … #define mmMMEA0_GMI_WR_LAZY … #define mmMMEA0_GMI_WR_LAZY_BASE_IDX … #define mmMMEA0_GMI_RD_CAM_CNTL … #define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA0_GMI_WR_CAM_CNTL … #define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA0_GMI_PAGE_BURST … #define mmMMEA0_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_AGE … #define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_AGE … #define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_QUEUING … #define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_QUEUING … #define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_FIXED … #define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_FIXED … #define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_URGENCY … #define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_URGENCY … #define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR0 … #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR1 … #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR2 … #define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR3 … #define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA0_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR4 … #define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR5 … #define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA0_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA0_ADDRDEC_BANK_CFG … #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA0_ADDRDEC_MISC_CFG … #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP0 … #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP1 … #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP0 … #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP1 … #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_RD_COMBINE_FLUSH … #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_WR_COMBINE_FLUSH … #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_GROUP_BURST … #define mmMMEA0_IO_GROUP_BURST_BASE_IDX … #define mmMMEA0_IO_RD_PRI_AGE … #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_WR_PRI_AGE … #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUEUING … #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUEUING … #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_RD_PRI_FIXED … #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_WR_PRI_FIXED … #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY … #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY … #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_SDP_ARB_DRAM … #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA0_SDP_ARB_GMI … #define mmMMEA0_SDP_ARB_GMI_BASE_IDX … #define mmMMEA0_SDP_ARB_FINAL … #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA0_SDP_DRAM_PRIORITY … #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_GMI_PRIORITY … #define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_IO_PRIORITY … #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_CREDITS … #define mmMMEA0_SDP_CREDITS_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE0 … #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE1 … #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE0 … #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE1 … #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE0 … #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE1 … #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_REQ_CNTL … #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA0_MISC … #define mmMMEA0_MISC_BASE_IDX … #define mmMMEA0_LATENCY_SAMPLING … #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA0_PERFCOUNTER_LO … #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA0_PERFCOUNTER_HI … #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA0_PERFCOUNTER0_CFG … #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER1_CFG … #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA0_EDC_CNT … #define mmMMEA0_EDC_CNT_BASE_IDX … #define mmMMEA0_EDC_CNT2 … #define mmMMEA0_EDC_CNT2_BASE_IDX … #define mmMMEA0_DSM_CNTL … #define mmMMEA0_DSM_CNTL_BASE_IDX … #define mmMMEA0_DSM_CNTLA … #define mmMMEA0_DSM_CNTLA_BASE_IDX … #define mmMMEA0_DSM_CNTLB … #define mmMMEA0_DSM_CNTLB_BASE_IDX … #define mmMMEA0_DSM_CNTL2 … #define mmMMEA0_DSM_CNTL2_BASE_IDX … #define mmMMEA0_DSM_CNTL2A … #define mmMMEA0_DSM_CNTL2A_BASE_IDX … #define mmMMEA0_DSM_CNTL2B … #define mmMMEA0_DSM_CNTL2B_BASE_IDX … #define mmMMEA0_CGTT_CLK_CTRL … #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA0_EDC_MODE … #define mmMMEA0_EDC_MODE_BASE_IDX … #define mmMMEA0_ERR_STATUS … #define mmMMEA0_ERR_STATUS_BASE_IDX … #define mmMMEA0_MISC2 … #define mmMMEA0_MISC2_BASE_IDX … #define mmMMEA0_ADDRDEC_SELECT … #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA0_EDC_CNT3 … #define mmMMEA0_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec1 // base address: 0x68f00 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_DRAM_RD_GRP2VC_MAP … #define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_DRAM_WR_GRP2VC_MAP … #define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_DRAM_RD_LAZY … #define mmMMEA1_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA1_DRAM_WR_LAZY … #define mmMMEA1_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA1_DRAM_RD_CAM_CNTL … #define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA1_DRAM_WR_CAM_CNTL … #define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA1_DRAM_PAGE_BURST … #define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_AGE … #define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_AGE … #define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUEUING … #define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUEUING … #define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_FIXED … #define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_FIXED … #define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_URGENCY … #define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_URGENCY … #define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_GMI_RD_GRP2VC_MAP … #define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_GMI_WR_GRP2VC_MAP … #define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA1_GMI_RD_LAZY … #define mmMMEA1_GMI_RD_LAZY_BASE_IDX … #define mmMMEA1_GMI_WR_LAZY … #define mmMMEA1_GMI_WR_LAZY_BASE_IDX … #define mmMMEA1_GMI_RD_CAM_CNTL … #define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA1_GMI_WR_CAM_CNTL … #define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA1_GMI_PAGE_BURST … #define mmMMEA1_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_AGE … #define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_AGE … #define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_QUEUING … #define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_QUEUING … #define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_FIXED … #define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_FIXED … #define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_URGENCY … #define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_URGENCY … #define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR0 … #define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR1 … #define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR2 … #define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR3 … #define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA1_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR4 … #define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA1_ADDRNORM_BASE_ADDR5 … #define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA1_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA1_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA1_ADDRDEC_BANK_CFG … #define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA1_ADDRDEC_MISC_CFG … #define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA1_IO_RD_CLI2GRP_MAP0 … #define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_IO_RD_CLI2GRP_MAP1 … #define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_IO_WR_CLI2GRP_MAP0 … #define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA1_IO_WR_CLI2GRP_MAP1 … #define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA1_IO_RD_COMBINE_FLUSH … #define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA1_IO_WR_COMBINE_FLUSH … #define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA1_IO_GROUP_BURST … #define mmMMEA1_IO_GROUP_BURST_BASE_IDX … #define mmMMEA1_IO_RD_PRI_AGE … #define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA1_IO_WR_PRI_AGE … #define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUEUING … #define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUEUING … #define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA1_IO_RD_PRI_FIXED … #define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA1_IO_WR_PRI_FIXED … #define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA1_IO_RD_PRI_URGENCY … #define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA1_IO_WR_PRI_URGENCY … #define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA1_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA1_SDP_ARB_DRAM … #define mmMMEA1_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA1_SDP_ARB_GMI … #define mmMMEA1_SDP_ARB_GMI_BASE_IDX … #define mmMMEA1_SDP_ARB_FINAL … #define mmMMEA1_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA1_SDP_DRAM_PRIORITY … #define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA1_SDP_GMI_PRIORITY … #define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA1_SDP_IO_PRIORITY … #define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA1_SDP_CREDITS … #define mmMMEA1_SDP_CREDITS_BASE_IDX … #define mmMMEA1_SDP_TAG_RESERVE0 … #define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_TAG_RESERVE1 … #define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_VCC_RESERVE0 … #define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_VCC_RESERVE1 … #define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_VCD_RESERVE0 … #define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA1_SDP_VCD_RESERVE1 … #define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA1_SDP_REQ_CNTL … #define mmMMEA1_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA1_MISC … #define mmMMEA1_MISC_BASE_IDX … #define mmMMEA1_LATENCY_SAMPLING … #define mmMMEA1_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA1_PERFCOUNTER_LO … #define mmMMEA1_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA1_PERFCOUNTER_HI … #define mmMMEA1_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA1_PERFCOUNTER0_CFG … #define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA1_PERFCOUNTER1_CFG … #define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA1_PERFCOUNTER_RSLT_CNTL … #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA1_EDC_CNT … #define mmMMEA1_EDC_CNT_BASE_IDX … #define mmMMEA1_EDC_CNT2 … #define mmMMEA1_EDC_CNT2_BASE_IDX … #define mmMMEA1_DSM_CNTL … #define mmMMEA1_DSM_CNTL_BASE_IDX … #define mmMMEA1_DSM_CNTLA … #define mmMMEA1_DSM_CNTLA_BASE_IDX … #define mmMMEA1_DSM_CNTLB … #define mmMMEA1_DSM_CNTLB_BASE_IDX … #define mmMMEA1_DSM_CNTL2 … #define mmMMEA1_DSM_CNTL2_BASE_IDX … #define mmMMEA1_DSM_CNTL2A … #define mmMMEA1_DSM_CNTL2A_BASE_IDX … #define mmMMEA1_DSM_CNTL2B … #define mmMMEA1_DSM_CNTL2B_BASE_IDX … #define mmMMEA1_CGTT_CLK_CTRL … #define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA1_EDC_MODE … #define mmMMEA1_EDC_MODE_BASE_IDX … #define mmMMEA1_ERR_STATUS … #define mmMMEA1_ERR_STATUS_BASE_IDX … #define mmMMEA1_MISC2 … #define mmMMEA1_MISC2_BASE_IDX … #define mmMMEA1_ADDRDEC_SELECT … #define mmMMEA1_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA1_EDC_CNT3 … #define mmMMEA1_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec2 // base address: 0x69400 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_DRAM_RD_GRP2VC_MAP … #define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA2_DRAM_WR_GRP2VC_MAP … #define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA2_DRAM_RD_LAZY … #define mmMMEA2_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA2_DRAM_WR_LAZY … #define mmMMEA2_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA2_DRAM_RD_CAM_CNTL … #define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA2_DRAM_WR_CAM_CNTL … #define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA2_DRAM_PAGE_BURST … #define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_AGE … #define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_AGE … #define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_QUEUING … #define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_QUEUING … #define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_FIXED … #define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_FIXED … #define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_URGENCY … #define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_URGENCY … #define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_GMI_RD_GRP2VC_MAP … #define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA2_GMI_WR_GRP2VC_MAP … #define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA2_GMI_RD_LAZY … #define mmMMEA2_GMI_RD_LAZY_BASE_IDX … #define mmMMEA2_GMI_WR_LAZY … #define mmMMEA2_GMI_WR_LAZY_BASE_IDX … #define mmMMEA2_GMI_RD_CAM_CNTL … #define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA2_GMI_WR_CAM_CNTL … #define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA2_GMI_PAGE_BURST … #define mmMMEA2_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_AGE … #define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_AGE … #define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_QUEUING … #define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_QUEUING … #define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_FIXED … #define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_FIXED … #define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_URGENCY … #define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_URGENCY … #define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR0 … #define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR1 … #define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA2_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR2 … #define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR3 … #define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA2_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR4 … #define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA2_ADDRNORM_BASE_ADDR5 … #define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA2_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA2_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA2_ADDRDEC_BANK_CFG … #define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA2_ADDRDEC_MISC_CFG … #define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA2_IO_RD_CLI2GRP_MAP0 … #define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_IO_RD_CLI2GRP_MAP1 … #define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_IO_WR_CLI2GRP_MAP0 … #define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA2_IO_WR_CLI2GRP_MAP1 … #define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA2_IO_RD_COMBINE_FLUSH … #define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA2_IO_WR_COMBINE_FLUSH … #define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA2_IO_GROUP_BURST … #define mmMMEA2_IO_GROUP_BURST_BASE_IDX … #define mmMMEA2_IO_RD_PRI_AGE … #define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA2_IO_WR_PRI_AGE … #define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA2_IO_RD_PRI_QUEUING … #define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA2_IO_WR_PRI_QUEUING … #define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA2_IO_RD_PRI_FIXED … #define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA2_IO_WR_PRI_FIXED … #define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA2_IO_RD_PRI_URGENCY … #define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA2_IO_WR_PRI_URGENCY … #define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA2_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA2_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA2_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA2_SDP_ARB_DRAM … #define mmMMEA2_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA2_SDP_ARB_GMI … #define mmMMEA2_SDP_ARB_GMI_BASE_IDX … #define mmMMEA2_SDP_ARB_FINAL … #define mmMMEA2_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA2_SDP_DRAM_PRIORITY … #define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA2_SDP_GMI_PRIORITY … #define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA2_SDP_IO_PRIORITY … #define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA2_SDP_CREDITS … #define mmMMEA2_SDP_CREDITS_BASE_IDX … #define mmMMEA2_SDP_TAG_RESERVE0 … #define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA2_SDP_TAG_RESERVE1 … #define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA2_SDP_VCC_RESERVE0 … #define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA2_SDP_VCC_RESERVE1 … #define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA2_SDP_VCD_RESERVE0 … #define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA2_SDP_VCD_RESERVE1 … #define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA2_SDP_REQ_CNTL … #define mmMMEA2_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA2_MISC … #define mmMMEA2_MISC_BASE_IDX … #define mmMMEA2_LATENCY_SAMPLING … #define mmMMEA2_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA2_PERFCOUNTER_LO … #define mmMMEA2_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA2_PERFCOUNTER_HI … #define mmMMEA2_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA2_PERFCOUNTER0_CFG … #define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA2_PERFCOUNTER1_CFG … #define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA2_PERFCOUNTER_RSLT_CNTL … #define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA2_EDC_CNT … #define mmMMEA2_EDC_CNT_BASE_IDX … #define mmMMEA2_EDC_CNT2 … #define mmMMEA2_EDC_CNT2_BASE_IDX … #define mmMMEA2_DSM_CNTL … #define mmMMEA2_DSM_CNTL_BASE_IDX … #define mmMMEA2_DSM_CNTLA … #define mmMMEA2_DSM_CNTLA_BASE_IDX … #define mmMMEA2_DSM_CNTLB … #define mmMMEA2_DSM_CNTLB_BASE_IDX … #define mmMMEA2_DSM_CNTL2 … #define mmMMEA2_DSM_CNTL2_BASE_IDX … #define mmMMEA2_DSM_CNTL2A … #define mmMMEA2_DSM_CNTL2A_BASE_IDX … #define mmMMEA2_DSM_CNTL2B … #define mmMMEA2_DSM_CNTL2B_BASE_IDX … #define mmMMEA2_CGTT_CLK_CTRL … #define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA2_EDC_MODE … #define mmMMEA2_EDC_MODE_BASE_IDX … #define mmMMEA2_ERR_STATUS … #define mmMMEA2_ERR_STATUS_BASE_IDX … #define mmMMEA2_MISC2 … #define mmMMEA2_MISC2_BASE_IDX … #define mmMMEA2_ADDRDEC_SELECT … #define mmMMEA2_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA2_EDC_CNT3 … #define mmMMEA2_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec3 // base address: 0x69900 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_DRAM_RD_GRP2VC_MAP … #define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA3_DRAM_WR_GRP2VC_MAP … #define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA3_DRAM_RD_LAZY … #define mmMMEA3_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA3_DRAM_WR_LAZY … #define mmMMEA3_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA3_DRAM_RD_CAM_CNTL … #define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA3_DRAM_WR_CAM_CNTL … #define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA3_DRAM_PAGE_BURST … #define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_AGE … #define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_AGE … #define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_QUEUING … #define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_QUEUING … #define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_FIXED … #define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_FIXED … #define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_URGENCY … #define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_URGENCY … #define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_GMI_RD_GRP2VC_MAP … #define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA3_GMI_WR_GRP2VC_MAP … #define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA3_GMI_RD_LAZY … #define mmMMEA3_GMI_RD_LAZY_BASE_IDX … #define mmMMEA3_GMI_WR_LAZY … #define mmMMEA3_GMI_WR_LAZY_BASE_IDX … #define mmMMEA3_GMI_RD_CAM_CNTL … #define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA3_GMI_WR_CAM_CNTL … #define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA3_GMI_PAGE_BURST … #define mmMMEA3_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_AGE … #define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_AGE … #define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_QUEUING … #define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_QUEUING … #define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_FIXED … #define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_FIXED … #define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_URGENCY … #define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_URGENCY … #define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR0 … #define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR1 … #define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA3_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR2 … #define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR3 … #define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA3_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR4 … #define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA3_ADDRNORM_BASE_ADDR5 … #define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA3_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA3_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA3_ADDRDEC_BANK_CFG … #define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA3_ADDRDEC_MISC_CFG … #define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA3_IO_RD_CLI2GRP_MAP0 … #define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_IO_RD_CLI2GRP_MAP1 … #define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_IO_WR_CLI2GRP_MAP0 … #define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA3_IO_WR_CLI2GRP_MAP1 … #define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA3_IO_RD_COMBINE_FLUSH … #define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA3_IO_WR_COMBINE_FLUSH … #define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA3_IO_GROUP_BURST … #define mmMMEA3_IO_GROUP_BURST_BASE_IDX … #define mmMMEA3_IO_RD_PRI_AGE … #define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA3_IO_WR_PRI_AGE … #define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA3_IO_RD_PRI_QUEUING … #define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA3_IO_WR_PRI_QUEUING … #define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA3_IO_RD_PRI_FIXED … #define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA3_IO_WR_PRI_FIXED … #define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA3_IO_RD_PRI_URGENCY … #define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA3_IO_WR_PRI_URGENCY … #define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA3_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA3_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA3_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA3_SDP_ARB_DRAM … #define mmMMEA3_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA3_SDP_ARB_GMI … #define mmMMEA3_SDP_ARB_GMI_BASE_IDX … #define mmMMEA3_SDP_ARB_FINAL … #define mmMMEA3_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA3_SDP_DRAM_PRIORITY … #define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA3_SDP_GMI_PRIORITY … #define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA3_SDP_IO_PRIORITY … #define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA3_SDP_CREDITS … #define mmMMEA3_SDP_CREDITS_BASE_IDX … #define mmMMEA3_SDP_TAG_RESERVE0 … #define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA3_SDP_TAG_RESERVE1 … #define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA3_SDP_VCC_RESERVE0 … #define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA3_SDP_VCC_RESERVE1 … #define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA3_SDP_VCD_RESERVE0 … #define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA3_SDP_VCD_RESERVE1 … #define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA3_SDP_REQ_CNTL … #define mmMMEA3_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA3_MISC … #define mmMMEA3_MISC_BASE_IDX … #define mmMMEA3_LATENCY_SAMPLING … #define mmMMEA3_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA3_PERFCOUNTER_LO … #define mmMMEA3_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA3_PERFCOUNTER_HI … #define mmMMEA3_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA3_PERFCOUNTER0_CFG … #define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA3_PERFCOUNTER1_CFG … #define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA3_PERFCOUNTER_RSLT_CNTL … #define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA3_EDC_CNT … #define mmMMEA3_EDC_CNT_BASE_IDX … #define mmMMEA3_EDC_CNT2 … #define mmMMEA3_EDC_CNT2_BASE_IDX … #define mmMMEA3_DSM_CNTL … #define mmMMEA3_DSM_CNTL_BASE_IDX … #define mmMMEA3_DSM_CNTLA … #define mmMMEA3_DSM_CNTLA_BASE_IDX … #define mmMMEA3_DSM_CNTLB … #define mmMMEA3_DSM_CNTLB_BASE_IDX … #define mmMMEA3_DSM_CNTL2 … #define mmMMEA3_DSM_CNTL2_BASE_IDX … #define mmMMEA3_DSM_CNTL2A … #define mmMMEA3_DSM_CNTL2A_BASE_IDX … #define mmMMEA3_DSM_CNTL2B … #define mmMMEA3_DSM_CNTL2B_BASE_IDX … #define mmMMEA3_CGTT_CLK_CTRL … #define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA3_EDC_MODE … #define mmMMEA3_EDC_MODE_BASE_IDX … #define mmMMEA3_ERR_STATUS … #define mmMMEA3_ERR_STATUS_BASE_IDX … #define mmMMEA3_MISC2 … #define mmMMEA3_MISC2_BASE_IDX … #define mmMMEA3_ADDRDEC_SELECT … #define mmMMEA3_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA3_EDC_CNT3 … #define mmMMEA3_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec4 // base address: 0x69e00 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_DRAM_RD_GRP2VC_MAP … #define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA4_DRAM_WR_GRP2VC_MAP … #define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA4_DRAM_RD_LAZY … #define mmMMEA4_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA4_DRAM_WR_LAZY … #define mmMMEA4_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA4_DRAM_RD_CAM_CNTL … #define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA4_DRAM_WR_CAM_CNTL … #define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA4_DRAM_PAGE_BURST … #define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_AGE … #define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_AGE … #define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_QUEUING … #define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_QUEUING … #define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_FIXED … #define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_FIXED … #define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_URGENCY … #define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_URGENCY … #define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_GMI_RD_GRP2VC_MAP … #define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA4_GMI_WR_GRP2VC_MAP … #define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA4_GMI_RD_LAZY … #define mmMMEA4_GMI_RD_LAZY_BASE_IDX … #define mmMMEA4_GMI_WR_LAZY … #define mmMMEA4_GMI_WR_LAZY_BASE_IDX … #define mmMMEA4_GMI_RD_CAM_CNTL … #define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA4_GMI_WR_CAM_CNTL … #define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA4_GMI_PAGE_BURST … #define mmMMEA4_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_AGE … #define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_AGE … #define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_QUEUING … #define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_QUEUING … #define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_FIXED … #define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_FIXED … #define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_URGENCY … #define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_URGENCY … #define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR0 … #define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR1 … #define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA4_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR2 … #define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR3 … #define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA4_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR4 … #define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA4_ADDRNORM_BASE_ADDR5 … #define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA4_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA4_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA4_ADDRDEC_BANK_CFG … #define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA4_ADDRDEC_MISC_CFG … #define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA4_IO_RD_CLI2GRP_MAP0 … #define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_IO_RD_CLI2GRP_MAP1 … #define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_IO_WR_CLI2GRP_MAP0 … #define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA4_IO_WR_CLI2GRP_MAP1 … #define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA4_IO_RD_COMBINE_FLUSH … #define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA4_IO_WR_COMBINE_FLUSH … #define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA4_IO_GROUP_BURST … #define mmMMEA4_IO_GROUP_BURST_BASE_IDX … #define mmMMEA4_IO_RD_PRI_AGE … #define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA4_IO_WR_PRI_AGE … #define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA4_IO_RD_PRI_QUEUING … #define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA4_IO_WR_PRI_QUEUING … #define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA4_IO_RD_PRI_FIXED … #define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA4_IO_WR_PRI_FIXED … #define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA4_IO_RD_PRI_URGENCY … #define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA4_IO_WR_PRI_URGENCY … #define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA4_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA4_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA4_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA4_SDP_ARB_DRAM … #define mmMMEA4_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA4_SDP_ARB_GMI … #define mmMMEA4_SDP_ARB_GMI_BASE_IDX … #define mmMMEA4_SDP_ARB_FINAL … #define mmMMEA4_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA4_SDP_DRAM_PRIORITY … #define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA4_SDP_GMI_PRIORITY … #define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA4_SDP_IO_PRIORITY … #define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA4_SDP_CREDITS … #define mmMMEA4_SDP_CREDITS_BASE_IDX … #define mmMMEA4_SDP_TAG_RESERVE0 … #define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA4_SDP_TAG_RESERVE1 … #define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA4_SDP_VCC_RESERVE0 … #define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA4_SDP_VCC_RESERVE1 … #define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA4_SDP_VCD_RESERVE0 … #define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA4_SDP_VCD_RESERVE1 … #define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA4_SDP_REQ_CNTL … #define mmMMEA4_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA4_MISC … #define mmMMEA4_MISC_BASE_IDX … #define mmMMEA4_LATENCY_SAMPLING … #define mmMMEA4_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA4_PERFCOUNTER_LO … #define mmMMEA4_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA4_PERFCOUNTER_HI … #define mmMMEA4_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA4_PERFCOUNTER0_CFG … #define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA4_PERFCOUNTER1_CFG … #define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA4_PERFCOUNTER_RSLT_CNTL … #define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA4_EDC_CNT … #define mmMMEA4_EDC_CNT_BASE_IDX … #define mmMMEA4_EDC_CNT2 … #define mmMMEA4_EDC_CNT2_BASE_IDX … #define mmMMEA4_DSM_CNTL … #define mmMMEA4_DSM_CNTL_BASE_IDX … #define mmMMEA4_DSM_CNTLA … #define mmMMEA4_DSM_CNTLA_BASE_IDX … #define mmMMEA4_DSM_CNTLB … #define mmMMEA4_DSM_CNTLB_BASE_IDX … #define mmMMEA4_DSM_CNTL2 … #define mmMMEA4_DSM_CNTL2_BASE_IDX … #define mmMMEA4_DSM_CNTL2A … #define mmMMEA4_DSM_CNTL2A_BASE_IDX … #define mmMMEA4_DSM_CNTL2B … #define mmMMEA4_DSM_CNTL2B_BASE_IDX … #define mmMMEA4_CGTT_CLK_CTRL … #define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA4_EDC_MODE … #define mmMMEA4_EDC_MODE_BASE_IDX … #define mmMMEA4_ERR_STATUS … #define mmMMEA4_ERR_STATUS_BASE_IDX … #define mmMMEA4_MISC2 … #define mmMMEA4_MISC2_BASE_IDX … #define mmMMEA4_ADDRDEC_SELECT … #define mmMMEA4_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA4_EDC_CNT3 … #define mmMMEA4_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_pctldec0 // base address: 0x6a300 #define mmPCTL0_CTRL … #define mmPCTL0_CTRL_BASE_IDX … #define mmPCTL0_MMHUB_DEEPSLEEP_IB … #define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE … #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB … #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX … #define mmPCTL0_PG_IGNORE_DEEPSLEEP … #define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB … #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL0_SLICE0_CFG_DAGB_BUSY … #define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL0_SLICE0_CFG_DS_ALLOW … #define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB … #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL0_SLICE1_CFG_DAGB_BUSY … #define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL0_SLICE1_CFG_DS_ALLOW … #define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB … #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL0_SLICE2_CFG_DAGB_BUSY … #define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL0_SLICE2_CFG_DS_ALLOW … #define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB … #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL0_SLICE3_CFG_DAGB_BUSY … #define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL0_SLICE3_CFG_DS_ALLOW … #define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB … #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL0_SLICE4_CFG_DAGB_BUSY … #define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL0_SLICE4_CFG_DS_ALLOW … #define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB … #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL0_UTCL2_MISC … #define mmPCTL0_UTCL2_MISC_BASE_IDX … #define mmPCTL0_SLICE0_MISC … #define mmPCTL0_SLICE0_MISC_BASE_IDX … #define mmPCTL0_SLICE1_MISC … #define mmPCTL0_SLICE1_MISC_BASE_IDX … #define mmPCTL0_SLICE2_MISC … #define mmPCTL0_SLICE2_MISC_BASE_IDX … #define mmPCTL0_SLICE3_MISC … #define mmPCTL0_SLICE3_MISC_BASE_IDX … #define mmPCTL0_SLICE4_MISC … #define mmPCTL0_SLICE4_MISC_BASE_IDX … #define mmPCTL0_UTCL2_RENG_EXECUTE … #define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_SLICE0_RENG_EXECUTE … #define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_SLICE1_RENG_EXECUTE … #define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_SLICE2_RENG_EXECUTE … #define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_SLICE3_RENG_EXECUTE … #define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_SLICE4_RENG_EXECUTE … #define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX … #define mmPCTL0_UTCL2_RENG_RAM_INDEX … #define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_UTCL2_RENG_RAM_DATA … #define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_SLICE0_RENG_RAM_INDEX … #define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_SLICE0_RENG_RAM_DATA … #define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_SLICE1_RENG_RAM_INDEX … #define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_SLICE1_RENG_RAM_DATA … #define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_SLICE2_RENG_RAM_INDEX … #define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_SLICE2_RENG_RAM_DATA … #define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_SLICE3_RENG_RAM_INDEX … #define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_SLICE3_RENG_RAM_DATA … #define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_SLICE4_RENG_RAM_INDEX … #define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL0_SLICE4_RENG_RAM_DATA … #define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1dec // base address: 0x6a500 #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS … #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1pldec // base address: 0x6a580 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1prdec // base address: 0x6a5c0 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO … #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI … #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2dec // base address: 0x6a600 #define mmATCL2_0_ATC_L2_CNTL … #define mmATCL2_0_ATC_L2_CNTL_BASE_IDX … #define mmATCL2_0_ATC_L2_CNTL2 … #define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_DATA0 … #define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_DATA1 … #define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_DATA2 … #define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX … #define mmATCL2_0_ATC_L2_CNTL3 … #define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX … #define mmATCL2_0_ATC_L2_STATUS … #define mmATCL2_0_ATC_L2_STATUS_BASE_IDX … #define mmATCL2_0_ATC_L2_STATUS2 … #define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX … #define mmATCL2_0_ATC_L2_STATUS3 … #define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX … #define mmATCL2_0_ATC_L2_MISC_CG … #define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX … #define mmATCL2_0_ATC_L2_MEM_POWER_LS … #define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX … #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL … #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX … #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX … #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL … #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX … #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL … #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX … #define mmATCL2_0_ATC_L2_CNTL4 … #define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX … #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES … #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pfdec // base address: 0x6a700 #define mmVML2PF0_VM_L2_CNTL … #define mmVML2PF0_VM_L2_CNTL_BASE_IDX … #define mmVML2PF0_VM_L2_CNTL2 … #define mmVML2PF0_VM_L2_CNTL2_BASE_IDX … #define mmVML2PF0_VM_L2_CNTL3 … #define mmVML2PF0_VM_L2_CNTL3_BASE_IDX … #define mmVML2PF0_VM_L2_STATUS … #define mmVML2PF0_VM_L2_STATUS_BASE_IDX … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define mmVML2PF0_VM_L2_CNTL4 … #define mmVML2PF0_VM_L2_CNTL4_BASE_IDX … #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES … #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID … #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 … #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL … #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL … #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2vcdec // base address: 0x6a800 #define mmVML2VC0_VM_CONTEXT0_CNTL … #define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_CNTL … #define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_CNTL … #define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_CNTL … #define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_CNTL … #define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_CNTL … #define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_CNTL … #define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_CNTL … #define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_CNTL … #define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_CNTL … #define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_CNTL … #define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_CNTL … #define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_CNTL … #define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_CNTL … #define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_CNTL … #define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_CNTL … #define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX … #define mmVML2VC0_VM_CONTEXTS_DISABLE … #define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM … #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ … #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK … #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6ab90 #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE … #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT … #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL … #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB … #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_FB_OFFSET … #define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_STEERING … #define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX … #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ … #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define mmVMSHAREDPF0_MC_MEM_POWER_LS … #define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_APT_CNTL … #define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL … #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE … #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL … #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX … #define mmMC_VM_XGMI_LFB_CNTL … #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX … #define mmMC_VM_XGMI_LFB_SIZE … #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedvcdec // base address: 0x6ac00 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE … #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP … #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_AGP_TOP … #define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_AGP_BOT … #define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_AGP_BASE … #define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL … #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedhvdec // base address: 0x6ac80 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 … #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 … #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 … #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 … #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 … #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX … #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER … #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 … #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL … #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX … #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID … #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE … #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntrdec // base address: 0x6adc0 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO … #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX … #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI … #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntldec // base address: 0x6add0 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG … #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG … #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL … #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pldec // base address: 0x6ae00 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2prdec // base address: 0x6ae40 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO … #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI … #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec5 // base address: 0x74000 #define mmDAGB5_RDCLI0 … #define mmDAGB5_RDCLI0_BASE_IDX … #define mmDAGB5_RDCLI1 … #define mmDAGB5_RDCLI1_BASE_IDX … #define mmDAGB5_RDCLI2 … #define mmDAGB5_RDCLI2_BASE_IDX … #define mmDAGB5_RDCLI3 … #define mmDAGB5_RDCLI3_BASE_IDX … #define mmDAGB5_RDCLI4 … #define mmDAGB5_RDCLI4_BASE_IDX … #define mmDAGB5_RDCLI5 … #define mmDAGB5_RDCLI5_BASE_IDX … #define mmDAGB5_RDCLI6 … #define mmDAGB5_RDCLI6_BASE_IDX … #define mmDAGB5_RDCLI7 … #define mmDAGB5_RDCLI7_BASE_IDX … #define mmDAGB5_RDCLI8 … #define mmDAGB5_RDCLI8_BASE_IDX … #define mmDAGB5_RDCLI9 … #define mmDAGB5_RDCLI9_BASE_IDX … #define mmDAGB5_RDCLI10 … #define mmDAGB5_RDCLI10_BASE_IDX … #define mmDAGB5_RDCLI11 … #define mmDAGB5_RDCLI11_BASE_IDX … #define mmDAGB5_RDCLI12 … #define mmDAGB5_RDCLI12_BASE_IDX … #define mmDAGB5_RDCLI13 … #define mmDAGB5_RDCLI13_BASE_IDX … #define mmDAGB5_RDCLI14 … #define mmDAGB5_RDCLI14_BASE_IDX … #define mmDAGB5_RDCLI15 … #define mmDAGB5_RDCLI15_BASE_IDX … #define mmDAGB5_RD_CNTL … #define mmDAGB5_RD_CNTL_BASE_IDX … #define mmDAGB5_RD_GMI_CNTL … #define mmDAGB5_RD_GMI_CNTL_BASE_IDX … #define mmDAGB5_RD_ADDR_DAGB … #define mmDAGB5_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB5_RD_CGTT_CLK_CTRL … #define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB5_RD_VC0_CNTL … #define mmDAGB5_RD_VC0_CNTL_BASE_IDX … #define mmDAGB5_RD_VC1_CNTL … #define mmDAGB5_RD_VC1_CNTL_BASE_IDX … #define mmDAGB5_RD_VC2_CNTL … #define mmDAGB5_RD_VC2_CNTL_BASE_IDX … #define mmDAGB5_RD_VC3_CNTL … #define mmDAGB5_RD_VC3_CNTL_BASE_IDX … #define mmDAGB5_RD_VC4_CNTL … #define mmDAGB5_RD_VC4_CNTL_BASE_IDX … #define mmDAGB5_RD_VC5_CNTL … #define mmDAGB5_RD_VC5_CNTL_BASE_IDX … #define mmDAGB5_RD_VC6_CNTL … #define mmDAGB5_RD_VC6_CNTL_BASE_IDX … #define mmDAGB5_RD_VC7_CNTL … #define mmDAGB5_RD_VC7_CNTL_BASE_IDX … #define mmDAGB5_RD_CNTL_MISC … #define mmDAGB5_RD_CNTL_MISC_BASE_IDX … #define mmDAGB5_RD_TLB_CREDIT … #define mmDAGB5_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB5_RDCLI_ASK_PENDING … #define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB5_RDCLI_GO_PENDING … #define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB5_RDCLI_GBLSEND_PENDING … #define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB5_RDCLI_TLB_PENDING … #define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB5_RDCLI_OARB_PENDING … #define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB5_RDCLI_OSD_PENDING … #define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB5_WRCLI0 … #define mmDAGB5_WRCLI0_BASE_IDX … #define mmDAGB5_WRCLI1 … #define mmDAGB5_WRCLI1_BASE_IDX … #define mmDAGB5_WRCLI2 … #define mmDAGB5_WRCLI2_BASE_IDX … #define mmDAGB5_WRCLI3 … #define mmDAGB5_WRCLI3_BASE_IDX … #define mmDAGB5_WRCLI4 … #define mmDAGB5_WRCLI4_BASE_IDX … #define mmDAGB5_WRCLI5 … #define mmDAGB5_WRCLI5_BASE_IDX … #define mmDAGB5_WRCLI6 … #define mmDAGB5_WRCLI6_BASE_IDX … #define mmDAGB5_WRCLI7 … #define mmDAGB5_WRCLI7_BASE_IDX … #define mmDAGB5_WRCLI8 … #define mmDAGB5_WRCLI8_BASE_IDX … #define mmDAGB5_WRCLI9 … #define mmDAGB5_WRCLI9_BASE_IDX … #define mmDAGB5_WRCLI10 … #define mmDAGB5_WRCLI10_BASE_IDX … #define mmDAGB5_WRCLI11 … #define mmDAGB5_WRCLI11_BASE_IDX … #define mmDAGB5_WRCLI12 … #define mmDAGB5_WRCLI12_BASE_IDX … #define mmDAGB5_WRCLI13 … #define mmDAGB5_WRCLI13_BASE_IDX … #define mmDAGB5_WRCLI14 … #define mmDAGB5_WRCLI14_BASE_IDX … #define mmDAGB5_WRCLI15 … #define mmDAGB5_WRCLI15_BASE_IDX … #define mmDAGB5_WR_CNTL … #define mmDAGB5_WR_CNTL_BASE_IDX … #define mmDAGB5_WR_GMI_CNTL … #define mmDAGB5_WR_GMI_CNTL_BASE_IDX … #define mmDAGB5_WR_ADDR_DAGB … #define mmDAGB5_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB5_WR_CGTT_CLK_CTRL … #define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB5_WR_DATA_DAGB … #define mmDAGB5_WR_DATA_DAGB_BASE_IDX … #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB5_WR_VC0_CNTL … #define mmDAGB5_WR_VC0_CNTL_BASE_IDX … #define mmDAGB5_WR_VC1_CNTL … #define mmDAGB5_WR_VC1_CNTL_BASE_IDX … #define mmDAGB5_WR_VC2_CNTL … #define mmDAGB5_WR_VC2_CNTL_BASE_IDX … #define mmDAGB5_WR_VC3_CNTL … #define mmDAGB5_WR_VC3_CNTL_BASE_IDX … #define mmDAGB5_WR_VC4_CNTL … #define mmDAGB5_WR_VC4_CNTL_BASE_IDX … #define mmDAGB5_WR_VC5_CNTL … #define mmDAGB5_WR_VC5_CNTL_BASE_IDX … #define mmDAGB5_WR_VC6_CNTL … #define mmDAGB5_WR_VC6_CNTL_BASE_IDX … #define mmDAGB5_WR_VC7_CNTL … #define mmDAGB5_WR_VC7_CNTL_BASE_IDX … #define mmDAGB5_WR_CNTL_MISC … #define mmDAGB5_WR_CNTL_MISC_BASE_IDX … #define mmDAGB5_WR_TLB_CREDIT … #define mmDAGB5_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB5_WR_DATA_CREDIT … #define mmDAGB5_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB5_WR_MISC_CREDIT … #define mmDAGB5_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB5_WRCLI_ASK_PENDING … #define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_GO_PENDING … #define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_GBLSEND_PENDING … #define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_TLB_PENDING … #define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_OARB_PENDING … #define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_OSD_PENDING … #define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_DBUS_ASK_PENDING … #define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB5_WRCLI_DBUS_GO_PENDING … #define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB5_DAGB_DLY … #define mmDAGB5_DAGB_DLY_BASE_IDX … #define mmDAGB5_CNTL_MISC … #define mmDAGB5_CNTL_MISC_BASE_IDX … #define mmDAGB5_CNTL_MISC2 … #define mmDAGB5_CNTL_MISC2_BASE_IDX … #define mmDAGB5_FIFO_EMPTY … #define mmDAGB5_FIFO_EMPTY_BASE_IDX … #define mmDAGB5_FIFO_FULL … #define mmDAGB5_FIFO_FULL_BASE_IDX … #define mmDAGB5_WR_CREDITS_FULL … #define mmDAGB5_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB5_RD_CREDITS_FULL … #define mmDAGB5_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB5_PERFCOUNTER_LO … #define mmDAGB5_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB5_PERFCOUNTER_HI … #define mmDAGB5_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB5_PERFCOUNTER0_CFG … #define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB5_PERFCOUNTER1_CFG … #define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB5_PERFCOUNTER2_CFG … #define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB5_PERFCOUNTER_RSLT_CNTL … #define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB5_RESERVE0 … #define mmDAGB5_RESERVE0_BASE_IDX … #define mmDAGB5_RESERVE1 … #define mmDAGB5_RESERVE1_BASE_IDX … #define mmDAGB5_RESERVE2 … #define mmDAGB5_RESERVE2_BASE_IDX … #define mmDAGB5_RESERVE3 … #define mmDAGB5_RESERVE3_BASE_IDX … #define mmDAGB5_RESERVE4 … #define mmDAGB5_RESERVE4_BASE_IDX … #define mmDAGB5_RESERVE5 … #define mmDAGB5_RESERVE5_BASE_IDX … #define mmDAGB5_RESERVE6 … #define mmDAGB5_RESERVE6_BASE_IDX … #define mmDAGB5_RESERVE7 … #define mmDAGB5_RESERVE7_BASE_IDX … #define mmDAGB5_RESERVE8 … #define mmDAGB5_RESERVE8_BASE_IDX … #define mmDAGB5_RESERVE9 … #define mmDAGB5_RESERVE9_BASE_IDX … #define mmDAGB5_RESERVE10 … #define mmDAGB5_RESERVE10_BASE_IDX … #define mmDAGB5_RESERVE11 … #define mmDAGB5_RESERVE11_BASE_IDX … #define mmDAGB5_RESERVE12 … #define mmDAGB5_RESERVE12_BASE_IDX … #define mmDAGB5_RESERVE13 … #define mmDAGB5_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec6 // base address: 0x74200 #define mmDAGB6_RDCLI0 … #define mmDAGB6_RDCLI0_BASE_IDX … #define mmDAGB6_RDCLI1 … #define mmDAGB6_RDCLI1_BASE_IDX … #define mmDAGB6_RDCLI2 … #define mmDAGB6_RDCLI2_BASE_IDX … #define mmDAGB6_RDCLI3 … #define mmDAGB6_RDCLI3_BASE_IDX … #define mmDAGB6_RDCLI4 … #define mmDAGB6_RDCLI4_BASE_IDX … #define mmDAGB6_RDCLI5 … #define mmDAGB6_RDCLI5_BASE_IDX … #define mmDAGB6_RDCLI6 … #define mmDAGB6_RDCLI6_BASE_IDX … #define mmDAGB6_RDCLI7 … #define mmDAGB6_RDCLI7_BASE_IDX … #define mmDAGB6_RDCLI8 … #define mmDAGB6_RDCLI8_BASE_IDX … #define mmDAGB6_RDCLI9 … #define mmDAGB6_RDCLI9_BASE_IDX … #define mmDAGB6_RDCLI10 … #define mmDAGB6_RDCLI10_BASE_IDX … #define mmDAGB6_RDCLI11 … #define mmDAGB6_RDCLI11_BASE_IDX … #define mmDAGB6_RDCLI12 … #define mmDAGB6_RDCLI12_BASE_IDX … #define mmDAGB6_RDCLI13 … #define mmDAGB6_RDCLI13_BASE_IDX … #define mmDAGB6_RDCLI14 … #define mmDAGB6_RDCLI14_BASE_IDX … #define mmDAGB6_RDCLI15 … #define mmDAGB6_RDCLI15_BASE_IDX … #define mmDAGB6_RD_CNTL … #define mmDAGB6_RD_CNTL_BASE_IDX … #define mmDAGB6_RD_GMI_CNTL … #define mmDAGB6_RD_GMI_CNTL_BASE_IDX … #define mmDAGB6_RD_ADDR_DAGB … #define mmDAGB6_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB6_RD_CGTT_CLK_CTRL … #define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB6_RD_VC0_CNTL … #define mmDAGB6_RD_VC0_CNTL_BASE_IDX … #define mmDAGB6_RD_VC1_CNTL … #define mmDAGB6_RD_VC1_CNTL_BASE_IDX … #define mmDAGB6_RD_VC2_CNTL … #define mmDAGB6_RD_VC2_CNTL_BASE_IDX … #define mmDAGB6_RD_VC3_CNTL … #define mmDAGB6_RD_VC3_CNTL_BASE_IDX … #define mmDAGB6_RD_VC4_CNTL … #define mmDAGB6_RD_VC4_CNTL_BASE_IDX … #define mmDAGB6_RD_VC5_CNTL … #define mmDAGB6_RD_VC5_CNTL_BASE_IDX … #define mmDAGB6_RD_VC6_CNTL … #define mmDAGB6_RD_VC6_CNTL_BASE_IDX … #define mmDAGB6_RD_VC7_CNTL … #define mmDAGB6_RD_VC7_CNTL_BASE_IDX … #define mmDAGB6_RD_CNTL_MISC … #define mmDAGB6_RD_CNTL_MISC_BASE_IDX … #define mmDAGB6_RD_TLB_CREDIT … #define mmDAGB6_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB6_RDCLI_ASK_PENDING … #define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB6_RDCLI_GO_PENDING … #define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB6_RDCLI_GBLSEND_PENDING … #define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB6_RDCLI_TLB_PENDING … #define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB6_RDCLI_OARB_PENDING … #define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB6_RDCLI_OSD_PENDING … #define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB6_WRCLI0 … #define mmDAGB6_WRCLI0_BASE_IDX … #define mmDAGB6_WRCLI1 … #define mmDAGB6_WRCLI1_BASE_IDX … #define mmDAGB6_WRCLI2 … #define mmDAGB6_WRCLI2_BASE_IDX … #define mmDAGB6_WRCLI3 … #define mmDAGB6_WRCLI3_BASE_IDX … #define mmDAGB6_WRCLI4 … #define mmDAGB6_WRCLI4_BASE_IDX … #define mmDAGB6_WRCLI5 … #define mmDAGB6_WRCLI5_BASE_IDX … #define mmDAGB6_WRCLI6 … #define mmDAGB6_WRCLI6_BASE_IDX … #define mmDAGB6_WRCLI7 … #define mmDAGB6_WRCLI7_BASE_IDX … #define mmDAGB6_WRCLI8 … #define mmDAGB6_WRCLI8_BASE_IDX … #define mmDAGB6_WRCLI9 … #define mmDAGB6_WRCLI9_BASE_IDX … #define mmDAGB6_WRCLI10 … #define mmDAGB6_WRCLI10_BASE_IDX … #define mmDAGB6_WRCLI11 … #define mmDAGB6_WRCLI11_BASE_IDX … #define mmDAGB6_WRCLI12 … #define mmDAGB6_WRCLI12_BASE_IDX … #define mmDAGB6_WRCLI13 … #define mmDAGB6_WRCLI13_BASE_IDX … #define mmDAGB6_WRCLI14 … #define mmDAGB6_WRCLI14_BASE_IDX … #define mmDAGB6_WRCLI15 … #define mmDAGB6_WRCLI15_BASE_IDX … #define mmDAGB6_WR_CNTL … #define mmDAGB6_WR_CNTL_BASE_IDX … #define mmDAGB6_WR_GMI_CNTL … #define mmDAGB6_WR_GMI_CNTL_BASE_IDX … #define mmDAGB6_WR_ADDR_DAGB … #define mmDAGB6_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB6_WR_CGTT_CLK_CTRL … #define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB6_WR_DATA_DAGB … #define mmDAGB6_WR_DATA_DAGB_BASE_IDX … #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB6_WR_VC0_CNTL … #define mmDAGB6_WR_VC0_CNTL_BASE_IDX … #define mmDAGB6_WR_VC1_CNTL … #define mmDAGB6_WR_VC1_CNTL_BASE_IDX … #define mmDAGB6_WR_VC2_CNTL … #define mmDAGB6_WR_VC2_CNTL_BASE_IDX … #define mmDAGB6_WR_VC3_CNTL … #define mmDAGB6_WR_VC3_CNTL_BASE_IDX … #define mmDAGB6_WR_VC4_CNTL … #define mmDAGB6_WR_VC4_CNTL_BASE_IDX … #define mmDAGB6_WR_VC5_CNTL … #define mmDAGB6_WR_VC5_CNTL_BASE_IDX … #define mmDAGB6_WR_VC6_CNTL … #define mmDAGB6_WR_VC6_CNTL_BASE_IDX … #define mmDAGB6_WR_VC7_CNTL … #define mmDAGB6_WR_VC7_CNTL_BASE_IDX … #define mmDAGB6_WR_CNTL_MISC … #define mmDAGB6_WR_CNTL_MISC_BASE_IDX … #define mmDAGB6_WR_TLB_CREDIT … #define mmDAGB6_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB6_WR_DATA_CREDIT … #define mmDAGB6_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB6_WR_MISC_CREDIT … #define mmDAGB6_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB6_WRCLI_ASK_PENDING … #define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_GO_PENDING … #define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_GBLSEND_PENDING … #define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_TLB_PENDING … #define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_OARB_PENDING … #define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_OSD_PENDING … #define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_DBUS_ASK_PENDING … #define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB6_WRCLI_DBUS_GO_PENDING … #define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB6_DAGB_DLY … #define mmDAGB6_DAGB_DLY_BASE_IDX … #define mmDAGB6_CNTL_MISC … #define mmDAGB6_CNTL_MISC_BASE_IDX … #define mmDAGB6_CNTL_MISC2 … #define mmDAGB6_CNTL_MISC2_BASE_IDX … #define mmDAGB6_FIFO_EMPTY … #define mmDAGB6_FIFO_EMPTY_BASE_IDX … #define mmDAGB6_FIFO_FULL … #define mmDAGB6_FIFO_FULL_BASE_IDX … #define mmDAGB6_WR_CREDITS_FULL … #define mmDAGB6_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB6_RD_CREDITS_FULL … #define mmDAGB6_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB6_PERFCOUNTER_LO … #define mmDAGB6_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB6_PERFCOUNTER_HI … #define mmDAGB6_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB6_PERFCOUNTER0_CFG … #define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB6_PERFCOUNTER1_CFG … #define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB6_PERFCOUNTER2_CFG … #define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB6_PERFCOUNTER_RSLT_CNTL … #define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB6_RESERVE0 … #define mmDAGB6_RESERVE0_BASE_IDX … #define mmDAGB6_RESERVE1 … #define mmDAGB6_RESERVE1_BASE_IDX … #define mmDAGB6_RESERVE2 … #define mmDAGB6_RESERVE2_BASE_IDX … #define mmDAGB6_RESERVE3 … #define mmDAGB6_RESERVE3_BASE_IDX … #define mmDAGB6_RESERVE4 … #define mmDAGB6_RESERVE4_BASE_IDX … #define mmDAGB6_RESERVE5 … #define mmDAGB6_RESERVE5_BASE_IDX … #define mmDAGB6_RESERVE6 … #define mmDAGB6_RESERVE6_BASE_IDX … #define mmDAGB6_RESERVE7 … #define mmDAGB6_RESERVE7_BASE_IDX … #define mmDAGB6_RESERVE8 … #define mmDAGB6_RESERVE8_BASE_IDX … #define mmDAGB6_RESERVE9 … #define mmDAGB6_RESERVE9_BASE_IDX … #define mmDAGB6_RESERVE10 … #define mmDAGB6_RESERVE10_BASE_IDX … #define mmDAGB6_RESERVE11 … #define mmDAGB6_RESERVE11_BASE_IDX … #define mmDAGB6_RESERVE12 … #define mmDAGB6_RESERVE12_BASE_IDX … #define mmDAGB6_RESERVE13 … #define mmDAGB6_RESERVE13_BASE_IDX … // addressBlock: mmhub_dagb_dagbdec7 // base address: 0x74400 #define mmDAGB7_RDCLI0 … #define mmDAGB7_RDCLI0_BASE_IDX … #define mmDAGB7_RDCLI1 … #define mmDAGB7_RDCLI1_BASE_IDX … #define mmDAGB7_RDCLI2 … #define mmDAGB7_RDCLI2_BASE_IDX … #define mmDAGB7_RDCLI3 … #define mmDAGB7_RDCLI3_BASE_IDX … #define mmDAGB7_RDCLI4 … #define mmDAGB7_RDCLI4_BASE_IDX … #define mmDAGB7_RDCLI5 … #define mmDAGB7_RDCLI5_BASE_IDX … #define mmDAGB7_RDCLI6 … #define mmDAGB7_RDCLI6_BASE_IDX … #define mmDAGB7_RDCLI7 … #define mmDAGB7_RDCLI7_BASE_IDX … #define mmDAGB7_RDCLI8 … #define mmDAGB7_RDCLI8_BASE_IDX … #define mmDAGB7_RDCLI9 … #define mmDAGB7_RDCLI9_BASE_IDX … #define mmDAGB7_RDCLI10 … #define mmDAGB7_RDCLI10_BASE_IDX … #define mmDAGB7_RDCLI11 … #define mmDAGB7_RDCLI11_BASE_IDX … #define mmDAGB7_RDCLI12 … #define mmDAGB7_RDCLI12_BASE_IDX … #define mmDAGB7_RDCLI13 … #define mmDAGB7_RDCLI13_BASE_IDX … #define mmDAGB7_RDCLI14 … #define mmDAGB7_RDCLI14_BASE_IDX … #define mmDAGB7_RDCLI15 … #define mmDAGB7_RDCLI15_BASE_IDX … #define mmDAGB7_RD_CNTL … #define mmDAGB7_RD_CNTL_BASE_IDX … #define mmDAGB7_RD_GMI_CNTL … #define mmDAGB7_RD_GMI_CNTL_BASE_IDX … #define mmDAGB7_RD_ADDR_DAGB … #define mmDAGB7_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB7_RD_CGTT_CLK_CTRL … #define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB7_RD_VC0_CNTL … #define mmDAGB7_RD_VC0_CNTL_BASE_IDX … #define mmDAGB7_RD_VC1_CNTL … #define mmDAGB7_RD_VC1_CNTL_BASE_IDX … #define mmDAGB7_RD_VC2_CNTL … #define mmDAGB7_RD_VC2_CNTL_BASE_IDX … #define mmDAGB7_RD_VC3_CNTL … #define mmDAGB7_RD_VC3_CNTL_BASE_IDX … #define mmDAGB7_RD_VC4_CNTL … #define mmDAGB7_RD_VC4_CNTL_BASE_IDX … #define mmDAGB7_RD_VC5_CNTL … #define mmDAGB7_RD_VC5_CNTL_BASE_IDX … #define mmDAGB7_RD_VC6_CNTL … #define mmDAGB7_RD_VC6_CNTL_BASE_IDX … #define mmDAGB7_RD_VC7_CNTL … #define mmDAGB7_RD_VC7_CNTL_BASE_IDX … #define mmDAGB7_RD_CNTL_MISC … #define mmDAGB7_RD_CNTL_MISC_BASE_IDX … #define mmDAGB7_RD_TLB_CREDIT … #define mmDAGB7_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB7_RDCLI_ASK_PENDING … #define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB7_RDCLI_GO_PENDING … #define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB7_RDCLI_GBLSEND_PENDING … #define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB7_RDCLI_TLB_PENDING … #define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB7_RDCLI_OARB_PENDING … #define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB7_RDCLI_OSD_PENDING … #define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB7_WRCLI0 … #define mmDAGB7_WRCLI0_BASE_IDX … #define mmDAGB7_WRCLI1 … #define mmDAGB7_WRCLI1_BASE_IDX … #define mmDAGB7_WRCLI2 … #define mmDAGB7_WRCLI2_BASE_IDX … #define mmDAGB7_WRCLI3 … #define mmDAGB7_WRCLI3_BASE_IDX … #define mmDAGB7_WRCLI4 … #define mmDAGB7_WRCLI4_BASE_IDX … #define mmDAGB7_WRCLI5 … #define mmDAGB7_WRCLI5_BASE_IDX … #define mmDAGB7_WRCLI6 … #define mmDAGB7_WRCLI6_BASE_IDX … #define mmDAGB7_WRCLI7 … #define mmDAGB7_WRCLI7_BASE_IDX … #define mmDAGB7_WRCLI8 … #define mmDAGB7_WRCLI8_BASE_IDX … #define mmDAGB7_WRCLI9 … #define mmDAGB7_WRCLI9_BASE_IDX … #define mmDAGB7_WRCLI10 … #define mmDAGB7_WRCLI10_BASE_IDX … #define mmDAGB7_WRCLI11 … #define mmDAGB7_WRCLI11_BASE_IDX … #define mmDAGB7_WRCLI12 … #define mmDAGB7_WRCLI12_BASE_IDX … #define mmDAGB7_WRCLI13 … #define mmDAGB7_WRCLI13_BASE_IDX … #define mmDAGB7_WRCLI14 … #define mmDAGB7_WRCLI14_BASE_IDX … #define mmDAGB7_WRCLI15 … #define mmDAGB7_WRCLI15_BASE_IDX … #define mmDAGB7_WR_CNTL … #define mmDAGB7_WR_CNTL_BASE_IDX … #define mmDAGB7_WR_GMI_CNTL … #define mmDAGB7_WR_GMI_CNTL_BASE_IDX … #define mmDAGB7_WR_ADDR_DAGB … #define mmDAGB7_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB7_WR_CGTT_CLK_CTRL … #define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB7_WR_DATA_DAGB … #define mmDAGB7_WR_DATA_DAGB_BASE_IDX … #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB7_WR_VC0_CNTL … #define mmDAGB7_WR_VC0_CNTL_BASE_IDX … #define mmDAGB7_WR_VC1_CNTL … #define mmDAGB7_WR_VC1_CNTL_BASE_IDX … #define mmDAGB7_WR_VC2_CNTL … #define mmDAGB7_WR_VC2_CNTL_BASE_IDX … #define mmDAGB7_WR_VC3_CNTL … #define mmDAGB7_WR_VC3_CNTL_BASE_IDX … #define mmDAGB7_WR_VC4_CNTL … #define mmDAGB7_WR_VC4_CNTL_BASE_IDX … #define mmDAGB7_WR_VC5_CNTL … #define mmDAGB7_WR_VC5_CNTL_BASE_IDX … #define mmDAGB7_WR_VC6_CNTL … #define mmDAGB7_WR_VC6_CNTL_BASE_IDX … #define mmDAGB7_WR_VC7_CNTL … #define mmDAGB7_WR_VC7_CNTL_BASE_IDX … #define mmDAGB7_WR_CNTL_MISC … #define mmDAGB7_WR_CNTL_MISC_BASE_IDX … #define mmDAGB7_WR_TLB_CREDIT … #define mmDAGB7_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB7_WR_DATA_CREDIT … #define mmDAGB7_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB7_WR_MISC_CREDIT … #define mmDAGB7_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB7_WRCLI_ASK_PENDING … #define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_GO_PENDING … #define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_GBLSEND_PENDING … #define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_TLB_PENDING … #define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_OARB_PENDING … #define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_OSD_PENDING … #define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_DBUS_ASK_PENDING … #define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB7_WRCLI_DBUS_GO_PENDING … #define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB7_DAGB_DLY … #define mmDAGB7_DAGB_DLY_BASE_IDX … #define mmDAGB7_CNTL_MISC … #define mmDAGB7_CNTL_MISC_BASE_IDX … #define mmDAGB7_CNTL_MISC2 … #define mmDAGB7_CNTL_MISC2_BASE_IDX … #define mmDAGB7_FIFO_EMPTY … #define mmDAGB7_FIFO_EMPTY_BASE_IDX … #define mmDAGB7_FIFO_FULL … #define mmDAGB7_FIFO_FULL_BASE_IDX … #define mmDAGB7_WR_CREDITS_FULL … #define mmDAGB7_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB7_RD_CREDITS_FULL … #define mmDAGB7_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB7_PERFCOUNTER_LO … #define mmDAGB7_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB7_PERFCOUNTER_HI … #define mmDAGB7_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB7_PERFCOUNTER0_CFG … #define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB7_PERFCOUNTER1_CFG … #define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB7_PERFCOUNTER2_CFG … #define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB7_PERFCOUNTER_RSLT_CNTL … #define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB7_RESERVE0 … #define mmDAGB7_RESERVE0_BASE_IDX … #define mmDAGB7_RESERVE1 … #define mmDAGB7_RESERVE1_BASE_IDX … #define mmDAGB7_RESERVE2 … #define mmDAGB7_RESERVE2_BASE_IDX … #define mmDAGB7_RESERVE3 … #define mmDAGB7_RESERVE3_BASE_IDX … #define mmDAGB7_RESERVE4 … #define mmDAGB7_RESERVE4_BASE_IDX … #define mmDAGB7_RESERVE5 … #define mmDAGB7_RESERVE5_BASE_IDX … #define mmDAGB7_RESERVE6 … #define mmDAGB7_RESERVE6_BASE_IDX … #define mmDAGB7_RESERVE7 … #define mmDAGB7_RESERVE7_BASE_IDX … #define mmDAGB7_RESERVE8 … #define mmDAGB7_RESERVE8_BASE_IDX … #define mmDAGB7_RESERVE9 … #define mmDAGB7_RESERVE9_BASE_IDX … #define mmDAGB7_RESERVE10 … #define mmDAGB7_RESERVE10_BASE_IDX … #define mmDAGB7_RESERVE11 … #define mmDAGB7_RESERVE11_BASE_IDX … #define mmDAGB7_RESERVE12 … #define mmDAGB7_RESERVE12_BASE_IDX … #define mmDAGB7_RESERVE13 … #define mmDAGB7_RESERVE13_BASE_IDX … // addressBlock: mmhub_ea_mmeadec5 // base address: 0x74a00 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_DRAM_RD_GRP2VC_MAP … #define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA5_DRAM_WR_GRP2VC_MAP … #define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA5_DRAM_RD_LAZY … #define mmMMEA5_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA5_DRAM_WR_LAZY … #define mmMMEA5_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA5_DRAM_RD_CAM_CNTL … #define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA5_DRAM_WR_CAM_CNTL … #define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA5_DRAM_PAGE_BURST … #define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_AGE … #define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_AGE … #define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_QUEUING … #define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_QUEUING … #define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_FIXED … #define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_FIXED … #define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_URGENCY … #define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_URGENCY … #define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_GMI_RD_GRP2VC_MAP … #define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA5_GMI_WR_GRP2VC_MAP … #define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA5_GMI_RD_LAZY … #define mmMMEA5_GMI_RD_LAZY_BASE_IDX … #define mmMMEA5_GMI_WR_LAZY … #define mmMMEA5_GMI_WR_LAZY_BASE_IDX … #define mmMMEA5_GMI_RD_CAM_CNTL … #define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA5_GMI_WR_CAM_CNTL … #define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA5_GMI_PAGE_BURST … #define mmMMEA5_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_AGE … #define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_AGE … #define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_QUEUING … #define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_QUEUING … #define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_FIXED … #define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_FIXED … #define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_URGENCY … #define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_URGENCY … #define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR0 … #define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR1 … #define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA5_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR2 … #define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR3 … #define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA5_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR4 … #define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA5_ADDRNORM_BASE_ADDR5 … #define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA5_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA5_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA5_ADDRDEC_BANK_CFG … #define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA5_ADDRDEC_MISC_CFG … #define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA5_IO_RD_CLI2GRP_MAP0 … #define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_IO_RD_CLI2GRP_MAP1 … #define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_IO_WR_CLI2GRP_MAP0 … #define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA5_IO_WR_CLI2GRP_MAP1 … #define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA5_IO_RD_COMBINE_FLUSH … #define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA5_IO_WR_COMBINE_FLUSH … #define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA5_IO_GROUP_BURST … #define mmMMEA5_IO_GROUP_BURST_BASE_IDX … #define mmMMEA5_IO_RD_PRI_AGE … #define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA5_IO_WR_PRI_AGE … #define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA5_IO_RD_PRI_QUEUING … #define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA5_IO_WR_PRI_QUEUING … #define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA5_IO_RD_PRI_FIXED … #define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA5_IO_WR_PRI_FIXED … #define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA5_IO_RD_PRI_URGENCY … #define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA5_IO_WR_PRI_URGENCY … #define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA5_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA5_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA5_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA5_SDP_ARB_DRAM … #define mmMMEA5_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA5_SDP_ARB_GMI … #define mmMMEA5_SDP_ARB_GMI_BASE_IDX … #define mmMMEA5_SDP_ARB_FINAL … #define mmMMEA5_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA5_SDP_DRAM_PRIORITY … #define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA5_SDP_GMI_PRIORITY … #define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA5_SDP_IO_PRIORITY … #define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA5_SDP_CREDITS … #define mmMMEA5_SDP_CREDITS_BASE_IDX … #define mmMMEA5_SDP_TAG_RESERVE0 … #define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA5_SDP_TAG_RESERVE1 … #define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA5_SDP_VCC_RESERVE0 … #define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA5_SDP_VCC_RESERVE1 … #define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA5_SDP_VCD_RESERVE0 … #define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA5_SDP_VCD_RESERVE1 … #define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA5_SDP_REQ_CNTL … #define mmMMEA5_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA5_MISC … #define mmMMEA5_MISC_BASE_IDX … #define mmMMEA5_LATENCY_SAMPLING … #define mmMMEA5_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA5_PERFCOUNTER_LO … #define mmMMEA5_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA5_PERFCOUNTER_HI … #define mmMMEA5_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA5_PERFCOUNTER0_CFG … #define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA5_PERFCOUNTER1_CFG … #define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA5_PERFCOUNTER_RSLT_CNTL … #define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA5_EDC_CNT … #define mmMMEA5_EDC_CNT_BASE_IDX … #define mmMMEA5_EDC_CNT2 … #define mmMMEA5_EDC_CNT2_BASE_IDX … #define mmMMEA5_DSM_CNTL … #define mmMMEA5_DSM_CNTL_BASE_IDX … #define mmMMEA5_DSM_CNTLA … #define mmMMEA5_DSM_CNTLA_BASE_IDX … #define mmMMEA5_DSM_CNTLB … #define mmMMEA5_DSM_CNTLB_BASE_IDX … #define mmMMEA5_DSM_CNTL2 … #define mmMMEA5_DSM_CNTL2_BASE_IDX … #define mmMMEA5_DSM_CNTL2A … #define mmMMEA5_DSM_CNTL2A_BASE_IDX … #define mmMMEA5_DSM_CNTL2B … #define mmMMEA5_DSM_CNTL2B_BASE_IDX … #define mmMMEA5_CGTT_CLK_CTRL … #define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA5_EDC_MODE … #define mmMMEA5_EDC_MODE_BASE_IDX … #define mmMMEA5_ERR_STATUS … #define mmMMEA5_ERR_STATUS_BASE_IDX … #define mmMMEA5_MISC2 … #define mmMMEA5_MISC2_BASE_IDX … #define mmMMEA5_ADDRDEC_SELECT … #define mmMMEA5_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA5_EDC_CNT3 … #define mmMMEA5_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec6 // base address: 0x74f00 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_DRAM_RD_GRP2VC_MAP … #define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA6_DRAM_WR_GRP2VC_MAP … #define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA6_DRAM_RD_LAZY … #define mmMMEA6_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA6_DRAM_WR_LAZY … #define mmMMEA6_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA6_DRAM_RD_CAM_CNTL … #define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA6_DRAM_WR_CAM_CNTL … #define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA6_DRAM_PAGE_BURST … #define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_AGE … #define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_AGE … #define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_QUEUING … #define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_QUEUING … #define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_FIXED … #define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_FIXED … #define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_URGENCY … #define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_URGENCY … #define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_GMI_RD_GRP2VC_MAP … #define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA6_GMI_WR_GRP2VC_MAP … #define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA6_GMI_RD_LAZY … #define mmMMEA6_GMI_RD_LAZY_BASE_IDX … #define mmMMEA6_GMI_WR_LAZY … #define mmMMEA6_GMI_WR_LAZY_BASE_IDX … #define mmMMEA6_GMI_RD_CAM_CNTL … #define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA6_GMI_WR_CAM_CNTL … #define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA6_GMI_PAGE_BURST … #define mmMMEA6_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_AGE … #define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_AGE … #define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_QUEUING … #define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_QUEUING … #define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_FIXED … #define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_FIXED … #define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_URGENCY … #define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_URGENCY … #define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR0 … #define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR1 … #define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA6_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR2 … #define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR3 … #define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA6_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR4 … #define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA6_ADDRNORM_BASE_ADDR5 … #define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA6_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA6_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA6_ADDRDEC_BANK_CFG … #define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA6_ADDRDEC_MISC_CFG … #define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA6_IO_RD_CLI2GRP_MAP0 … #define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_IO_RD_CLI2GRP_MAP1 … #define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_IO_WR_CLI2GRP_MAP0 … #define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA6_IO_WR_CLI2GRP_MAP1 … #define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA6_IO_RD_COMBINE_FLUSH … #define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA6_IO_WR_COMBINE_FLUSH … #define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA6_IO_GROUP_BURST … #define mmMMEA6_IO_GROUP_BURST_BASE_IDX … #define mmMMEA6_IO_RD_PRI_AGE … #define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA6_IO_WR_PRI_AGE … #define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA6_IO_RD_PRI_QUEUING … #define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA6_IO_WR_PRI_QUEUING … #define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA6_IO_RD_PRI_FIXED … #define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA6_IO_WR_PRI_FIXED … #define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA6_IO_RD_PRI_URGENCY … #define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA6_IO_WR_PRI_URGENCY … #define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA6_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA6_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA6_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA6_SDP_ARB_DRAM … #define mmMMEA6_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA6_SDP_ARB_GMI … #define mmMMEA6_SDP_ARB_GMI_BASE_IDX … #define mmMMEA6_SDP_ARB_FINAL … #define mmMMEA6_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA6_SDP_DRAM_PRIORITY … #define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA6_SDP_GMI_PRIORITY … #define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA6_SDP_IO_PRIORITY … #define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA6_SDP_CREDITS … #define mmMMEA6_SDP_CREDITS_BASE_IDX … #define mmMMEA6_SDP_TAG_RESERVE0 … #define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA6_SDP_TAG_RESERVE1 … #define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA6_SDP_VCC_RESERVE0 … #define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA6_SDP_VCC_RESERVE1 … #define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA6_SDP_VCD_RESERVE0 … #define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA6_SDP_VCD_RESERVE1 … #define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA6_SDP_REQ_CNTL … #define mmMMEA6_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA6_MISC … #define mmMMEA6_MISC_BASE_IDX … #define mmMMEA6_LATENCY_SAMPLING … #define mmMMEA6_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA6_PERFCOUNTER_LO … #define mmMMEA6_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA6_PERFCOUNTER_HI … #define mmMMEA6_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA6_PERFCOUNTER0_CFG … #define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA6_PERFCOUNTER1_CFG … #define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA6_PERFCOUNTER_RSLT_CNTL … #define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA6_EDC_CNT … #define mmMMEA6_EDC_CNT_BASE_IDX … #define mmMMEA6_EDC_CNT2 … #define mmMMEA6_EDC_CNT2_BASE_IDX … #define mmMMEA6_DSM_CNTL … #define mmMMEA6_DSM_CNTL_BASE_IDX … #define mmMMEA6_DSM_CNTLA … #define mmMMEA6_DSM_CNTLA_BASE_IDX … #define mmMMEA6_DSM_CNTLB … #define mmMMEA6_DSM_CNTLB_BASE_IDX … #define mmMMEA6_DSM_CNTL2 … #define mmMMEA6_DSM_CNTL2_BASE_IDX … #define mmMMEA6_DSM_CNTL2A … #define mmMMEA6_DSM_CNTL2A_BASE_IDX … #define mmMMEA6_DSM_CNTL2B … #define mmMMEA6_DSM_CNTL2B_BASE_IDX … #define mmMMEA6_CGTT_CLK_CTRL … #define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA6_EDC_MODE … #define mmMMEA6_EDC_MODE_BASE_IDX … #define mmMMEA6_ERR_STATUS … #define mmMMEA6_ERR_STATUS_BASE_IDX … #define mmMMEA6_MISC2 … #define mmMMEA6_MISC2_BASE_IDX … #define mmMMEA6_ADDRDEC_SELECT … #define mmMMEA6_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA6_EDC_CNT3 … #define mmMMEA6_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_ea_mmeadec7 // base address: 0x75400 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_DRAM_RD_GRP2VC_MAP … #define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA7_DRAM_WR_GRP2VC_MAP … #define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA7_DRAM_RD_LAZY … #define mmMMEA7_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA7_DRAM_WR_LAZY … #define mmMMEA7_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA7_DRAM_RD_CAM_CNTL … #define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA7_DRAM_WR_CAM_CNTL … #define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA7_DRAM_PAGE_BURST … #define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_AGE … #define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_AGE … #define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_QUEUING … #define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_QUEUING … #define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_FIXED … #define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_FIXED … #define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_URGENCY … #define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_URGENCY … #define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_GMI_RD_CLI2GRP_MAP0 … #define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_GMI_RD_CLI2GRP_MAP1 … #define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_GMI_WR_CLI2GRP_MAP0 … #define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_GMI_WR_CLI2GRP_MAP1 … #define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_GMI_RD_GRP2VC_MAP … #define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA7_GMI_WR_GRP2VC_MAP … #define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA7_GMI_RD_LAZY … #define mmMMEA7_GMI_RD_LAZY_BASE_IDX … #define mmMMEA7_GMI_WR_LAZY … #define mmMMEA7_GMI_WR_LAZY_BASE_IDX … #define mmMMEA7_GMI_RD_CAM_CNTL … #define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX … #define mmMMEA7_GMI_WR_CAM_CNTL … #define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX … #define mmMMEA7_GMI_PAGE_BURST … #define mmMMEA7_GMI_PAGE_BURST_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_AGE … #define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_AGE … #define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_QUEUING … #define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_QUEUING … #define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_FIXED … #define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_FIXED … #define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_URGENCY … #define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_URGENCY … #define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING … #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING … #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1 … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2 … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3 … #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1 … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2 … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3 … #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR0 … #define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR1 … #define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA7_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR2 … #define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR2 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR3 … #define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR3 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX … #define mmMMEA7_ADDRNORM_OFFSET_ADDR3 … #define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR4 … #define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR4 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX … #define mmMMEA7_ADDRNORM_BASE_ADDR5 … #define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX … #define mmMMEA7_ADDRNORM_LIMIT_ADDR5 … #define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX … #define mmMMEA7_ADDRNORM_OFFSET_ADDR5 … #define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX … #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL … #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX … #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG … #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA7_ADDRDEC_BANK_CFG … #define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA7_ADDRDEC_MISC_CFG … #define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 … #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE … #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 … #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 … #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 … #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 … #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 … #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 … #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 … #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 … #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 … #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 … #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 … #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 … #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 … #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 … #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 … #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 … #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 … #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 … #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 … #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_RM_SEL_CS01 … #define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_RM_SEL_CS23 … #define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX … #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 … #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX … #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 … #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX … #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL … #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX … #define mmMMEA7_IO_RD_CLI2GRP_MAP0 … #define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_IO_RD_CLI2GRP_MAP1 … #define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_IO_WR_CLI2GRP_MAP0 … #define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA7_IO_WR_CLI2GRP_MAP1 … #define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA7_IO_RD_COMBINE_FLUSH … #define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA7_IO_WR_COMBINE_FLUSH … #define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA7_IO_GROUP_BURST … #define mmMMEA7_IO_GROUP_BURST_BASE_IDX … #define mmMMEA7_IO_RD_PRI_AGE … #define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA7_IO_WR_PRI_AGE … #define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA7_IO_RD_PRI_QUEUING … #define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA7_IO_WR_PRI_QUEUING … #define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA7_IO_RD_PRI_FIXED … #define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA7_IO_WR_PRI_FIXED … #define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA7_IO_RD_PRI_URGENCY … #define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA7_IO_WR_PRI_URGENCY … #define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA7_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA7_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA7_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA7_SDP_ARB_DRAM … #define mmMMEA7_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA7_SDP_ARB_GMI … #define mmMMEA7_SDP_ARB_GMI_BASE_IDX … #define mmMMEA7_SDP_ARB_FINAL … #define mmMMEA7_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA7_SDP_DRAM_PRIORITY … #define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA7_SDP_GMI_PRIORITY … #define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX … #define mmMMEA7_SDP_IO_PRIORITY … #define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA7_SDP_CREDITS … #define mmMMEA7_SDP_CREDITS_BASE_IDX … #define mmMMEA7_SDP_TAG_RESERVE0 … #define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA7_SDP_TAG_RESERVE1 … #define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA7_SDP_VCC_RESERVE0 … #define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA7_SDP_VCC_RESERVE1 … #define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA7_SDP_VCD_RESERVE0 … #define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA7_SDP_VCD_RESERVE1 … #define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA7_SDP_REQ_CNTL … #define mmMMEA7_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA7_MISC … #define mmMMEA7_MISC_BASE_IDX … #define mmMMEA7_LATENCY_SAMPLING … #define mmMMEA7_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA7_PERFCOUNTER_LO … #define mmMMEA7_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA7_PERFCOUNTER_HI … #define mmMMEA7_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA7_PERFCOUNTER0_CFG … #define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA7_PERFCOUNTER1_CFG … #define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA7_PERFCOUNTER_RSLT_CNTL … #define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA7_EDC_CNT … #define mmMMEA7_EDC_CNT_BASE_IDX … #define mmMMEA7_EDC_CNT2 … #define mmMMEA7_EDC_CNT2_BASE_IDX … #define mmMMEA7_DSM_CNTL … #define mmMMEA7_DSM_CNTL_BASE_IDX … #define mmMMEA7_DSM_CNTLA … #define mmMMEA7_DSM_CNTLA_BASE_IDX … #define mmMMEA7_DSM_CNTLB … #define mmMMEA7_DSM_CNTLB_BASE_IDX … #define mmMMEA7_DSM_CNTL2 … #define mmMMEA7_DSM_CNTL2_BASE_IDX … #define mmMMEA7_DSM_CNTL2A … #define mmMMEA7_DSM_CNTL2A_BASE_IDX … #define mmMMEA7_DSM_CNTL2B … #define mmMMEA7_DSM_CNTL2B_BASE_IDX … #define mmMMEA7_CGTT_CLK_CTRL … #define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA7_EDC_MODE … #define mmMMEA7_EDC_MODE_BASE_IDX … #define mmMMEA7_ERR_STATUS … #define mmMMEA7_ERR_STATUS_BASE_IDX … #define mmMMEA7_MISC2 … #define mmMMEA7_MISC2_BASE_IDX … #define mmMMEA7_ADDRDEC_SELECT … #define mmMMEA7_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA7_EDC_CNT3 … #define mmMMEA7_EDC_CNT3_BASE_IDX … // addressBlock: mmhub_pctldec1 // base address: 0x76300 #define mmPCTL1_CTRL … #define mmPCTL1_CTRL_BASE_IDX … #define mmPCTL1_MMHUB_DEEPSLEEP_IB … #define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE … #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB … #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX … #define mmPCTL1_PG_IGNORE_DEEPSLEEP … #define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB … #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL1_SLICE0_CFG_DAGB_BUSY … #define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL1_SLICE0_CFG_DS_ALLOW … #define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB … #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL1_SLICE1_CFG_DAGB_BUSY … #define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL1_SLICE1_CFG_DS_ALLOW … #define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB … #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL1_SLICE2_CFG_DAGB_BUSY … #define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL1_SLICE2_CFG_DS_ALLOW … #define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB … #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL1_SLICE3_CFG_DAGB_BUSY … #define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL1_SLICE3_CFG_DS_ALLOW … #define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB … #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL1_SLICE4_CFG_DAGB_BUSY … #define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX … #define mmPCTL1_SLICE4_CFG_DS_ALLOW … #define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB … #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL1_UTCL2_MISC … #define mmPCTL1_UTCL2_MISC_BASE_IDX … #define mmPCTL1_SLICE0_MISC … #define mmPCTL1_SLICE0_MISC_BASE_IDX … #define mmPCTL1_SLICE1_MISC … #define mmPCTL1_SLICE1_MISC_BASE_IDX … #define mmPCTL1_SLICE2_MISC … #define mmPCTL1_SLICE2_MISC_BASE_IDX … #define mmPCTL1_SLICE3_MISC … #define mmPCTL1_SLICE3_MISC_BASE_IDX … #define mmPCTL1_SLICE4_MISC … #define mmPCTL1_SLICE4_MISC_BASE_IDX … #define mmPCTL1_UTCL2_RENG_EXECUTE … #define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_SLICE0_RENG_EXECUTE … #define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_SLICE1_RENG_EXECUTE … #define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_SLICE2_RENG_EXECUTE … #define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_SLICE3_RENG_EXECUTE … #define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_SLICE4_RENG_EXECUTE … #define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX … #define mmPCTL1_UTCL2_RENG_RAM_INDEX … #define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_UTCL2_RENG_RAM_DATA … #define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_SLICE0_RENG_RAM_INDEX … #define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_SLICE0_RENG_RAM_DATA … #define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_SLICE1_RENG_RAM_INDEX … #define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_SLICE1_RENG_RAM_DATA … #define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_SLICE2_RENG_RAM_INDEX … #define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_SLICE2_RENG_RAM_DATA … #define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_SLICE3_RENG_RAM_INDEX … #define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_SLICE3_RENG_RAM_DATA … #define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_SLICE4_RENG_RAM_INDEX … #define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL1_SLICE4_RENG_RAM_DATA … #define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1dec:1 // base address: 0x76500 #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS … #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1pldec:1 // base address: 0x76580 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_l1tlb_vml1prdec:1 // base address: 0x765c0 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO … #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI … #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2dec:1 // base address: 0x76600 #define mmATCL2_1_ATC_L2_CNTL … #define mmATCL2_1_ATC_L2_CNTL_BASE_IDX … #define mmATCL2_1_ATC_L2_CNTL2 … #define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_DATA0 … #define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_DATA1 … #define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_DATA2 … #define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX … #define mmATCL2_1_ATC_L2_CNTL3 … #define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX … #define mmATCL2_1_ATC_L2_STATUS … #define mmATCL2_1_ATC_L2_STATUS_BASE_IDX … #define mmATCL2_1_ATC_L2_STATUS2 … #define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX … #define mmATCL2_1_ATC_L2_STATUS3 … #define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX … #define mmATCL2_1_ATC_L2_MISC_CG … #define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX … #define mmATCL2_1_ATC_L2_MEM_POWER_LS … #define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX … #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL … #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX … #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX … #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL … #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX … #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL … #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX … #define mmATCL2_1_ATC_L2_CNTL4 … #define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX … #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES … #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pfdec:1 // base address: 0x76700 #define mmVML2PF1_VM_L2_CNTL … #define mmVML2PF1_VM_L2_CNTL_BASE_IDX … #define mmVML2PF1_VM_L2_CNTL2 … #define mmVML2PF1_VM_L2_CNTL2_BASE_IDX … #define mmVML2PF1_VM_L2_CNTL3 … #define mmVML2PF1_VM_L2_CNTL3_BASE_IDX … #define mmVML2PF1_VM_L2_STATUS … #define mmVML2PF1_VM_L2_STATUS_BASE_IDX … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define mmVML2PF1_VM_L2_CNTL4 … #define mmVML2PF1_VM_L2_CNTL4_BASE_IDX … #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES … #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID … #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 … #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL … #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL … #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2vcdec:1 // base address: 0x76800 #define mmVML2VC1_VM_CONTEXT0_CNTL … #define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_CNTL … #define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_CNTL … #define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_CNTL … #define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_CNTL … #define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_CNTL … #define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_CNTL … #define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_CNTL … #define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_CNTL … #define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_CNTL … #define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_CNTL … #define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_CNTL … #define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_CNTL … #define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_CNTL … #define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_CNTL … #define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_CNTL … #define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX … #define mmVML2VC1_VM_CONTEXTS_DISABLE … #define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM … #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ … #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK … #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedpfdec:1 // base address: 0x76b90 #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE … #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT … #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL … #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB … #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_FB_OFFSET … #define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_STEERING … #define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX … #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ … #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define mmVMSHAREDPF1_MC_MEM_POWER_LS … #define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_APT_CNTL … #define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL … #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE … #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL … #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedvcdec:1 // base address: 0x76c00 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE … #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP … #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_AGP_TOP … #define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_AGP_BOT … #define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_AGP_BASE … #define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL … #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vmsharedhvdec:1 // base address: 0x76c80 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 … #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 … #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 … #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 … #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 … #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX … #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER … #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 … #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL … #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX … #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID … #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE … #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 // base address: 0x76dc0 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO … #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX … #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI … #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 // base address: 0x76dd0 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG … #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG … #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL … #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2pldec:1 // base address: 0x76e00 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_utcl2_vml2prdec:1 // base address: 0x76e40 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO … #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI … #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX … #endif
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