/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_atombios.h" #include "nbio_v7_4.h" #include "amdgpu_ras.h" #include "nbio/nbio_7_4_offset.h" #include "nbio/nbio_7_4_sh_mask.h" #include "nbio/nbio_7_4_0_smn.h" #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" #include <uapi/linux/kfd_ioctl.h> #define smnPCIE_LC_CNTL … #define smnPCIE_LC_CNTL3 … #define smnPCIE_LC_CNTL6 … #define smnPCIE_LC_CNTL7 … #define smnNBIF_MGCG_CTRL_LCLK … #define smnRCC_BIF_STRAP3 … #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK … #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK … #define smnRCC_BIF_STRAP5 … #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK … #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 … #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK … #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP … #define smnPSWUSP0_PCIE_LC_CNTL2 … #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL … #define smnRCC_BIF_STRAP2 … #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK … #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT … #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT … #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT … /* * These are nbio v7_4_1 registers mask. Temporarily define these here since * nbio v7_4_1 header is incomplete. */ #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK … #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK … #define mmBIF_MMSCH1_DOORBELL_RANGE … #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX … //BIF_MMSCH1_DOORBELL_RANGE #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT … #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT … #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK … #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK … #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK … #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK … #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE … #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX … //BIF_MMSCH1_DOORBELL_ALDE_RANGE #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT … #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT … #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK … #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK … #define mmRCC_DEV0_EPF0_STRAP0_ALDE … #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX … #define mmBIF_DOORBELL_INT_CNTL_ALDE … #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX … #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT … #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK … #define mmBIF_INTR_CNTL_ALDE … #define mmBIF_INTR_CNTL_ALDE_BASE_IDX … static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status); static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) { … } static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) { … } static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) { … } static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) { … } static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index, int doorbell_size) { … } static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index, int instance) { … } static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { … } static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { … } static void nbio_v7_4_ih_control(struct amdgpu_device *adev) { … } static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) { … } const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = …; static void nbio_v7_4_init_registers(struct amdgpu_device *adev) { … } static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) { … } static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) { … } static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = …; static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = …; static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) { … } static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) { … } #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 … #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE … #define smnRAS_GLOBAL_STATUS_LO_ALDE … static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) { … } static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, bool enable) { … } const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = …; struct amdgpu_nbio_ras nbio_v7_4_ras = …; #ifdef CONFIG_PCIEASPM static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) { … } #endif static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) { … } #define MMIO_REG_HOLE_OFFSET … static void nbio_v7_4_set_reg_remap(struct amdgpu_device *adev) { … } const struct amdgpu_nbio_funcs nbio_v7_4_funcs = …;
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