/* SPDX-License-Identifier: GPL-2.0+ */ /* * Register Map - Based on PolarBear_CSRs.RevA.xlsx (2023-04-21) * * Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company. */ #ifndef MFD_IDTRC38XXX_REG #define MFD_IDTRC38XXX_REG /* GLOBAL */ #define SOFT_RESET_CTRL … #define MISC_CTRL … #define APLL_REINIT … #define APLL_REINIT_VFC3A … #define DEVICE_ID … #define DEVICE_ID_MASK … #define DEVICE_ID_SHIFT … /* FOD */ #define FOD_0 … #define FOD_0_VFC3A … #define FOD_1 … #define FOD_1_VFC3A … #define FOD_2 … #define FOD_2_VFC3A … /* TDCAPLL */ #define TDC_CTRL … #define TDC_ENABLE_CTRL … #define TDC_DAC_CAL_CTRL … #define TDC_EN … #define TDC_DAC_RECAL_REQ … #define TDC_DAC_RECAL_REQ_VFC3A … #define TDC_FB_DIV_INT_CNFG … #define TDC_FB_DIV_INT_CNFG_VFC3A … #define TDC_FB_DIV_INT_MASK … #define TDC_REF_DIV_CNFG … #define TDC_REF_DIV_CNFG_VFC3A … #define TDC_REF_DIV_CONFIG_MASK … /* TIME SYNC CHANNEL */ #define TIME_CLOCK_SRC … #define TIME_CLOCK_COUNT … #define TIME_CLOCK_COUNT_MASK … #define SUB_SYNC_GEN_CNFG … #define TOD_COUNTER_READ_REQ … #define TOD_COUNTER_READ_REQ_VFC3A … #define TOD_SYNC_LOAD_VAL_CTRL … #define TOD_SYNC_LOAD_VAL_CTRL_VFC3A … #define SYNC_COUNTER_MASK … #define SUB_SYNC_COUNTER_MASK … #define TOD_SYNC_LOAD_REQ_CTRL … #define TOD_SYNC_LOAD_REQ_CTRL_VFC3A … #define SYNC_LOAD_ENABLE … #define SUB_SYNC_LOAD_ENABLE … #define SYNC_LOAD_REQ … #define LPF_MODE_CNFG … #define LPF_MODE_CNFG_VFC3A … enum lpf_mode { … }; #define LPF_CTRL … #define LPF_CTRL_VFC3A … #define LPF_EN … #define LPF_BW_CNFG … #define LPF_BW_SHIFT … #define LPF_BW_MULT … #define LPF_BW_SHIFT_DEFAULT … #define LPF_BW_MULT_DEFAULT … #define LPF_BW_SHIFT_1PPS … #define LPF_WR_PHASE_CTRL … #define LPF_WR_PHASE_CTRL_VFC3A … #define LPF_WR_FREQ_CTRL … #define LPF_WR_FREQ_CTRL_VFC3A … #define TIME_CLOCK_TDC_FANOUT_CNFG … #define TIME_SYNC_TO_TDC_EN … #define SIG1_MUX_SEL_MASK … #define SIG2_MUX_SEL_MASK … enum tdc_mux_sel { … }; #define TIME_CLOCK_MEAS_CNFG … #define TDC_MEAS_MODE … enum tdc_meas_mode { … }; #define TIME_CLOCK_MEAS_DIV_CNFG … #define TIME_REF_DIV_MASK … #define TIME_CLOCK_MEAS_CTRL … #define TDC_MEAS_EN … #define TDC_MEAS_START … #define TDC_FIFO_READ_REQ … #define TDC_FIFO_READ … #define COARSE_MEAS_MASK … #define FINE_MEAS_MASK … #define TDC_FIFO_CTRL … #define FIFO_CLEAR … #define TDC_FIFO_STS … #define FIFO_FULL … #define FIFO_EMPTY … #define TDC_FIFO_EVENT … #define FIFO_OVERRUN … /* DPLL */ #define MAX_REFERENCE_INDEX … #define MAX_NUM_REF_PRIORITY … #define MAX_DPLL_INDEX … #define DPLL_STS … #define DPLL_STS_VFC3A … #define DPLL_STATE_STS_MASK … #define DPLL_STATE_STS_SHIFT … #define DPLL_REF_SEL_STS_MASK … #define DPLL_REF_SEL_STS_SHIFT … #define DPLL_REF_PRIORITY_CNFG … #define DPLL_REFX_PRIORITY_DISABLE_MASK … #define DPLL_REF0_PRIORITY_ENABLE_AND_SET_MASK … #define DPLL_REF1_PRIORITY_ENABLE_AND_SET_MASK … #define DPLL_REF2_PRIORITY_ENABLE_AND_SET_MASK … #define DPLL_REF3_PRIORITY_ENABLE_AND_SET_MASK … #define DPLL_REF0_PRIORITY_SHIFT … #define DPLL_REF1_PRIORITY_SHIFT … #define DPLL_REF2_PRIORITY_SHIFT … #define DPLL_REF3_PRIORITY_SHIFT … enum dpll_state { … }; /* REFMON */ #define LOSMON_STS_0 … #define LOSMON_STS_0_VFC3A … #define LOSMON_STS_1 … #define LOSMON_STS_1_VFC3A … #define LOSMON_STS_2 … #define LOSMON_STS_2_VFC3A … #define LOSMON_STS_3 … #define LOSMON_STS_3_VFC3A … #define LOS_STS_MASK … #define FREQMON_STS_0 … #define FREQMON_STS_0_VFC3A … #define FREQMON_STS_1 … #define FREQMON_STS_1_VFC3A … #define FREQMON_STS_2 … #define FREQMON_STS_2_VFC3A … #define FREQMON_STS_3 … #define FREQMON_STS_3_VFC3A … #define FREQ_FAIL_STS_SHIFT … /* Firmware interface */ #define TIME_CLK_FREQ_ADDR … #define XTAL_FREQ_ADDR … /* * Return register address and field mask based on passed in firmware version */ #define IDTFC3_FW_REG(FW, VER, REG) … #define IDTFC3_FW_FIELD(FW, VER, FIELD) … enum fw_version { … }; /* XTAL_FREQ_ADDR/TIME_CLK_FREQ_ADDR */ enum { … }; struct idtfc3_hw_param { … }; struct idtfc3_fwrc { … } __packed; static inline void idtfc3_default_hw_param(struct idtfc3_hw_param *hw_param) { … } static inline int idtfc3_set_hw_param(struct idtfc3_hw_param *hw_param, u16 addr, u8 val) { … } #endif
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