/* SPDX-License-Identifier: GPL-2.0-only */ /* * AMD CS5535/CS5536 definitions * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2009 Andres Salomon <[email protected]> */ #ifndef _CS5535_H #define _CS5535_H #include <asm/msr.h> /* MSRs */ #define MSR_GLIU_P2D_RO0 … #define MSR_LX_GLD_MSR_CONFIG … #define MSR_LX_MSR_PADSEL … #define MSR_GLCP_SYS_RSTPLL … #define MSR_GLCP_DOTPLL … #define MSR_LBAR_SMB … #define MSR_LBAR_GPIO … #define MSR_LBAR_MFGPT … #define MSR_LBAR_ACPI … #define MSR_LBAR_PMS … #define MSR_DIVIL_SOFT_RESET … #define MSR_PIC_YSEL_LOW … #define MSR_PIC_YSEL_HIGH … #define MSR_PIC_ZSEL_LOW … #define MSR_PIC_ZSEL_HIGH … #define MSR_PIC_IRQM_LPC … #define MSR_MFGPT_IRQ … #define MSR_MFGPT_NR … #define MSR_MFGPT_SETUP … #define MSR_RTC_DOMA_OFFSET … #define MSR_RTC_MONA_OFFSET … #define MSR_RTC_CEN_OFFSET … #define MSR_LX_SPARE_MSR … #define MSR_GX_GLD_MSR_CONFIG … #define MSR_GX_MSR_PADSEL … static inline int cs5535_pic_unreqz_select_high(unsigned int group, unsigned int irq) { … } /* PIC registers */ #define CS5536_PIC_INT_SEL1 … #define CS5536_PIC_INT_SEL2 … /* resource sizes */ #define LBAR_GPIO_SIZE … #define LBAR_MFGPT_SIZE … #define LBAR_ACPI_SIZE … #define LBAR_PMS_SIZE … /* * PMC registers (PMS block) * It is only safe to access these registers as dword accesses. * See CS5536 Specification Update erratas 17 & 18 */ #define CS5536_PM_SCLK … #define CS5536_PM_IN_SLPCTL … #define CS5536_PM_WKXD … #define CS5536_PM_WKD … #define CS5536_PM_SSC … /* * PM registers (ACPI block) * It is only safe to access these registers as dword accesses. * See CS5536 Specification Update erratas 17 & 18 */ #define CS5536_PM1_STS … #define CS5536_PM1_EN … #define CS5536_PM1_CNT … #define CS5536_PM_GPE0_STS … #define CS5536_PM_GPE0_EN … /* CS5536_PM1_STS bits */ #define CS5536_WAK_FLAG … #define CS5536_RTC_FLAG … #define CS5536_PWRBTN_FLAG … /* CS5536_PM1_EN bits */ #define CS5536_PM_PWRBTN … #define CS5536_PM_RTC … /* CS5536_PM_GPE0_STS bits */ #define CS5536_GPIOM7_PME_FLAG … #define CS5536_GPIOM6_PME_FLAG … /* CS5536_PM_GPE0_EN bits */ #define CS5536_GPIOM7_PME_EN … #define CS5536_GPIOM6_PME_EN … /* VSA2 magic values */ #define VSA_VRC_INDEX … #define VSA_VRC_DATA … #define VSA_VR_UNLOCK … #define VSA_VR_SIGNATURE … #define VSA_VR_MEM_SIZE … #define AMD_VSA_SIG … #define GSW_VSA_SIG … #include <linux/io.h> static inline int cs5535_has_vsa2(void) { … } /* GPIOs */ #define GPIO_OUTPUT_VAL … #define GPIO_OUTPUT_ENABLE … #define GPIO_OUTPUT_OPEN_DRAIN … #define GPIO_OUTPUT_INVERT … #define GPIO_OUTPUT_AUX1 … #define GPIO_OUTPUT_AUX2 … #define GPIO_PULL_UP … #define GPIO_PULL_DOWN … #define GPIO_INPUT_ENABLE … #define GPIO_INPUT_INVERT … #define GPIO_INPUT_FILTER … #define GPIO_INPUT_EVENT_COUNT … #define GPIO_READ_BACK … #define GPIO_INPUT_AUX1 … #define GPIO_EVENTS_ENABLE … #define GPIO_LOCK_ENABLE … #define GPIO_POSITIVE_EDGE_EN … #define GPIO_NEGATIVE_EDGE_EN … #define GPIO_POSITIVE_EDGE_STS … #define GPIO_NEGATIVE_EDGE_STS … #define GPIO_FLTR7_AMOUNT … #define GPIO_MAP_X … #define GPIO_MAP_Y … #define GPIO_MAP_Z … #define GPIO_MAP_W … #define GPIO_FE7_SEL … void cs5535_gpio_set(unsigned offset, unsigned int reg); void cs5535_gpio_clear(unsigned offset, unsigned int reg); int cs5535_gpio_isset(unsigned offset, unsigned int reg); int cs5535_gpio_set_irq(unsigned group, unsigned irq); void cs5535_gpio_setup_event(unsigned offset, int pair, int pme); /* MFGPTs */ #define MFGPT_MAX_TIMERS … #define MFGPT_TIMER_ANY … #define MFGPT_DOMAIN_WORKING … #define MFGPT_DOMAIN_STANDBY … #define MFGPT_DOMAIN_ANY … #define MFGPT_CMP1 … #define MFGPT_CMP2 … #define MFGPT_EVENT_IRQ … #define MFGPT_EVENT_NMI … #define MFGPT_EVENT_RESET … #define MFGPT_REG_CMP1 … #define MFGPT_REG_CMP2 … #define MFGPT_REG_COUNTER … #define MFGPT_REG_SETUP … #define MFGPT_SETUP_CNTEN … #define MFGPT_SETUP_CMP2 … #define MFGPT_SETUP_CMP1 … #define MFGPT_SETUP_SETUP … #define MFGPT_SETUP_STOPEN … #define MFGPT_SETUP_EXTEN … #define MFGPT_SETUP_REVEN … #define MFGPT_SETUP_CLKSEL … struct cs5535_mfgpt_timer; extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg); extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, uint16_t value); extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp, int event, int enable); extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq, int enable); extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer, int domain); extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer); static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq) { … } static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq) { … } #endif
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