// SPDX-License-Identifier: GPL-2.0 /* * TSC frequency enumeration via MSR * * Copyright (C) 2013, 2018 Intel Corporation * Author: Bin Gao <[email protected]> */ #include <linux/kernel.h> #include <linux/thread_info.h> #include <asm/apic.h> #include <asm/cpu_device_id.h> #include <asm/intel-family.h> #include <asm/msr.h> #include <asm/param.h> #include <asm/tsc.h> #define MAX_NUM_FREQS … /* * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is * unclear if the root PLL outputs are used directly by the CPU clock PLL or * if there is another PLL in between. * This does not matter though, we can model the chain of PLLs as a single PLL * with a quotient equal to the quotients of all PLLs in the chain multiplied. * So we can create a simplified model of the CPU clock setup using a reference * clock of 100 MHz plus a quotient which gets us as close to the frequency * from the SDM as possible. * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 = * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw. */ #define TSC_REFERENCE_KHZ … struct muldiv { … }; /* * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. * Unfortunately some Intel Atom SoCs aren't quite compliant to this, * so we need manually differentiate SoC families. This is what the * field use_msr_plat does. */ struct freq_desc { … }; /* * Penwell and Clovertrail use spread spectrum clock, * so the freq number is not exactly the same as reported * by MSR based on SDM. */ static const struct freq_desc freq_desc_pnw = …; static const struct freq_desc freq_desc_clv = …; /* * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: * 000: 100 * 5 / 6 = 83.3333 MHz * 001: 100 * 1 / 1 = 100.0000 MHz * 010: 100 * 4 / 3 = 133.3333 MHz * 011: 100 * 7 / 6 = 116.6667 MHz * 100: 100 * 4 / 5 = 80.0000 MHz */ static const struct freq_desc freq_desc_byt = …; /* * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: * 0000: 100 * 5 / 6 = 83.3333 MHz * 0001: 100 * 1 / 1 = 100.0000 MHz * 0010: 100 * 4 / 3 = 133.3333 MHz * 0011: 100 * 7 / 6 = 116.6667 MHz * 0100: 100 * 4 / 5 = 80.0000 MHz * 0101: 100 * 14 / 15 = 93.3333 MHz * 0110: 100 * 9 / 10 = 90.0000 MHz * 0111: 100 * 8 / 9 = 88.8889 MHz * 1000: 100 * 7 / 8 = 87.5000 MHz */ static const struct freq_desc freq_desc_cht = …; /* * Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model: * 0001: 100 * 1 / 1 = 100.0000 MHz * 0010: 100 * 4 / 3 = 133.3333 MHz */ static const struct freq_desc freq_desc_tng = …; /* * Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model: * 0000: 100 * 5 / 6 = 83.3333 MHz * 0001: 100 * 1 / 1 = 100.0000 MHz * 0010: 100 * 4 / 3 = 133.3333 MHz * 0011: 100 * 1 / 1 = 100.0000 MHz */ static const struct freq_desc freq_desc_ann = …; /* * 24 MHz crystal? : 24 * 13 / 4 = 78 MHz * Frequency step for Lightning Mountain SoC is fixed to 78 MHz, * so all the frequency entries are 78000. */ static const struct freq_desc freq_desc_lgm = …; static const struct x86_cpu_id tsc_msr_cpu_ids[] = …; /* * MSR-based CPU/TSC frequency discovery for certain CPUs. * * Set global "lapic_timer_period" to bus_clock_cycles/jiffy * Return processor base frequency in KHz, or 0 on failure. */ unsigned long cpu_khz_from_msr(void) { … }
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