/* SPDX-License-Identifier: GPL-2.0 */ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ #include <linux/platform_device.h> #include <linux/platform_data/brcmnand.h> #include <linux/gpio/driver.h> /** ChipCommon core registers. **/ #define BCMA_CC_ID … #define BCMA_CC_ID_ID … #define BCMA_CC_ID_ID_SHIFT … #define BCMA_CC_ID_REV … #define BCMA_CC_ID_REV_SHIFT … #define BCMA_CC_ID_PKG … #define BCMA_CC_ID_PKG_SHIFT … #define BCMA_CC_ID_NRCORES … #define BCMA_CC_ID_NRCORES_SHIFT … #define BCMA_CC_ID_TYPE … #define BCMA_CC_ID_TYPE_SHIFT … #define BCMA_CC_CAP … #define BCMA_CC_CAP_NRUART … #define BCMA_CC_CAP_MIPSEB … #define BCMA_CC_CAP_UARTCLK … #define BCMA_CC_CAP_UARTCLK_INT … #define BCMA_CC_CAP_UARTGPIO … #define BCMA_CC_CAP_EXTBUS … #define BCMA_CC_CAP_FLASHT … #define BCMA_CC_FLASHT_NONE … #define BCMA_CC_FLASHT_STSER … #define BCMA_CC_FLASHT_ATSER … #define BCMA_CC_FLASHT_NAND … #define BCMA_CC_FLASHT_PARA … #define BCMA_CC_CAP_PLLT … #define BCMA_PLLTYPE_NONE … #define BCMA_PLLTYPE_1 … #define BCMA_PLLTYPE_2 … #define BCMA_PLLTYPE_3 … #define BCMA_PLLTYPE_4 … #define BCMA_PLLTYPE_5 … #define BCMA_PLLTYPE_6 … #define BCMA_PLLTYPE_7 … #define BCMA_CC_CAP_PCTL … #define BCMA_CC_CAP_OTPS … #define BCMA_CC_CAP_OTPS_SHIFT … #define BCMA_CC_CAP_OTPS_BASE … #define BCMA_CC_CAP_JTAGM … #define BCMA_CC_CAP_BROM … #define BCMA_CC_CAP_64BIT … #define BCMA_CC_CAP_PMU … #define BCMA_CC_CAP_ECI … #define BCMA_CC_CAP_SPROM … #define BCMA_CC_CAP_NFLASH … #define BCMA_CC_CORECTL … #define BCMA_CC_CORECTL_UARTCLK0 … #define BCMA_CC_CORECTL_SE … #define BCMA_CC_CORECTL_UARTCLKEN … #define BCMA_CC_BIST … #define BCMA_CC_OTPS … #define BCMA_CC_OTPS_PROGFAIL … #define BCMA_CC_OTPS_PROTECT … #define BCMA_CC_OTPS_HW_PROTECT … #define BCMA_CC_OTPS_SW_PROTECT … #define BCMA_CC_OTPS_CID_PROTECT … #define BCMA_CC_OTPS_GU_PROG_IND … #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT … #define BCMA_CC_OTPS_GU_PROG_HW … #define BCMA_CC_OTPC … #define BCMA_CC_OTPC_RECWAIT … #define BCMA_CC_OTPC_PROGWAIT … #define BCMA_CC_OTPC_PRW_SHIFT … #define BCMA_CC_OTPC_MAXFAIL … #define BCMA_CC_OTPC_VSEL … #define BCMA_CC_OTPC_SELVL … #define BCMA_CC_OTPP … #define BCMA_CC_OTPP_COL … #define BCMA_CC_OTPP_ROW … #define BCMA_CC_OTPP_ROW_SHIFT … #define BCMA_CC_OTPP_READERR … #define BCMA_CC_OTPP_VALUE … #define BCMA_CC_OTPP_READ … #define BCMA_CC_OTPP_START … #define BCMA_CC_OTPP_BUSY … #define BCMA_CC_OTPL … #define BCMA_CC_OTPL_GURGN_OFFSET … #define BCMA_CC_IRQSTAT … #define BCMA_CC_IRQMASK … #define BCMA_CC_IRQ_GPIO … #define BCMA_CC_IRQ_EXT … #define BCMA_CC_IRQ_WDRESET … #define BCMA_CC_CHIPCTL … #define BCMA_CC_CHIPSTAT … #define BCMA_CC_CHIPST_4313_SPROM_PRESENT … #define BCMA_CC_CHIPST_4313_OTP_PRESENT … #define BCMA_CC_CHIPST_4331_SPROM_PRESENT … #define BCMA_CC_CHIPST_4331_OTP_PRESENT … #define BCMA_CC_CHIPST_43228_ILP_DIV_EN … #define BCMA_CC_CHIPST_43228_OTP_PRESENT … #define BCMA_CC_CHIPST_43228_SERDES_REFCLK_PADSEL … #define BCMA_CC_CHIPST_43228_SDIO_MODE … #define BCMA_CC_CHIPST_43228_SDIO_OTP_PRESENT … #define BCMA_CC_CHIPST_43228_SDIO_RESET … #define BCMA_CC_CHIPST_4706_PKG_OPTION … #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT … #define BCMA_CC_CHIPST_4706_SFLASH_TYPE … #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN … #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE … #define BCMA_CC_CHIPST_5357_NAND_BOOT … #define BCMA_CC_CHIPST_4360_XTAL_40MZ … #define BCMA_CC_JCMD … #define BCMA_CC_JCMD_START … #define BCMA_CC_JCMD_BUSY … #define BCMA_CC_JCMD_PAUSE … #define BCMA_CC_JCMD0_ACC_MASK … #define BCMA_CC_JCMD0_ACC_IRDR … #define BCMA_CC_JCMD0_ACC_DR … #define BCMA_CC_JCMD0_ACC_IR … #define BCMA_CC_JCMD0_ACC_RESET … #define BCMA_CC_JCMD0_ACC_IRPDR … #define BCMA_CC_JCMD0_ACC_PDR … #define BCMA_CC_JCMD0_IRW_MASK … #define BCMA_CC_JCMD_ACC_MASK … #define BCMA_CC_JCMD_ACC_IRDR … #define BCMA_CC_JCMD_ACC_DR … #define BCMA_CC_JCMD_ACC_IR … #define BCMA_CC_JCMD_ACC_RESET … #define BCMA_CC_JCMD_ACC_IRPDR … #define BCMA_CC_JCMD_ACC_PDR … #define BCMA_CC_JCMD_IRW_MASK … #define BCMA_CC_JCMD_IRW_SHIFT … #define BCMA_CC_JCMD_DRW_MASK … #define BCMA_CC_JIR … #define BCMA_CC_JDR … #define BCMA_CC_JCTL … #define BCMA_CC_JCTL_FORCE_CLK … #define BCMA_CC_JCTL_EXT_EN … #define BCMA_CC_JCTL_EN … #define BCMA_CC_FLASHCTL … /* Start/busy bit in flashcontrol */ #define BCMA_CC_FLASHCTL_OPCODE … #define BCMA_CC_FLASHCTL_ACTION … #define BCMA_CC_FLASHCTL_CS_ACTIVE … #define BCMA_CC_FLASHCTL_START … #define BCMA_CC_FLASHCTL_BUSY … /* Flashcontrol action + opcodes for ST flashes */ #define BCMA_CC_FLASHCTL_ST_WREN … #define BCMA_CC_FLASHCTL_ST_WRDIS … #define BCMA_CC_FLASHCTL_ST_RDSR … #define BCMA_CC_FLASHCTL_ST_WRSR … #define BCMA_CC_FLASHCTL_ST_READ … #define BCMA_CC_FLASHCTL_ST_PP … #define BCMA_CC_FLASHCTL_ST_SE … #define BCMA_CC_FLASHCTL_ST_BE … #define BCMA_CC_FLASHCTL_ST_DP … #define BCMA_CC_FLASHCTL_ST_RES … #define BCMA_CC_FLASHCTL_ST_CSA … #define BCMA_CC_FLASHCTL_ST_SSE … /* Flashcontrol action + opcodes for Atmel flashes */ #define BCMA_CC_FLASHCTL_AT_READ … #define BCMA_CC_FLASHCTL_AT_PAGE_READ … #define BCMA_CC_FLASHCTL_AT_STATUS … #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE … #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE … #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM … #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE … #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE … #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD … #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD … #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE … #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE … #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM … #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM … #define BCMA_CC_FLASHADDR … #define BCMA_CC_FLASHDATA … /* Status register bits for ST flashes */ #define BCMA_CC_FLASHDATA_ST_WIP … #define BCMA_CC_FLASHDATA_ST_WEL … #define BCMA_CC_FLASHDATA_ST_BP_MASK … #define BCMA_CC_FLASHDATA_ST_BP_SHIFT … #define BCMA_CC_FLASHDATA_ST_SRWD … /* Status register bits for Atmel flashes */ #define BCMA_CC_FLASHDATA_AT_READY … #define BCMA_CC_FLASHDATA_AT_MISMATCH … #define BCMA_CC_FLASHDATA_AT_ID_MASK … #define BCMA_CC_FLASHDATA_AT_ID_SHIFT … #define BCMA_CC_BCAST_ADDR … #define BCMA_CC_BCAST_DATA … #define BCMA_CC_GPIOPULLUP … #define BCMA_CC_GPIOPULLDOWN … #define BCMA_CC_GPIOIN … #define BCMA_CC_GPIOOUT … #define BCMA_CC_GPIOOUTEN … #define BCMA_CC_GPIOCTL … #define BCMA_CC_GPIOPOL … #define BCMA_CC_GPIOIRQ … #define BCMA_CC_WATCHDOG … #define BCMA_CC_GPIOTIMER … #define BCMA_CC_GPIOTIMER_OFFTIME … #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT … #define BCMA_CC_GPIOTIMER_ONTIME … #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT … #define BCMA_CC_GPIOTOUTM … #define BCMA_CC_CLOCK_N … #define BCMA_CC_CLOCK_SB … #define BCMA_CC_CLOCK_PCI … #define BCMA_CC_CLOCK_M2 … #define BCMA_CC_CLOCK_MIPS … #define BCMA_CC_CLKDIV … #define BCMA_CC_CLKDIV_SFLASH … #define BCMA_CC_CLKDIV_SFLASH_SHIFT … #define BCMA_CC_CLKDIV_OTP … #define BCMA_CC_CLKDIV_OTP_SHIFT … #define BCMA_CC_CLKDIV_JTAG … #define BCMA_CC_CLKDIV_JTAG_SHIFT … #define BCMA_CC_CLKDIV_UART … #define BCMA_CC_CAP_EXT … #define BCMA_CC_CAP_EXT_SECI_PRESENT … #define BCMA_CC_CAP_EXT_GSIO_PRESENT … #define BCMA_CC_CAP_EXT_GCI_PRESENT … #define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT … #define BCMA_CC_CAP_EXT_AOB_PRESENT … #define BCMA_CC_PLLONDELAY … #define BCMA_CC_FREFSELDELAY … #define BCMA_CC_SLOWCLKCTL … #define BCMA_CC_SLOWCLKCTL_SRC … #define BCMA_CC_SLOWCLKCTL_SRC_LPO … #define BCMA_CC_SLOWCLKCTL_SRC_XTAL … #define BCMA_CC_SLOECLKCTL_SRC_PCI … #define BCMA_CC_SLOWCLKCTL_LPOFREQ … #define BCMA_CC_SLOWCLKCTL_LPOPD … #define BCMA_CC_SLOWCLKCTL_FSLOW … #define BCMA_CC_SLOWCLKCTL_IPLL … #define BCMA_CC_SLOWCLKCTL_ENXTAL … #define BCMA_CC_SLOWCLKCTL_XTALPU … #define BCMA_CC_SLOWCLKCTL_CLKDIV … #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT … #define BCMA_CC_SYSCLKCTL … #define BCMA_CC_SYSCLKCTL_IDLPEN … #define BCMA_CC_SYSCLKCTL_ALPEN … #define BCMA_CC_SYSCLKCTL_PLLEN … #define BCMA_CC_SYSCLKCTL_FORCEALP … #define BCMA_CC_SYSCLKCTL_FORCEHT … #define BCMA_CC_SYSCLKCTL_CLKDIV … #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT … #define BCMA_CC_CLKSTSTR … #define BCMA_CC_EROM … #define BCMA_CC_PCMCIA_CFG … #define BCMA_CC_PCMCIA_MEMWAIT … #define BCMA_CC_PCMCIA_ATTRWAIT … #define BCMA_CC_PCMCIA_IOWAIT … #define BCMA_CC_IDE_CFG … #define BCMA_CC_IDE_MEMWAIT … #define BCMA_CC_IDE_ATTRWAIT … #define BCMA_CC_IDE_IOWAIT … #define BCMA_CC_PROG_CFG … #define BCMA_CC_PROG_WAITCNT … #define BCMA_CC_FLASH_CFG … #define BCMA_CC_FLASH_CFG_DS … #define BCMA_CC_FLASH_WAITCNT … #define BCMA_CC_SROM_CONTROL … #define BCMA_CC_SROM_CONTROL_START … #define BCMA_CC_SROM_CONTROL_BUSY … #define BCMA_CC_SROM_CONTROL_OPCODE … #define BCMA_CC_SROM_CONTROL_OP_READ … #define BCMA_CC_SROM_CONTROL_OP_WRITE … #define BCMA_CC_SROM_CONTROL_OP_WRDIS … #define BCMA_CC_SROM_CONTROL_OP_WREN … #define BCMA_CC_SROM_CONTROL_OTPSEL … #define BCMA_CC_SROM_CONTROL_OTP_PRESENT … #define BCMA_CC_SROM_CONTROL_LOCK … #define BCMA_CC_SROM_CONTROL_SIZE_MASK … #define BCMA_CC_SROM_CONTROL_SIZE_1K … #define BCMA_CC_SROM_CONTROL_SIZE_4K … #define BCMA_CC_SROM_CONTROL_SIZE_16K … #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT … #define BCMA_CC_SROM_CONTROL_PRESENT … /* Block 0x140 - 0x190 registers are chipset specific */ #define BCMA_CC_4706_FLASHSCFG … #define BCMA_CC_4706_FLASHSCFG_MASK … #define BCMA_CC_4706_FLASHSCFG_SF1 … #define BCMA_CC_4706_FLASHSCFG_PF1 … #define BCMA_CC_4706_FLASHSCFG_SF1_TYPE … #define BCMA_CC_4706_FLASHSCFG_NF1 … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB … #define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB … /* NAND flash registers for BCM4706 (corerev = 31) */ #define BCMA_CC_NFLASH_CTL … #define BCMA_CC_NFLASH_CTL_ERR … #define BCMA_CC_NFLASH_CONF … #define BCMA_CC_NFLASH_COL_ADDR … #define BCMA_CC_NFLASH_ROW_ADDR … #define BCMA_CC_NFLASH_DATA … #define BCMA_CC_NFLASH_WAITCNT0 … /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND … #define BCMA_CC_UART0_DATA … #define BCMA_CC_UART0_IMR … #define BCMA_CC_UART0_FCR … #define BCMA_CC_UART0_LCR … #define BCMA_CC_UART0_MCR … #define BCMA_CC_UART0_LSR … #define BCMA_CC_UART0_MSR … #define BCMA_CC_UART0_SCRATCH … #define BCMA_CC_UART1_DATA … #define BCMA_CC_UART1_IMR … #define BCMA_CC_UART1_FCR … #define BCMA_CC_UART1_LCR … #define BCMA_CC_UART1_MCR … #define BCMA_CC_UART1_LSR … #define BCMA_CC_UART1_MSR … #define BCMA_CC_UART1_SCRATCH … /* PMU registers (rev >= 20) */ #define BCMA_CC_PMU_CTL … #define BCMA_CC_PMU_CTL_ILP_DIV … #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT … #define BCMA_CC_PMU_CTL_RES … #define BCMA_CC_PMU_CTL_RES_SHIFT … #define BCMA_CC_PMU_CTL_RES_RELOAD … #define BCMA_CC_PMU_CTL_PLL_UPD … #define BCMA_CC_PMU_CTL_NOILPONW … #define BCMA_CC_PMU_CTL_HTREQEN … #define BCMA_CC_PMU_CTL_ALPREQEN … #define BCMA_CC_PMU_CTL_XTALFREQ … #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT … #define BCMA_CC_PMU_CTL_ILPDIVEN … #define BCMA_CC_PMU_CTL_LPOSEL … #define BCMA_CC_PMU_CAP … #define BCMA_CC_PMU_CAP_REVISION … #define BCMA_CC_PMU_STAT … #define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL … #define BCMA_CC_PMU_STAT_WDRESET … #define BCMA_CC_PMU_STAT_INTPEND … #define BCMA_CC_PMU_STAT_SBCLKST … #define BCMA_CC_PMU_STAT_HAVEALP … #define BCMA_CC_PMU_STAT_HAVEHT … #define BCMA_CC_PMU_STAT_RESINIT … #define BCMA_CC_PMU_RES_STAT … #define BCMA_CC_PMU_RES_PEND … #define BCMA_CC_PMU_TIMER … #define BCMA_CC_PMU_MINRES_MSK … #define BCMA_CC_PMU_MAXRES_MSK … #define BCMA_CC_PMU_RES_TABSEL … #define BCMA_CC_PMU_RES_DEPMSK … #define BCMA_CC_PMU_RES_UPDNTM … #define BCMA_CC_PMU_RES_TIMER … #define BCMA_CC_PMU_CLKSTRETCH … #define BCMA_CC_PMU_WATCHDOG … #define BCMA_CC_PMU_RES_REQTS … #define BCMA_CC_PMU_RES_REQT … #define BCMA_CC_PMU_RES_REQM … #define BCMA_CC_PMU_CHIPCTL_ADDR … #define BCMA_CC_PMU_CHIPCTL_DATA … #define BCMA_CC_PMU_REGCTL_ADDR … #define BCMA_CC_PMU_REGCTL_DATA … #define BCMA_CC_PMU_PLLCTL_ADDR … #define BCMA_CC_PMU_PLLCTL_DATA … #define BCMA_CC_PMU_STRAPOPT … #define BCMA_CC_PMU_XTAL_FREQ … #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK … #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK … #define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT … #define BCMA_CC_SPROM … /* NAND flash MLC controller registers (corerev >= 38) */ #define BCMA_CC_NAND_REVISION … #define BCMA_CC_NAND_CMD_START … #define BCMA_CC_NAND_CMD_ADDR_X … #define BCMA_CC_NAND_CMD_ADDR … #define BCMA_CC_NAND_CMD_END_ADDR … #define BCMA_CC_NAND_CS_NAND_SELECT … #define BCMA_CC_NAND_CS_NAND_XOR … #define BCMA_CC_NAND_SPARE_RD0 … #define BCMA_CC_NAND_SPARE_RD4 … #define BCMA_CC_NAND_SPARE_RD8 … #define BCMA_CC_NAND_SPARE_RD12 … #define BCMA_CC_NAND_SPARE_WR0 … #define BCMA_CC_NAND_SPARE_WR4 … #define BCMA_CC_NAND_SPARE_WR8 … #define BCMA_CC_NAND_SPARE_WR12 … #define BCMA_CC_NAND_ACC_CONTROL … #define BCMA_CC_NAND_CONFIG … #define BCMA_CC_NAND_TIMING_1 … #define BCMA_CC_NAND_TIMING_2 … #define BCMA_CC_NAND_SEMAPHORE … #define BCMA_CC_NAND_DEVID … #define BCMA_CC_NAND_DEVID_X … #define BCMA_CC_NAND_BLOCK_LOCK_STATUS … #define BCMA_CC_NAND_INTFC_STATUS … #define BCMA_CC_NAND_ECC_CORR_ADDR_X … #define BCMA_CC_NAND_ECC_CORR_ADDR … #define BCMA_CC_NAND_ECC_UNC_ADDR_X … #define BCMA_CC_NAND_ECC_UNC_ADDR … #define BCMA_CC_NAND_READ_ERROR_COUNT … #define BCMA_CC_NAND_CORR_STAT_THRESHOLD … #define BCMA_CC_NAND_READ_ADDR_X … #define BCMA_CC_NAND_READ_ADDR … #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X … #define BCMA_CC_NAND_PAGE_PROGRAM_ADDR … #define BCMA_CC_NAND_COPY_BACK_ADDR_X … #define BCMA_CC_NAND_COPY_BACK_ADDR … #define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X … #define BCMA_CC_NAND_BLOCK_ERASE_ADDR … #define BCMA_CC_NAND_INV_READ_ADDR_X … #define BCMA_CC_NAND_INV_READ_ADDR … #define BCMA_CC_NAND_BLK_WR_PROTECT … #define BCMA_CC_NAND_ACC_CONTROL_CS1 … #define BCMA_CC_NAND_CONFIG_CS1 … #define BCMA_CC_NAND_TIMING_1_CS1 … #define BCMA_CC_NAND_TIMING_2_CS1 … #define BCMA_CC_NAND_SPARE_RD16 … #define BCMA_CC_NAND_SPARE_RD20 … #define BCMA_CC_NAND_SPARE_RD24 … #define BCMA_CC_NAND_SPARE_RD28 … #define BCMA_CC_NAND_CACHE_ADDR … #define BCMA_CC_NAND_CACHE_DATA … #define BCMA_CC_NAND_CTRL_CONFIG … #define BCMA_CC_NAND_CTRL_STATUS … /* Divider allocation in 4716/47162/5356 */ #define BCMA_CC_PMU5_MAINPLL_CPU … #define BCMA_CC_PMU5_MAINPLL_MEM … #define BCMA_CC_PMU5_MAINPLL_SSB … /* PLL usage in 4716/47162 */ #define BCMA_CC_PMU4716_MAINPLL_PLL0 … /* PLL usage in 5356/5357 */ #define BCMA_CC_PMU5356_MAINPLL_PLL0 … #define BCMA_CC_PMU5357_MAINPLL_PLL0 … /* 4706 PMU */ #define BCMA_CC_PMU4706_MAINPLL_PLL0 … #define BCMA_CC_PMU6_4706_PROCPLL_OFF … #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK … #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT … #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK … #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT … #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK … #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT … #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK … #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT … /* PMU rev 15 */ #define BCMA_CC_PMU15_PLL_PLLCTL0 … #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK … #define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK … #define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK … #define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK … #define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK … #define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK … #define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT … #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK … #define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT … /* ALP clock on pre-PMU chips */ #define BCMA_CC_PMU_ALP_CLOCK … /* HT clock for systems with PMU-enabled chipcommon */ #define BCMA_CC_PMU_HT_CLOCK … /* PMU rev 5 (& 6) */ #define BCMA_CC_PPL_P1P2_OFF … #define BCMA_CC_PPL_P1_MASK … #define BCMA_CC_PPL_P1_SHIFT … #define BCMA_CC_PPL_P2_MASK … #define BCMA_CC_PPL_P2_SHIFT … #define BCMA_CC_PPL_M14_OFF … #define BCMA_CC_PPL_MDIV_MASK … #define BCMA_CC_PPL_MDIV_WIDTH … #define BCMA_CC_PPL_NM5_OFF … #define BCMA_CC_PPL_NDIV_MASK … #define BCMA_CC_PPL_NDIV_SHIFT … #define BCMA_CC_PPL_FMAB_OFF … #define BCMA_CC_PPL_MRAT_MASK … #define BCMA_CC_PPL_MRAT_SHIFT … #define BCMA_CC_PPL_ABRAT_MASK … #define BCMA_CC_PPL_ABRAT_SHIFT … #define BCMA_CC_PPL_FDIV_MASK … #define BCMA_CC_PPL_PLLCTL_OFF … #define BCMA_CC_PPL_PCHI_OFF … #define BCMA_CC_PPL_PCHI_MASK … #define BCMA_CC_PMU_PLL_CTL0 … #define BCMA_CC_PMU_PLL_CTL1 … #define BCMA_CC_PMU_PLL_CTL2 … #define BCMA_CC_PMU_PLL_CTL3 … #define BCMA_CC_PMU_PLL_CTL4 … #define BCMA_CC_PMU_PLL_CTL5 … #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK … #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT … #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK … #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT … #define BCMA_CCB_MII_MNG_CTL … #define BCMA_CCB_MII_MNG_CMD_DATA … /* BCM4331 ChipControl numbers. */ #define BCMA_CHIPCTL_4331_BT_COEXIST … #define BCMA_CHIPCTL_4331_SECI … #define BCMA_CHIPCTL_4331_EXT_LNA … #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 … #define BCMA_CHIPCTL_4331_EXTPA_EN … #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS … #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS … #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 … #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN … #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN … #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN … #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN … #define BCMA_CHIPCTL_4331_EXTPA_EN2 … #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 … #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 … /* 43224 chip-specific ChipControl register bits */ #define BCMA_CCTRL_43224_GPIO_TOGGLE … #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE … #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE … /* 4313 Chip specific ChipControl register bits */ #define BCMA_CCTRL_4313_12MA_LED_DRIVE … /* BCM5357 ChipControl register bits */ #define BCMA_CHIPCTL_5357_EXTPA … #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 … #define BCMA_CHIPCTL_5357_NFLASH … #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE … #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE … #define BCMA_RES_4314_LPLDO_PU … #define BCMA_RES_4314_PMU_SLEEP_DIS … #define BCMA_RES_4314_PMU_BG_PU … #define BCMA_RES_4314_CBUCK_LPOM_PU … #define BCMA_RES_4314_CBUCK_PFM_PU … #define BCMA_RES_4314_CLDO_PU … #define BCMA_RES_4314_LPLDO2_LVM … #define BCMA_RES_4314_WL_PMU_PU … #define BCMA_RES_4314_LNLDO_PU … #define BCMA_RES_4314_LDO3P3_PU … #define BCMA_RES_4314_OTP_PU … #define BCMA_RES_4314_XTAL_PU … #define BCMA_RES_4314_WL_PWRSW_PU … #define BCMA_RES_4314_LQ_AVAIL … #define BCMA_RES_4314_LOGIC_RET … #define BCMA_RES_4314_MEM_SLEEP … #define BCMA_RES_4314_MACPHY_RET … #define BCMA_RES_4314_WL_CORE_READY … #define BCMA_RES_4314_ILP_REQ … #define BCMA_RES_4314_ALP_AVAIL … #define BCMA_RES_4314_MISC_PWRSW_PU … #define BCMA_RES_4314_SYNTH_PWRSW_PU … #define BCMA_RES_4314_RX_PWRSW_PU … #define BCMA_RES_4314_RADIO_PU … #define BCMA_RES_4314_VCO_LDO_PU … #define BCMA_RES_4314_AFE_LDO_PU … #define BCMA_RES_4314_RX_LDO_PU … #define BCMA_RES_4314_TX_LDO_PU … #define BCMA_RES_4314_HT_AVAIL … #define BCMA_RES_4314_MACPHY_CLK_AVAIL … /* Data for the PMU, if available. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) */ struct bcma_chipcommon_pmu { … }; #ifdef CONFIG_BCMA_PFLASH struct bcma_pflash { … }; #endif #ifdef CONFIG_BCMA_SFLASH struct mtd_info; struct bcma_sflash { … }; #endif #ifdef CONFIG_BCMA_NFLASH struct bcma_nflash { … }; #endif #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_serial_port { … }; #endif /* CONFIG_BCMA_DRIVER_MIPS */ struct bcma_drv_cc { … }; struct bcma_drv_cc_b { … }; /* Register access */ #define bcma_cc_read32(cc, offset) … #define bcma_cc_write32(cc, offset, val) … #define bcma_cc_mask32(cc, offset, mask) … #define bcma_cc_set32(cc, offset, set) … #define bcma_cc_maskset32(cc, offset, mask, set) … /* PMU registers access */ #define bcma_pmu_read32(cc, offset) … #define bcma_pmu_write32(cc, offset, val) … #define bcma_pmu_mask32(cc, offset, mask) … #define bcma_pmu_set32(cc, offset, set) … #define bcma_pmu_maskset32(cc, offset, mask, set) … extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); /* Chipcommon GPIO pin access. */ u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); /* PMU support */ extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value); extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set); extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set); extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set); extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc); void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value); #endif /* LINUX_BCMA_DRIVER_CC_H_ */
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