linux/drivers/gpu/drm/amd/amdgpu/nv.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <drm/amdgpu_drm.h>

#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "amdgpu_ih.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_ucode.h"
#include "amdgpu_psp.h"
#include "atom.h"
#include "amd_pcie.h"

#include "gc/gc_10_1_0_offset.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "mp/mp_11_0_offset.h"

#include "soc15.h"
#include "soc15_common.h"
#include "gmc_v10_0.h"
#include "gfxhub_v2_0.h"
#include "mmhub_v2_0.h"
#include "nbio_v2_3.h"
#include "nbio_v7_2.h"
#include "hdp_v5_0.h"
#include "nv.h"
#include "navi10_ih.h"
#include "gfx_v10_0.h"
#include "sdma_v5_0.h"
#include "sdma_v5_2.h"
#include "vcn_v2_0.h"
#include "jpeg_v2_0.h"
#include "vcn_v3_0.h"
#include "jpeg_v3_0.h"
#include "amdgpu_vkms.h"
#include "mxgpu_nv.h"
#include "smuio_v11_0.h"
#include "smuio_v11_0_6.h"

static const struct amd_ip_funcs nv_common_ip_funcs;

/* Navi */
static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = …;

static const struct amdgpu_video_codecs nv_video_codecs_encode = …;

/* Navi1x */
static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs nv_video_codecs_decode = …;

/* Sienna Cichlid */
static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = …;

static const struct amdgpu_video_codecs sc_video_codecs_encode = …;

static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = …;

static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = …;

static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = …;

static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = …;

/* SRIOV Sienna Cichlid, not const since data is controlled by host */
static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = …;

static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = …;

static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = …;

static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = …;

static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = …;

static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = …;

/* Beige Goby*/
static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs bg_video_codecs_decode = …;

static const struct amdgpu_video_codecs bg_video_codecs_encode = …;

/* Yellow Carp*/
static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = …;

static const struct amdgpu_video_codecs yc_video_codecs_decode = …;

static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
				 const struct amdgpu_video_codecs **codecs)
{ … }

static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 nv_get_config_memsize(struct amdgpu_device *adev)
{ … }

static u32 nv_get_xclk(struct amdgpu_device *adev)
{ … }


void nv_grbm_select(struct amdgpu_device *adev,
		     u32 me, u32 pipe, u32 queue, u32 vmid)
{ … }

static bool nv_read_disabled_bios(struct amdgpu_device *adev)
{ … }

static struct soc15_allowed_register_entry nv_allowed_read_registers[] = …;

static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
					 u32 sh_num, u32 reg_offset)
{ … }

static uint32_t nv_get_register_value(struct amdgpu_device *adev,
				      bool indexed, u32 se_num,
				      u32 sh_num, u32 reg_offset)
{ … }

static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
			    u32 sh_num, u32 reg_offset, u32 *value)
{ … }

static int nv_asic_mode2_reset(struct amdgpu_device *adev)
{ … }

static enum amd_reset_method
nv_asic_reset_method(struct amdgpu_device *adev)
{ … }

static int nv_asic_reset(struct amdgpu_device *adev)
{ … }

static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{ … }

static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
{ … }

static void nv_program_aspm(struct amdgpu_device *adev)
{ … }

const struct amdgpu_ip_block_version nv_common_ip_block = …;

void nv_set_virt_ops(struct amdgpu_device *adev)
{ … }

static bool nv_need_full_reset(struct amdgpu_device *adev)
{ … }

static bool nv_need_reset_on_init(struct amdgpu_device *adev)
{ … }

static void nv_init_doorbell_index(struct amdgpu_device *adev)
{ … }

static void nv_pre_asic_init(struct amdgpu_device *adev)
{ … }

static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
				       bool enter)
{ … }

static const struct amdgpu_asic_funcs nv_asic_funcs = …;

static int nv_common_early_init(void *handle)
{ … }

static int nv_common_late_init(void *handle)
{ … }

static int nv_common_sw_init(void *handle)
{ … }

static int nv_common_sw_fini(void *handle)
{ … }

static int nv_common_hw_init(void *handle)
{ … }

static int nv_common_hw_fini(void *handle)
{ … }

static int nv_common_suspend(void *handle)
{ … }

static int nv_common_resume(void *handle)
{ … }

static bool nv_common_is_idle(void *handle)
{ … }

static int nv_common_wait_for_idle(void *handle)
{ … }

static int nv_common_soft_reset(void *handle)
{ … }

static int nv_common_set_clockgating_state(void *handle,
					   enum amd_clockgating_state state)
{ … }

static int nv_common_set_powergating_state(void *handle,
					   enum amd_powergating_state state)
{ … }

static void nv_common_get_clockgating_state(void *handle, u64 *flags)
{ … }

static const struct amd_ip_funcs nv_common_ip_funcs = …;